CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

Data sheet acquired from Harris Semiconductor SCHS129F

January 1998 - Revised May 2005

High-Speed CMOS Logic Hex Inverting Schmitt Trigger

Description
The HC14 and HCT14 each contain six inverting Schmitt triggers in one package.

Features
Unlimited Input Rise and Fall Times

[ /Title (CD74H C14, CD74H CT14) /Subject (High Speed CMOS Logic Hex Invert-

Exceptionally High Noise Immunity Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - CMOS Input Compatibility, Il 1A at VOL, VOH

Ordering Information
PART NUMBER CD54HC14F3A CD54HCT14F3A CD74HC14E CD74HC14M CD74HC14MT CD74HC14M96 CD74HC14PW CD74HC14PWR CD74HCT14E CD74HCT14M CD74HCT14MT CD74HCT14M96 CD74HCT14PW CD74HCT14PWR TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufx 96 denotes tape and reel. The sufx T denotes a small-quantity reel of 250.

Pinout
CD54HC14, CD54HCT14 (CERDIP) CD74HC14, CD74HCT14 (PDIP, SOIC, TSSOP) TOP VIEW
1A 1 1Y 2 2A 3 2Y 4 3A 5 3Y 6 GND 7 14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2005, Texas Instruments Incorporated

CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Functional Diagram

1A 1 2 1Y

2A

2Y

3A

3Y

4A

4Y

5A

11

10

5Y

6A

13

12

6Y GND = 7 VCC = 14

TRUTH TABLE INPUT (A) L H H= High Level L= Low Level OUTPUT (Y) H L

Logic Diagram
nA nY

VO

VH VH = VT+ - VTVI VTV T+ VT+ VT -

VCC VI GND VCC VO GND VH

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

CD54HC14, CD74HC14, CD54HCT, CD74HCT14

Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA

Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES Input Switch Points VT+ 2 4.5 6 VT2 4.5 6 VH 2 4.5 6 High Level Output Voltage CMOS Loads VOH V T-0.02 -0.02 -0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VT+ 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 0.7 1.7 2.1 0.3 0.9 1.2 0.2 0.4 0.6 1.9 4.4 5.9 3.98 5.48 1.5 3.15 4.2 1.0 2.2 3.0 1.0 1.4 1.6 0.1 0.1 0.1 0.26 0.26 0.7 1.7 2.1 0.3 0.9 1.2 0.2 0.4 0.6 1.9 4.4 5.9 3.84 5.34 1.5 3.15 4.2 1.0 2.2 3.0 1.0 1.4 1.6 0.1 0.1 0.1 0.33 0.33 0.7 1.7 2.1 0.3 0.9 1.2 0.2 0.4 0.6 1.9 4.4 5.9 3.7 5.2 1.5 3.15 4.2 1.0 2.2 3.0 1.0 1.4 1.6 0.1 0.1 0.1 0.4 0.4 V V V V V V V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS

CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

DC Electrical Specications
(Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current HCT TYPES Input Switch Points VT+ 4.5 5.5 VT4.5 5.5 VH 4.5 5.5 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VT+ VOH V T-0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.4 1 V V V V V V V V V V A SYMBOL II ICC VI (V) VCC or GND VCC or GND IO (mA) VCC (V) 0 6 6 MIN 25oC MAX 0.1 2 -40oC TO 85oC MIN MAX 1 20 -55oC TO 125oC MIN MAX 1 40 UNITS A A

Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE:

ICC ICC (Note 2)

0 -

5.5 4.5 to 5.5

2 360

20 450

40 490

A A

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT nA UNIT LOADS 0.6

NOTE: Unit Load is ICC limit specied in DC Electrical Specications table, e.g., 360A max at 25oC.

Switching Specications Input tr, tf = 6ns

PARAMETER HC TYPES Propagation Delay, A to Y tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Times tTLH, tTHL CL = 50pF 2 4.5 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, A to Y Output Transition Times Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per inverter. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tPLH, tPHL CL = 50pF CL = 15pF tTLH, tTHL CI CPD CL = 50pF 4.5 5 4.5 5 16 20 38 15 10 48 19 10 57 22 10 ns ns ns pF pF CI CPD 5 11 20 135 27 23 75 15 13 10 170 34 29 95 19 16 10 18 205 41 35 110 22 19 10 ns ns ns ns ns ns ns pF pF SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

Test Circuits and Waveforms

tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V

GND

tTHL

INVERTING OUTPUT

FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

PACKAGING INFORMATION
Orderable Device CD54HC14F CD54HC14F3A CD54HCT14F CD54HCT14F3A CD74HC14E CD74HC14EE4 CD74HC14M CD74HC14M96 CD74HC14M96E4 CD74HC14M96G4 CD74HC14ME4 CD74HC14MG4 CD74HC14MT CD74HC14MTE4 CD74HC14MTG4 CD74HC14PW CD74HC14PWE4 CD74HC14PWG4 CD74HC14PWR CD74HC14PWRE4 CD74HC14PWRG4 CD74HCT14E CD74HCT14EE4 CD74HCT14M CD74HCT14M96 CD74HCT14M96E4 CD74HCT14M96G4 Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP PDIP PDIP SOIC SOIC SOIC SOIC Package Drawing J J J J N N D D D D D D D D D PW PW PW PW PW PW N N D D D D Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 1 1 1 1 25 25 50 TBD TBD TBD TBD Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Lead/Ball Finish A42 A42 A42 A42 CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 250 250 250 90 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 50 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS &

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Orderable Device

Status (1)

Package Type SOIC SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP

Package Drawing D D D D D PW PW PW PW PW PW

Pins Package Eco Plan (2) Qty no Sb/Br) 14 14 14 14 14 14 14 14 14 14 14 50 50 250 250 250 90 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish

MSL Peak Temp (3)

CD74HCT14ME4 CD74HCT14MG4 CD74HCT14MT CD74HCT14MTE4 CD74HCT14MTG4 CD74HCT14PW CD74HCT14PWE4 CD74HCT14PWG4 CD74HCT14PWR CD74HCT14PWRE4 CD74HCT14PWRG4
(1)

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Aug-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC SOIC TSSOP SOIC SOIC TSSOP D D D PW D D PW 14 14 14 14 14 14 14

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 330.0 330.0 16.4 16.4 16.4 12.4 16.4 16.4 12.4 6.5 6.5 6.5 6.9 6.5 6.5 6.9

B0 (mm) 9.0 9.0 9.0 5.6 9.0 9.0 5.6

K0 (mm) 2.1 2.1 2.1 1.6 2.1 2.1 1.6

P1 (mm) 8.0 8.0 8.0 8.0 8.0 8.0 8.0

W Pin1 (mm) Quadrant 16.0 16.0 16.0 12.0 16.0 16.0 12.0 Q1 Q1 Q1 Q1 Q1 Q1 Q1

CD74HC14M96 CD74HC14M96 CD74HC14MT CD74HC14PWR CD74HCT14M96 CD74HCT14MT CD74HCT14PWR

2500 2500 250 2000 2500 250 2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Aug-2010

*All dimensions are nominal

Device CD74HC14M96 CD74HC14M96 CD74HC14MT CD74HC14PWR CD74HCT14M96 CD74HCT14MT CD74HCT14PWR

Package Type SOIC SOIC SOIC TSSOP SOIC SOIC TSSOP

Package Drawing D D D PW D D PW

Pins 14 14 14 14 14 14 14

SPQ 2500 2500 250 2000 2500 250 2000

Length (mm) 346.0 333.2 346.0 346.0 346.0 346.0 346.0

Width (mm) 346.0 345.9 346.0 346.0 346.0 346.0 346.0

Height (mm) 33.0 28.6 33.0 29.0 33.0 33.0 29.0

Pack Materials-Page 2

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