Design and Implementation of MTJ-based Register

Yanfeng Jiang, Jiaxin Ju, Xiaobo Zhang, Bing Yang Department of Microelectronics, North China University of Technology, Beijing, 100144 E-mail: yfjiang@ncut.edu.cn
AbstractA novel register, in which MTJ device is centered, is proposed in this paper. Based on the demand of MTJs reading and writing process, some additional devices have been integrated with the MTJ device to compose the actual structure. It has been simulated using Hspice and the simulated result shows that it can be operated as a register in the circuit. Moreover, the layout of the register based on 0.5m CMOS process has been finished. Keywords- MTJ; Register; Integrated circuit

I.

INTRODUCTION
Figure 1. Basic structure of SRAM cell. The part inside the dashed circle equals to that in right part, being two inverters connected in anti-parallel mode.

For MTJ devices have many merits[1-6], such as novolatile, small size, compatible with the existing CMOS technology, many efforts have been made on how to use it in existing circuit. In recently published works, there was an attempt to exploit magnetologic for implementation of combinational logic[1-4]. Other works have been tried on to implement the MTJ device on sequential logic circuits.Weisheng Zhao et al. [5]have reported a novel logic circuit based on spin-MTJ, in which two MTJ devices have been included in a flip-flop circuit acting as adjustable resistance. However, for MTJ, it would be better to use its non-volatile property in sequential circuit design. Thus, the MTJ register can store its data even without power supply. A register is a kind of key element in circuit. It can store its input data triggered by clock edge. Before the next clock rising edge coming, its output remains the current data all the time. So, a register can be considered as a kind of SRAM except that a clock signal affects its state. However, for a conventional register and SRAM, when the power is off, they will lose their memory. After the device is reset, all data in them will be lost. For a digital system with lots of registers, when it be turned off, the system has been reset. After it is turned on, all initial process will be repeated once again. For example, in FPGA with LUT architecture, its states are stored in SRAMs. When it be power off, all states in SRAM be lost. Fortunately, there is ROM chip outside FPGA to store the data in SRAM. After it be turned on, FPGA will be configured based on the data provided by the external ROM. This process will influence the speed of FPGA. So, it will have a great potential future for developing a novel register with data being remained during the stage of power-off. In this paper, a novel register based on MTJ device is presented, which can utilize the character of MTJ. A driving circuit has been designed, which can write data under the combined effects of input data and clock signal. With the help

of the driving circuit, at the rising edge of clock signal, the state of MTJ will be influenced by the input data. In the third part of the paper, the circuit will be given and its operation principle will be presented. Its layout and its simulation result will be given in it, too. II. DESIGN OF MTJ-REGISTER

Basically, a SRAM cell is shown in Fig.1. A cell includes six transistors, which are shown by M1 to M6. The four transistors inside the dashed circle, as shown in Fig.1, is an equivalent structure of two inverters connected in anti-parallel mode. The structure of the two inverters with retaining data function is called keeper. Once the data input, it will retain in these two inverters unless data be changed. So, the four transistors, including M1,M2,M5,M6, act as the memory cell in SRAM, which can retain data in its own way. The keepers structure has been also used in register circuit. For example, a D flip-flop circuit is shown in Fig.2. Based on this circuit, one can see that the inverters are the main part in the D flip-flop.

Figure 2. A flip-flop schematic structure and its symbol

Based on Fig.1 and Fig.2, the keeper can be considered as a basic memory cell, which has the function of retaining data. So, one thought can rise that whether the memory cell can be substituted by other cells.

Figure 3. Schematic structure of MTJ, it symbol and terminals

MTJ devices can act as the memory cell, which has been realized in these years. Can it be used to take the place of the inverters in Fig.1 and Fig.2? As we know, MTJ is a magnetic storage device, which being its fundamental function instead of the adjustable resistance. A circuit centered by MTJ device will be proposed, especially utilizing its storage property. In this paper, since the MTJ is a storage cell, its function is equal to the keeper shown in Fig.1. So, a new concept on how to use MTJ to construct a register in electric circuit will be discussed here based on the above opinion. MTJ device will take the place of the storage inverters. That means MTJ devices will be the key part in circuit. The structure of MTJ is shown in Fig.3. To write information in the MTJ, a magnetic field should be applied through the junction. Two write lines are added to the structure to generate the magnetic field required to change the value stored in the MTJ. Currents are applied on these lines, as shown in Fig.3. Here, the current on write line1 is I1 and I2 is on write line2. The current applied on the write lines generates a magnetic field around these lines. At the cross point of the write lines, the magnetic field is high enough to change the magnetic orientation of the free layer. Fields generated from current I1 and I2, , shown in Fig. 3, work together to write a state into the MTJ register. The write line2 conductor generates a magnetic field orthogonal to the free magnetic layer stable state orientation and acts to reduce the magnitude of field required opposite the free magnetic layer orientation to drive the free magnetic layer orientation to its opposite state. The field generated from the write line2 conductor alone may bring the orientation of the free magnetic layer close to the switch point, however, it ideally cannot directly switch the state of MTJ register. The write line1 conductor generates a magnetic field in line with the orientation of the free magnetic layer stable states. The direction of I1 flowing through the write line1 conductor determines whether its generated field aligns parallel or antiparallel to the free magnetic layer stable state. In operation, current flowing through a write line2 conductor generates a hard axis field and current flowing at the same time through a write line1 conductor generates an easy axis field. The direction of current I2 flowing through the write line2 has little impact on switching, however, the direction of current flowing through the write line1 conductor determines the state written to MTJ register.

Figure 4. Schematic of a D flip-flop centered by a MTJ device

Based on the above operation principle, MTJ is a currentmode device, which means its driving signal is current instead of voltage. When a MTJ is used to construct a register, the external signals, such as clk and D in Fig.2, should be converted into current signal. The signal clk will apply on write line2, generating I2 at its rising edge in its driving circuit since register only samples at that point. The input data D, will apply on write line1. Its driving circuit should act in this way that when D=1, it generates I1 in parallel direction. On the contrary, when D=0, it generates current in anti-parallel way. The above is the fundamental requirements for the driving circuit in MTJ register. In this way, a MTJ register is designed, as shown in Fig.4. For the circuit shown in Fig.4, it acts as a register centered by a MTJ device. It is consisted by one MTJ device, six transistors, one resistor and one capacitor. Its operation principle is shown in following: Normally, MTJ can be considered as a six-terminal device, in which four terminals, two for write1 and two for write2, contribute to write process. The rest two terminals, read1 and read2, work for read process. For the register, the write process is determined by the state of D and CLK. According to its operation principle, every time when the CLK has a rising edge, the data at the D terminal at this time will be stored in the register. In Fig.4, two write lines are controlled by CLK and D data separately. M2, M3, M4 and M5 constructs a H-bridge structure combined with write line1. When D=1, M2 and M5 are on-state and current on write line1 will flow from left to right. When D=0, M3 and M4 are on-state, current on write line1 will flow in the reverse direction. So, the structure composed by the four transistors can provide the current on write line1 with adjustable current direction corresponding to D input. Fig.5(a) denotes the input D and the current on write line1 is shown in Fig.5(b), where positive current means current flowing from left to right and negative means the reverse direction. When current flowing on write line1, a magnetic field is generated around this line, with different

directions corresponding to the currents flowing in different directions. But the generated magnetic field isnt high enough to change the magnetic orientation of the free layer. A magnetic field from write line2 is needed and a combined effect of write line1 and write line2 can generate a magnetic field at the cross point of the write lines to change the magnetic orientation of the free layer. Based on the principle of register, it is an edge sensitive device. It samples the D input data at the point of CLK rising edge. So, a differential circuit, composed by C1 and R1, as shown in Fig.4, is used here. The output of differential circuit is connected to the gate of M1. When there is a positive edge on CLK, there will be a positive pulse on M1 gate. So M1 will be in on-state and there will be a pulse current on write line2. The voltage waveform at the gate of M1 is shown in Fig.5(d), corresponding to the CLK signal as shown in Fig.5(c). When the voltage shown as Fig.5(d) is applied on the gate of M1, the current on write line2 is generated as shown in Fig.5(e), which is pulsed current. Only at the time corresponding to the rising edge of CLK is there a transient pulse generated. Fig.6 shows the waveforms of currents I1, I2 and MTJ state. When the pulsed I2 appears, since I1 always exists, MTJ will enter into a state with the combined effect of I1 and I2. If I1 flowing in its parallel direction, MTJ will be in its on-state. On the contrary, if I1 flowing in reverse direction, MTJ will be in its off-state.

Figure 7. The equivalent circuit for the reading process in MTJregister

The dimensions of M1 to M5 in this register are determined the writing currents since the permitted current flowing through a MOS transistor is proportional to the ratio of width to length of channel. Here their dimensions are all fixed to be 20/0.5. For the reading process, it is determined by M6 and MTJ device. Fig.7 shows its equivalent circuit extracted from Fig.4. During reading process, MTJ device can be considered as adjustable resistance, with high value when it is in off-state and low resistance in on-state. For the circuit in Fig.7, the output of Q should reflect the MTJs state. That means that the outputs voltage value should be distinguished at different state. Since M6 is always in its saturation state, its dimension will influence output Q. So, discussion will be made on how to determine the dimension of M6. For the two states of MTJ, assuming its values are R1 and R2 when it is at on-state and off-state. So, its output should be: V1 VDD I D R1 (1) (2) Where ID is the current flowing through the drain of transistor, which showing as in Eqn(3).

V2 VDD I D R2

ID
Figure 5. Five Waveforms Corresponding to the Circuit in Fig.4, in which Fig.5(a) denotes the D input; Fig.5(b) is the current flowing through the write line1; Fig.5(c) denotes the CLK input; Fig.5(d) represents the voltage on the gate of M1; Fig.5(e) denotes the current flowing through the write line2.

1 W n Cox (VGS VTH ) 2 2 L

(3)

Figure 6. The write timeplate of MTJ, where Fig.6(a) corresponding to the current on write line1, Fig.6(b) being the current on write line2. Fig.6(c)denotes the data stored in MTJ.

Combining Eqn(1),(2) and (3), one can calculate W/L value of M6 on the condition that the difference between V 1 and V2 should at least be 0.5V. Based on actual measurement, for a fabricated MTJ, when it is on-state, its resistance is 55k . It is changed to 80k when it is off-state. For the two states, the difference of output voltage should be at least 0.5V. So the dimension of M6 in Fig4 and Fig.7 should be 48/0.5. In this way, a MTJ register has been designed, which under controlled by input data D and clk signal. Its state can be changed with different data input and it only samples at the rising edge of clk. So, it has a similar property to the conventional register. Moreover, since it is centered by a MTJ device, its state will be remained even though power being off.

Figure 9. Layout of MTJ-register Figure 8. The simulated results of MTJ-register, the first column is the Clk signal, the second the input data. The third is the current flowing through the write line1. The fourth denotes the current on the write line2. The last is the output value of the register.

IV. CONCLUSION In this paper, a circuit centered by a MTJ device has been constructed, which aimed at building a MTJ-based register. For thus register, during its writing process, two currents flowing on the write line1 and write line2 are needed, in which the direction of current on write line1 should be changed according to the input data. For the current on write line2, only the currents corresponding to clk rising edge are needed to be sampled. For the reading process, the output results should be distinguished between the MTJs two states. ACKNOWLEDGMENT This work is supported by NSFC (coded: 60876078), Funding Project for Academic Human Resources Development in Institutions of Higher Learning Under the Jurisdiction of Beijing Municipality. (PHR(IHLB)), Beijing Novel Research Star(2005B01) funded by Ministry of Beijing Science and Technology and Funding No.205004 from Ministry of Education Key Project. REFERENCES
[1] [2] [3] [4] [5] [6] Jianguo Wang, Hao Meng and Jian-Ping Wang, Programmable spintronics logic device based on a magnetic tunnel junction element, Journal of Applied Physics 97, 10D509, 2005 H. Meng, J. Wang, and J. P. Wang, A spintronics full adder for magnetic CPU, IEEE Electron. Devices Lett., vol. 26, pp. 360362,Jun. 2005. Seungyeon Lee, Seungjun Lee, Hyungsoon Shin, etc, Advanced HSPICE macromodel for magnetic tunnel junction, Japanese Journal of Applied Physics, Vol44, PP2696-2700, April 2005 S. Tehrani et al., Magnetoresistive ransom access memory using magnetictunnel junctions, Proc. IEEE, vol. 91, pp. 703714, May 2003. Weisheng Zhao, Eric Belhaire, Claude Chappert, etc., New nonvolatile logic based on spin-MTJ, Phys.stat.sol.(a) 205, pp1373-1377, June 2008 Seungyeon Lee, Nakmyeong Kim, Heejung Yang, etc., The 3-Bit Gray Counter Based on Magnetic-Tunnel-Junction Elements, IEEE Transactions on Magnetics, Vol.43, pp. 2677-2679, June 2007

III. SIMULATION AND DISCUSSION S. Y. Lee etc. have made a circuit macromodel of MTJ device[3]. This model has been used in their simultion of magnetologic circuit[6]. Here the simulation has adopted their model. CSMC 0.5m CMOS device models have been used here in combining with the MTJ model. A plot of the simulation results with HSPICE can be observed in Fig.8. It can be observed that the simulated circuit can act as a register, which can store data triggered by Clk and data. In Fig.8, there are five waves, representing Clk, input D, I 1, I2, output Q, separately. For Clk signal , it is a periodic wave. Based on the circuit shown in Fig.4, input data D is responsible for the current I1, which flowing through write line1. For the input data, it has been altered into the directional current signal, which is shown as the third column in Fig.8. When D=1, I1 is positive direction. When D=0, I1 is flowing in reverse direction. For the current on write line2, which is generated by Clk signal, its rising edge has been sampled and rest of it has all been omitted, as shown in Fig.8. In this way, currents on write line1 and line2 are both generated as predicted. The last column shows the output data, which can be seen that corresponding to the operation principle of register. So, simulated results show that the structure shown in Fig.4 can act as a register, which is centered by a MTJ device. The layout of register based on CSMC 0.5m CMOS technology is shown in Fig.9. It can be seen that MTJ device is located in it, with six terminals as write line1, write line2 and read line. For the designed MTJ-based register, its memory cell is a MTJ device. So the register is non-volatile and its data can be remained all the time even without power supply. It can be predicted that digital circuit adopting such registers will have new properties.