It's hard to figure out what our variety of XS Board products do if you don't understand what complex programmable

logic devices and field-programmable gate arrays are! This short tutorial will introduce the main concepts of these types of chips. In the beginning (OK, actually in the 60's) there was discrete logic. Systems were built from lots of individual chips with a spaghetti-like maze of wiring between them. It was difficult to modify such a system after you built it. Heck, after a week or two it was difficult to remember what each of the chips was for! Manufacturing such a system took a lot of time because each design change required that the wiring be redone which usually meant building a new printed circuit board. The chip makers solved this problem by placing an unconnected array of AND-OR gates in a single chip called a programmable logic device (PLD). The PLD contained an array of fuses that could be blown open or left closed to connect various inputs to each AND gate. You could program a PLD with a set of Boolean sum-of-product equations so it would perform the logic functions you needed in your system. Since the PLDs could be rewired internally, there was less of a need to change the printed circuit boards which held them.

Simple PLDs could only handle up to 1020 logic equations, so you couldn't fit a very large logic design into just one of them. You had to figure out how to break your larger designs apart and fit them into a set of PLDs. This was time-consuming and meant you had to interconnect the PLDs with wires. The wires were a big no-no because eventually you would make some design change that couldn't be handled just by reprogramming the PLDs and then you would have to build a new circuit board. The chip makers came to the rescue again by building much larger programmable chips called complex programmable logic devices (CPLDs) and fieldprogrammable gate arrays (FPGAs). With these, you could essentially get a complete system onto a single chip. A CPLD contains a bunch of PLD blocks whose inputs and outputs are connected together by a global interconnection matrix. So a CPLD has two levels of programmability: each PLD block can be programmed, and then the interconnections between the PLDs can be programmed. An FPGA takes a different approach. It has a bunch of simple, configurable logic blocks arranged in an array with interspersed switches that can rearrange the interconnections between

the logic blocks. Each logic block is individually programmed to perform a logic function (such as AND, OR, XOR, etc.) and then the switches are programmed to connect the blocks so that the complete logic functions are implemented.

CPLD and FPGA manufacturers use a variety of methods to make the connections between logic blocks. Some make chips with fuses or anti-fuses that are programmed by passing a large current through them. These types of CPLDs and FPGAs are one-time programmable (OTP) because you can't rewire them internally once the fuses are blown. Other manufacturers make the connections using pass transistors that are opened or closed by storing a charge on their gate electrodes using a high-voltage pulse. This type of programmable device resembles an EPROM or EEPROM: you can erase it and then place it in a special programmer socket and reprogram it. That's fine unless you have the CPLD or FPGA soldered into a circuit board. Finally, some manufacturers use static RAM or Flash bits to control the pass transistors for each interconnection. By loading each bit with a 1 or a 0, you can control whether the switch is closed or opened and, therefore, whether two logic elements are connected or not. CPLDs and FPGAs built using RAM/Flash switches can be reprogrammed without removing them from the circuit board. They are often said to be in-circuit reconfigurable or in-circuit programmable. Regardless of the interconnection method used, you can see that figuring out which switches to open and close in order to create a logic circuit would be quite a chore. That's why the chip manufacturers provide development software that takes a description of the logic design as input and then outputs a binary file which configures the switches in a CPLD or FPGA so that it acts like the design. Implementing a logic design with the FPGA or CPLD development software usually consists of the following steps (depicted in the figure below): 1. You enter a description of your logic circuit using a hardware description language (HDL) such as VHDL or Verilog. You can also draw your design using a schematic editor.

2. You use a logic synthesizer program to transform the HDL or schematic into a netlist. The netlist is just a description of the various logic gates in your design and how they are interconnected. 3. You use the implementation tools to map the logic gates and interconnections into the FPGA. The configurable logic blocks in the FPGA can be further decomposed into lookup tables that perform logic operations. The CLBs and LUTs are interwoven with various routing resources. The mapping tool collects your netlist gates into groups that fit into the LUTs and then the place & route tool assigns the gate collections to specific CLBs while opening or closing the switches in the routing matrices to connect the gates together. 4. Once the implementation phase is complete, a program extracts the state of the switches in the routing matrices and generates a bitstream where the ones and zeroes correspond to open or closed switches. (This is a bit of a simplification, but it will serve for the purposes of this tutorial.) 5. The bitstream is downloaded into a physical FPGA chip (usually embedded in some larger system such as an XS Board). The electronic switches in the FPGA open or close in response to the binary bits in the bitstream. Upon completion of the downloading, the FPGA will perform the operations specified by your HDL code or schematic. You can apply input signals to the I/O pins of the FPGA to check the operation of your design. That's really all there is to it. Software such as Xilinx Foundation or WebPACK provides the HDL and schematic editors, logic synthesizer, fitter, and bitstream generator software. The XSTOOLs from XESS provide utilities for downloading the bitstream into a CPLD or FPGA contained in an XS Board.

From Wikipedia
A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.

Contents

1 Features in common with PALs 2 Features in common with FPGAs 3 Non-volatility 4 Distinctions 5 See also 6 Some notable CPLD suppliers

Features in common with PALs

Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up. For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

Features in common with FPGAs

Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million. Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the presence of onchip non-volatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.

Non-volatility

The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.

Distinctions
CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in turn were preceded by standard logic products, that offered no programmability and were "programmed" by wiring several standard logic chips together. The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (for example, sum of products).

See also

Application-specific integrated circuit (ASIC) Erasable programmable logic device (EPLD) Simple programmable logic device (SPLD) Macrocell array Programmable array logic (PAL) Programmable logic array (PLA) Programmable logic device (PLD) Field-programmable gate array (FPGA) VHSIC Hardware Description Language (VHDL) Verilog Hardware Description Language

Some notable CPLD suppliers

Altera Atmel Cypress Semiconductor Lattice Semiconductor Xilinx