Design & Synthesis of High Performance Phase Locked Loop

Registration seminar report submitted in partial fulllment of the requirements for the degree of

Doctor of Philosophy
in

Electronics and Communication Engineering

by

Umakanta Nanda
(Roll No. 511EC101)
under the guidance of

Prof. D.P. ACHARYA

&

Prof. S.K. PATRA

Department of Computer Science and Engineering National Institute of Technology Rourkela Rourkela, Odisha, 769 008, India

Contents
1 INTRODUCTION 2 PLL COMPONENTS 2.1 2.2 2.3 2.4 Phase Frequency Detector with Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . Charge pump and Loop lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 2 3 3 4 5 6 6 7 8 8 9

3 NOISE IN PLL 4 A BRIEF REVIEW OF THE PLL DESIGN 5 WORK CARRIED OUT SO FAR 5.1 5.2 5.3 5.4 Implementation of PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimization of LC VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 SUMMARY AND PROPOSED FUTURE WORK

List of Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Block Diagram of PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFD with Charge pump [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge pump with loop lter [2, 4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic of CSVCO drawn in Cadence ADE . . . . . . . . . . . . . . . . . . . . . . . . . Schematic of LCVCO drawn in Cadence ADE . . . . . . . . . . . . . . . . . . . . . . . . . Frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCO signal exhibiting phase noise [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ((a)Layout of 1 GHz PLL,(b)Layout of 2.4 GHz PLL) . . . . . . . . . . . . . . . . . . . . Post layout transient analysis of 1 GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . Phase noise and jitter plots of 1 GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . Post layout transient analysis of 2.4 GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . Phase noise and jitter plots of 2.4 GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . Design parameters for LCVCO 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a)Phase noise analysis, (b)Transient analysis . . . . . . . . . . . . . . . . . . . . . . . . . Tuning range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 3 4 4 4 6 7 7 7 8 8 9 9

List of Tables
1 2 Summary of Results of both PLLs and comparison . . . . . . . . . . . . . . . . . . . . . . Comparison Of this work with some of the recent works . . . . . . . . . . . . . . . . . . . 8 9

Abstract
The design of Phase Locked Loop (PLL) which would oer better performance is the prime objective of this research. The performance of the PLL dictates the quality of the communication systems where it is used. It is desirable for the PLL to have fast locking, low noise, wide lock range, low power consumption and less silicon area. However to achieve these performance parameters simultaneously for the PLL is a challenging task. In this work ecient multiobjective optimization method is applied to attain multiple optimal performance objectives. The major indices under consideration would be lock in time, phase noise and power consumption. In the initial phase trial PLL designs with two cases of operating frequencies viz 1 GHz and 2.4 GHz are considered for implementation. The design of these PLLs are performed in 90nm process technology (GPDK 090) in Cadence Virtuoso Analog Design Environment. This work also has vision to optimize these performances with various architectures of dierent PLL components.The eects of circuit parasitics are also to be included in the design. The statistical analysis for the manufacturability of the design is also proposed to be carried out. Keywords:Phase Locked Loop, Phase noise, Jitter, Lock range, Lock in time, Multi Objective Optimization

INTRODUCTION

The Phase Locked Loop (PLL) is a vital mixed signal circuit having wide range of applications [1]. The application domains are communication systems, processors, and many Modern embedded systems. The typical structure of a PLL is shown in Figure 1. It consists of a phase frequency detector, charge pump, loop lter, voltage controlled oscillator (VCO) and a frequency divider.

Figure 1: Block Diagram of PLL

The main objective of PLL is to recover the signal without phase and frequency error and less jitter which can be achieved after much iteration inside the system. In this report the preliminary implementation of PLL is carried out using Cadence Virtuso ADE. The simulation results and the performance of PLL have been demonstrated by individually designing each block of the PLL and nally assembling them to build a complete PLL. This is performed for two cases of PLL with operating frequency 1GHz and 2GHz in 90 nm CMOS process. The report elaborates the further course of research to be undertaken. The remaining part of report is organized as follows. In section 2 the internal components of PLL are outlined. The sources of noise in PLL are described in section 3. Section 4 provides a brief review of earlier PLL designs. The research work carried out so far is discussed in section 5. The report is summarized and further work dimensions are presented in section 6.

2
2.1

PLL COMPONENTS
Phase Frequency Detector with Charge pump

The phase frequency detector [2] is used to minimize the phase error introduced by the reference signal. The phase frequency detector has two inputs one is from the input of the PLL and other is from the output of divider circuit which divides the output frequency of VCO to bring it within the lock range to the reference frequency. It is also used to minimize the frequency error of the incoming signal.

Figure 2: PFD with Charge pump [3]

In the above gure a conventional PFD and a fast Phase Frequency acquisition PFD [3] are shown. Depending upon the phase and frequency deviation, it generates two output signals UP and DOWN. The use of the PFD permits the use of a charge pump as shown in gure 2 in place of the conventional PD and low pass lter. The advantages of the PFD and charge pump include: The capture range is only limited by the VCO output frequency range. The static phase error is zero if the mismatches and osets are negligible. When QA is high charge is deposited in CP (A leads B).When QB is high charge is removed from CP (B leads A).When QA and QB both are low Vout remains constant.

2.2

Charge pump and Loop lter

The charge pump [2, 4] is shown in gure 3. This circuit gives a constant current of value IP DI which should be insensitive to the supply voltage variation. The amplitude of the current always remains same but the polarity changes which depends on the value of the UP and DOWN signal.

Figure 3: Charge pump with loop lter [2, 4]

The current IP DI can be expressed as, IP U M P = KP DI 2 Loop lter which is a low pass lter is one of the most important components of PLL. It aects the IP DI = dynamic characteristics of the PLL like rise time, settling time, peak overshoot, damping ratio, damping factor, bandwidth and noise performance of a PLL. There are several architectures available for loop lters. A passive phase lead-lag lter having two poles and one zero is used in this work. The output voltage of the loop lter controls the oscillation frequency of the VCO. The loop lter voltage will increase if fref rising edge leads n rising edge and will decrease if fin rising edge leads fref rising edge. If the PLL is in locked state the loop lter maintains a constant output value [5].

2.3

Voltage Controlled Oscillator

Voltage controlled oscillator (VCO) is a circuit which accepts a control voltage as input and produces oscillations of frequency which depends on the input voltage. There are several architectures of VCOs out of which the ring oscillators and the LC VCOs are the prominent ones. The current starved VCO (CSVCO) shown in gure 4 is a simple ring oscillator with number of stages in which the oscillation frequency is controlled by the help of current conduction through the circuit [2].

Figure 4: Schematic of CSVCO drawn in Cadence ADE

The voltage propagation time period is a function of current so that if we are able to control the value of current in the circuit then we can control the frequency of oscillation also. In current starved voltage controlled ring oscillator P-MOS are always in the saturation region and with the help of control voltage Vctrl we are controlling the current through the N-MOS and nally controlling the frequency of oscillation. The oscillation frequency of the N stage VCO is 1 ID = N (t1 + t2 ) Ctot VDD Where, t1 , t2 represent the charging and discharging times fosc = Ctot is the total capacitance LCVCO is another type of voltage controlled oscillator which oers very low phase noise.A typical LCVCO is depicted in g 5.

2.4

Frequency Divider

The output of the VCO is fedback to the input of PFD through the frequency divider circuit, to bring the VCO output frequency comparable to the input refrence frequence.

Figure 5: Schematic of LCVCO drawn in Cadence ADE

Figure 6: Frequency divider

NOISE IN PLL

The total noise of the PLL is nothing but the summation of individual noise contribution of dierent PLL building blocks. The VCO and the frequency divider are the blocks which contribute most of the noise in a PLL, because they are the blocks which are dealing with the high frequency signal. These are more subject to thermal noise. Phase noise is the measure of variations in the frequency domain. Figure 7 shows a plot of a VCO signal exhibiting phase noise. Phase noise spreads some of the oscillators power to adjacent frequencies, which results in sidebands. The phase noise is the ratio of the area of the rectangle with 1-Hz bandwidth at oset fm to the total area under the power spectrum curve, approximately the dierence in the height of the spectrum at the centre f0 and at f0 + fm . The main sources of noise are,

Figure 7: VCO signal exhibiting phase noise [6]

Phase jitter from reference oscillator n,REF rad2 N2 S (f ) 2 ,out m Hz R Where S,out (fm ) is PSD Phase jitter by reference oscillator. S,out (fm ) = |H(fm )|2 We know that phase frequency response H(f) acts as a low pass lter on to the phase jitter caused by

reference oscillator. To minimize VCO Output jitter, the loop bandwidth must be as small as possible. But low bandwidth means low Wn [6] which means higher lock in time [1]. Phase jitter from VCOn,V CO
2

S,out (fm ) = |He (fm )|2 S,V CO (fm )rad Hz Where S,V CO (fm ) is PSD Phase jitter by VCO and S,out is PSD output Phase jitter due to VCO. The bandwidth of highpass function He (fm ) is same as bandwidth of low pass function H(f) as He (fm ) = 1 H(f ). It is assumed that the most of the VCO noise is icker noise and most of the power is concentrated at f0 . To minimize the output phase jitter, PLL bandwidth should be as large as possible, but it is contradictory with the statement mentioned above [1]. Spurs at f ref , 2f ref . from carrier frequency, generated by PFD The carrier to spur ratio [1] is, S=
Carrier power Side band power

Using the relations, Ip = Kp 2 2 = R2 C1

2 n = Kp K0 NC1

= n 2/2 We get, S=

1 2 4 2 2 2 n fref TOV 2 N 2

Where TOV is the overlapping time of the UP nad DN signal from phase detector. is the current imballance between the two current sources of charge pump.

A BRIEF REVIEW OF THE PLL DESIGN

Woo-Yeol Shin et al. [7] adopts a split half duty sample feed forward loop lter to reduce the patern jitter and acquisition time of a PLL. Here the RMS jitter is found out to be 5.418 ps and p-p jitter is 40 ps. Merrick Brownlee et al. [8] describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. Fabricated in a 0.18- m CMOS process, the PLL occupies 0.15 mm2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms. Sin-Jhih Li et al. [9] uses a dual path control in the loop lter for a 10 GHz PLL. The capacitance can be eectively reduced while mentaining the required bandwidth. The locking range is 10.1 to 11 GHz. Chia-Yu Yao et al. [10] modies a second order passive lead lag lter which results smaller area, lower power and better noise perfermance. Employing the modied loop lter can lower the power consumption by using a smaller pump current, or it can improve the noise performance by reducing the VCO sensitivity. Hiroshi Kodama et al. [11] developes a new interpolative ring VCO having a wide control voltage over which the frequency variation is linear. It operates at from 3.432 to 4.488 GHz (LF Mode) and from 6.6 to 9.24 GHz(HF Mode). Asad A Abidi [12] analyzes dierent sources of noise and their eects on ring oscillator and LC Oscillators. Also guides to choose between ring oscillator and LC oscillator. In dierential ring oscillator, white noise in the delay stages and icker noise in the tuning current are mainly responsible for jitter and phase noise.

I Thompson and P V Brennan [13] analyzes phase noise generated by PFD by taking Figure Of Merit in to account . An analysis has been presented that enables the FOM to be predicted for a given PFD from device parameters. Mozhgan Mansuri et al. [3] designs a PFD which helps in fast frequency acquisition. This PFD architecture has been incorporated in our design. Donhee Ham et al. [14] describes Concepts and Methods in Optimization of Integrated LC VCOs. They have used Graphical methods to optimize LCVCO. Yin Xu et al. [15] uses a NMOS varactor in CMOS LC VCO in 0.5m Process to have wide tuning range. In NMOS varactor all the three terminals drain body and source have been sorted together.

5
5.1

WORK CARRIED OUT SO FAR

Implementation of PLL

In this work two PLLs with operating frequencies of 1 GHz and 2.4 GHz is designed. In gures 8(a) and 8(b) the physical layout of the PLLs have been shown.

Figure 8: ((a)Layout of 1 GHz PLL,(b)Layout of 2.4 GHz PLL)

5.2

Simulation Results

Both the PLLs have been simulated and the results have been shown by taking two case studies. The transient, Phase noise and jitter analysis have been demonstrated below. Case Study 1: 1GHz PLL

Figure 9: Post layout transient analysis of 1 GHz PLL

Figure 10: Phase noise and jitter plots of 1 GHz PLL

Case Study 2: 2.4 GHz PLL

Figure 11: Post layout transient analysis of 2.4 GHz PLL

The design of PLL is performed in 90 nm process technology (GPDK 090) in Cadance virtuoso Analog design environment by considering 2 case studies. The work carried out for 1 GHz PLL is compared with [16] in the table1.

Figure 12: Phase noise and jitter plots of 2.4 GHz PLL Table 1: Summary of Results of both PLLs and comparison
P arameters Technology Frequency Vdd Lock range Lock time Phase noise @1 MHz oset Jitter(Jc) 1 GHz OurW ork GPDK 90 nm 1 GHz 1.8 V 250-950 MHz 220 ns -91.74 dBc/Hz 6.125 ps (RMS) 37.85 ps (P-P) @1.1 GHz Power consumption 3.43 mW [16] 0.18 m 1 GHz 1.8 V 0.9-1.25 GHz 5 s -105 dBc/Hz 3.5 pS (RMS) 27.8 ps (P-P) @1.2 GHz 10.8 mw 2.4GHzP LL GPDK 90 nm 2.4 GHz 1.8 V 2-3 GHz 650ns -63.76 dBc/Hz 1.198 Ps (RMS) 7.405 ps (P-P) @1.2 GHz 7.94 mW

5.3

Optimization of LC VCO

Using the Combining Multi Objective Dierential Evolution (CMODE) [17] optimization technique a simple LC VCO (shown in gure 13) of 2.5 GHz frequency of oscillation constrained by gpdk090 process technology library has been designed. The design parameters have been extracted from MATLAB by using CMODE.

Figure 13: Design parameters for LCVCO 5

5.4

Simulation Results and Discussion

The simulation has been carried out in Cadence Spectre ADE and the phase noise curve, transient analysis, and the tuning range has been shown in g. 14(a), 14(b) and 15. The LC VCO performance indices, phase noise is found to be -119.7 dBc/Hz at 1 MHz oset and power consumption is measured to be 515 uW respectively.

Figure 14: (a)Phase noise analysis, (b)Transient analysis

Figure 15: Tuning range

The Figure Of Merit (FOM) of the LCVCO is found out to be -190.26 dBc/Hz at 1 MHz oset. The measured output frequency of oscillation is observed to be 2.42 GHz and the VCO has a tuning range of 10.53%. The work can be extended in several other dimensions such as the chip area and tuning range as performance indices for optimization. The used technique provides the optimal design parameters in a single run which saves lot of time and design cost.

SUMMARY AND PROPOSED FUTURE WORK

Ecient PLL design has been carried out by considering two case studies. The noise performance of the designed 1 GHz PLL is good where as the lock range, locking time and the power consumption is comparatively better than the recent works. A LC VCO design whose optimal design parameters have been generated from MATLAB by using CMODE Algorithm has been demonstrated and compared with some recent papers. In future the same algorithm will be implemented for design of each block of the PLL to reduce noise, power consumption and locking time. Complete parasitic aware PLL circuit optimization is to be carried out. Statistical analysis for process and temperature variation of the PLL needs to be carried out manfacturability of the design before its release for possible fabrication.

Table 2: Comparison Of this work with some of the recent works

Ref. [18] [19] [20] This work F req.(GHz) 2.5 2.4 2.72 2.42 Vdc (V ) 1.8 1.8 1.2 1.8 Pdc (mw) 5.4 3.99 0.812 0.515 Pnoise dBc/Hz@1M Hz -128.7 -130.5 -123.2 -119.7 T uningrange(%) 11 8 10.53 F OM dBc/Hz @1M Hz -192.7 -190.26

References
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