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VHDL code for quadrature encoder receiver module dewplanet

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VHDL code for quadrature encoder receiver module dewplanet

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* The Construction of Merlin Part II: First Prototype May 04

VHDL code for quadrature encoder receiver module


Categories: Electronics by dew

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VHDL code for quadrature encoder receiver module dewplanet

Like Tw eet Original document: Quadrature Encoder Receiver Module: An Implementation on FPGA

In the original document cited above, we discussed some designs of quadrature encoder receiver module where Verilog code listings were included. This supplementary article provides the same implementations using VHDL. The development flows remain the same for both design A and B, so we basically list the codes and show simulation results here without repeating the design details.

Design A
For Design A, the receiver module generates pulses at output pin U (up) or D (down), corresponding to whether A leads B, or A lags B, respectively (*). We showed the design process using STG (State Transition Graph) that yielded the results in equation (1) (4) . The VHDL code for this implementation is in Listing 1 with simulation result shown in Figure 1. (The synthesis and behavioral simulation was performed using Xilinx Webpack 13.4 and Isim simulation, which could be downloaded from Xilinx website. (*) It turns out that in the original document, the Karnaugh map for output U and D shuffles, so as the resulting equations (3) and (4). You could verify from the simulation in Figure 9. If this gives the wrong sense for your motor setup, simply switch equation (3) and (4). We do so in the VHDL code below.
lbayIE; irr EE ueIE.T_OI_14AL s EESDLGC16.L; ett xec i niy 4n1 s Pr (ABCk:i SDLGC ot ,,l n T_OI; UD:ot SDLGC; , u T_OI) edxec; n 4n1 acietr Bhvoa o xec i rhtcue eairl f 4n1 s sga Q,Q :SDLGC inl 0 1 T_OI; bgn ei poes(l) rcs Ck bgn ei i (l'vn adCk'' te f Ckeet n l=1) hn Q < AxrB 0 = o ; Q < B 1 = ; edi; n f edpoes n rcs; U< (o AadntBadQ)o (o AadQ adntQ) = nt n o n 1 r nt n 1 n o 0 o ( adntQ adntQ)o ( adBadntQ) r A n o 1 n o 0 r A n n o 1; D< (o AadBadntQ)o (o AadntQ adQ) = nt n n o 1 r nt n o 1 n 0 o ( adQ adQ)o ( adntBadQ) r A n 1 n 0 r A n o n 1; edBhvoa; n eairl

Listing 1: VHDL code for X4 receiver module (Design A, STG method) Download and add these source files to Xilinx ISE project x4enc1.vhd -- Code in listing 1 x4enc1_tb.vhd -- VHDL test bench for simulation

Figure 1: Simulation result for X4 receiver module (Design A, STG method) Manually solving for logic equations using STG might be fun for simple problem, though its quite easy to make mistakes (as you can see). Such implementation is often referred to as structural model. With the advancement of computer technology and software, its preferred that we benefit from development tools as much as possible. For the receiver module design A, we can draw an ASM (Algorithmic State Machine) chart like it Figure 2 and write VHDL code from it directly, such as in Listing 2. This approach is named behavioral model, since we just describe what the model must do and leave the low-level synthesis to the software. The simulation result in Figure 3 confirms that the module has similar behavior as the STG design version, with much less human effort in the design process.

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VHDL code for quadrature encoder receiver module dewplanet

Figure 2: ASM chart for X4 receiver module (design A)


lbayIE; irr EE ueIE.T_OI_14AL s EESDLGC16.L; ett xec i niy 4n2 s Pr (A :i SDLGCVCO ( dwt 0; ot B n T_OI_ETR 1 ono ) Ck:i SDLGC l n T_OI; U :ot SDLGCVCO ( dwt 0) D u T_OI_ETR 1 ono ); edxec; n 4n2 acietr Bhvoa o xec i rhtcue eairl f 4n2 s sga Sae SDLGCVCO ( dwt 0 : "0; inl tt: T_OI_ETR 1 ono ) = 0" - Sae0="0,Sae1="1, - tt 0" tt 0" - Sae2="0,Sae3="1 - tt 1" tt 1" bgn ei poes(L) rcs Ck bgn ei i (l'vn adCk'' te f Ckeet n l=1) hn cs Saei ae tt s we "0 = - Sae0 hn 0" > - tt cs A i ae B s we "0 = U < "0;-sasa Sae0 hn 0" > D = 0"- ty t tt we "1 = U < "1;Sae< "1;- t Sae3 hn 0" > D = 0" tt = 1" - o tt we "0 = U < "0;Sae< "1;- t Sae1 hn 1" > D = 1" tt = 0" - o tt we ohr = U < "0; hn tes > D = 0" edcs; n ae we "1 = - Sae1 hn 0" > - tt cs A i ae B s we "0 = U < "1;Sae< "0;- t Sae0 hn 0" > D = 0" tt = 0" - o tt we "0 = U < "0;- sasa Sae1 hn 1" > D = 0" - ty t tt we "1 = U < "0;Sae< "0;- t Sae2 hn 1" > D = 1" tt = 1" - o tt we ohr = U < "0; hn tes > D = 0" edcs; n ae we "0 = - Sae2 hn 1" > - tt cs A i ae B s we "1 = U < "0;Sae< "1;- t Sae3 hn 0" > D = 1" tt = 1" - o tt we "0 = U < "1;Sae< "1;- t Sae1 hn 1" > D = 0" tt = 0" - o tt we "1 = U < "0; - sasa Sae2 hn 1" > D = 0" - ty t tt we ohr = U < "0; hn tes > D = 0" edcs; n ae we "1 = - Sae3 hn 1" > - tt cs A i ae B s we "0 = U < "0;Sae< "0;- t Sae0 hn 0" > D = 1" tt = 0" - o tt we "1 = U < "0;- sasa Sae3 hn 0" > D = 0" - ty t tt we "1 = U < "1;Sae< "0;- t Sae2 hn 1" > D = 0" tt = 1" - o tt we ohr = U < "0; hn tes > D = 0" edcs; n ae we ohr = nl; hn tes > ul edcs; n ae edi; n f edpoes n rcs; edBhvoa; n eairl

Listing 2: VHDL code for X4 receiver module (Design A, ASM method ) Download and add these source files to Xilinx ISE project x4enc2.vhd -- Code in listing 2 x4enc2_tb.vhd -- VHDL test bench for simulation

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VHDL code for quadrature encoder receiver module dewplanet

Figure 3: Simulation result for X4 receiver module (Design A, ASM method)

Design B
Design B in the original document refers to the X4 encoder receiver module intended to be used with a counter that accepts pulse and direction inputs. So the module must provide output P (pulse) and DIR (direction). Following the same discussion there, the resulting VHDL code is as in Listing 3, with simulation result shown in Figure 4.
lbayIE; irr EE ueIE.T_OI_14AL s EESDLGC16.L;

ett xec i niy 4n3 s Pr (AB Ck:i SDLGC ot ,, l n T_OI; PDr:ot SDLGC; ,i u T_OI) edxec; n 4n3 acietr Bhvoa o xec i rhtcue eairl f 4n3 s sga A,B :SDLGCVCO ( dwt 0 : "0; inl r r T_OI_ETR 1 ono ) = 0" bgn ei poes(l,,) rcs CkAB bgn ei i (l'vn adCk'' te f Ckeet n l=1) hn A < (r0&) r = A()A; B < (r0&) r = B()B; i (r="1)te - rsn eg o A f A 0" hn - iig de f P< '' = 1; i ( ='' te Dr< '' - AlasB f B 0) hn i = 1; ed es Dr< '' le i = 0; edi; n f esf(r="0)te - fligeg o A li A 1" hn - aln de f P< '' = 1; i ( ='' te Dr< '' - AlasB f B 1) hn i = 1; ed es Dr< '' le i = 0; edi; n f esf(r="1)te - pstv eg o B li B 0" hn - oiie de f P< '' = 1; i ( ='' te Dr< '' - AlasB f A 1) hn i = 1; ed es Dr< '' le i = 0; edi; n f esf(r="0)te - pstv eg o B li B 1" hn - oiie de f P< '' = 1; i ( ='' te Dr< '' - AlasB f A 0) hn i = 1; ed es Dr< '' le i = 0; edi; n f es P< '' le = 0; edi; n f edi; n f edpoes n rcs; edBhvoa; n eairl

- BlasA ed

- BlasA ed

- BlasA ed

- BlasA ed

Listing 3: VHDL code for X4 receiver module (Design B) Download and add these source files to Xilinx ISE project x4enc3.vhd -- Code in listing 3 x4enc3_tb.vhd -- VHDL test bench for simulation

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VHDL code for quadrature encoder receiver module dewplanet

Figure 4: Simulation result for X4 receiver module (Design B) Tags: quadrature encoder, VHDL
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