Basic Concepts in Serial I/O Interfacing I/O Devices Using I/O devices data can be transferred between the

e microprocessor and the outside world. This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O.
The other method is serial I/O where one bit is transferred at a time

using the SI and SO pins on the Microprocessor. Dealing with I/O Devices There are two ways to deal with I/O devices. Consider them like any other memory location. They are assigned a 16-bit address within the address range of the 8085. The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory. This is called memory-mapped I/O. Treat them separately from memory: I/O devices are assigned a port number within the 8-bit address range of 00H to FFH. The user in this case would access these devices using the IN and OUT instructions only. This is called I/O-mapped I/O or Peripheral-mapped I/O. Basic interfacing concepts The first step in interfacing an I/O device would be to determine which instructions will be used to access it.

 If you want the user to use the IN/OUT instructions, then it should be interfaced as a peripheral-mapped I/O device. If the user should use regular data transfer instructions (LDA, STA, etc.) then it should be interfaced as a memory-mapped I/O device. Peripheral I/O instructions There are two instructions: IN brings data (8-bits) from an input device to the accumulator OUT brings data (8-bits) from the accumulator to an output device. They are both 2 byte instructions with the second byte holding the 8-bit address of the device. Note: Given that there are separate instructions for input and output, the 8085 can actually communicate with 256 different input devices AND an additional 256 different output devices. The execution of the OUT instruction The OUT instruction requires 3 machine cycles and 10 T-states. The first cycle is an opcode fetch cycle to fetch the 1st byte of the instruction from memory (OUT). The second cycle is a memory read cycle to bring the 8-bit port number from the next location. The third cycle is an I/O write cycle. In this cycle, the 8085 places the port number on AD0-AD7 AND A8-A15 and the signal WR is set low (active). Since the device address is placed on both AD0-AD7 as well as A8-A15, there is no need for de-multiplexing AD0-AD7. A8-A15 can be used directly to identify the device.

The execution of the IN instruction The execution of the IN instruction is almost identical to that of the OUT instruction. 3 machine cycles, 10 T-states. The first machine cycle is the opcode fetch. The second cycle is the memory read to get the port number. The third is an I/O Read cycle.

Again, in T1 the port address (8-bits) is placed on both

AD0- AD7, and A8-A15. The IO/M signal is set high to indicate an I/O operation. At the beginning of T2, the RD signal is set low (active) and the I/O device responds by placing the 8bit data on the data bus. The interfacing of output devices Output devices are usually slow. Also, the output is usually expected to continue appearing on the output device for a long period of time. Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally. To do this the external latch should be enabled when the ports address is present on the address bus, the IO/M signal is set high and WR is set low. The resulting signal would be active when the output device is being accessed by the microprocessor. Decoding the address bus (for memory-mapped devices) follows the same techniques discussed in interfacing memory. Interfacing of input devices The basic concepts are similar to interfacing of output devices.

 The address lines are decoded to generate a signal that is active when the particular port is being accessed. An IORD signal is generated by combining the IO/M and the RD signals from the microprocessor. A tri-state buffer is used to connect the input device to the data bus. The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IORD. Examples of Interfacing I/O Devices To illustrate the techniques of interfacing I/O devices we will design the circuits needed to interface 8 LEDs to display the contents of the accumulator as well as 8 switches to set the contents of the accumulator. Interfacing the LEDs Lets first design the external circuit. The data on the data bus from the microprocessor stays for an extremely short amount of time. So, in order to keep it long enough for displaying, we will need an external latch.

We will use an 8-bit latch to hold the data we need to

connect the 8 LED to the latches outputs. However, the latch will not be able to source enough current. So, we will use the inverted outputs and make it sink the current instead. When should the latch be enabled? It needs to be enabled when the data is on the data bus. That happens when the ALE signal is low. However, we only want to display the data that is being sent to the I/O, we dont want to display the data being saved in memory.

 So, the latch needs to be enabled only during I/O operations. That happens when IO/M=1 Finally we only want to display data intended for our port. We must decide on a port number. Lets say FFH. Now, we can design the control circuit. Interfacing the LEDs (Control Circuit)

WR = 0 IO/M = 1

The Latch will be enabled when:

The address on A8 A15 = FFH

Interfacing the LEDs (Latch & LEDs)

Interfacing the LEDs (the program) When a bit on the AD bus is 1, the corresponding Q will be zero and the LED will have 5 volts on the anode and 0 on the cathode. Therefore, it will be on. Finally, to write the program: MVI A, Data OUT FF HLT ; load the data to be displayed ; send the data to output port FF ; End

Interfacing the switches The binary value from the switches will have to be carried by the data bus. However, the data bus is a shared bus. So, the switches must be connected to the data bus using Tri-state buffers. Similar to the latch, the buffers must be enabled only on I/O Read operation from this I/O port.

 Lets choose I/O port 0FH for the switches. So, the buffers must be enabled when: o RD = 0 o IO/M = 1 o A8-A15 = 0FH Interfacing the Switches (Control Circuit)

Interfacing the Switches (Latch & Switches)

Interfacing the Switches (the program) Finally, the program: IN 0FH ; input data from port 0F into A

HLT INPUT:

; END IN 0FH OUT FFH JMP INPUT

If we combine both circuits, then we can write the following program:

Direct Memory Access Direct Memory Access--the ability of an I/O subsystem to transfer data to and from a memory subsystem without processor intervention. DMA Controller--a device that can control data transfers between an I/O subsystem and a memory subsystem in the same manner that a processor can control such transfers.

DMA Controller The DMA controller can issue commands to the memory that behave exactly like the commands issued by the CPU. The DMA controller in a sense is a second processor in the system but is dedicated to an I/O function. The DMA controller as shown below connects one or more I/O ports directly to memory, where the I/O data stream passes through the DMA controller faster and more efficiently than through the processor as the DMA channel is specialized to the data transfer task.

The DMA interface The DMA adds one more level of complexity to the I/O interface because a DMA controller has independent access to memory. One set of wires (bus) can carry at most one transaction at a time. If the DMA and a microprocessor share the signal wire to memory there must be a mechanism to arbitrate which shall have access to memory when both attempt to at the same time. Functional behavior of a DMA transaction 1. The processor transmits the following information to a DMA controller: Beginning address in memory Block length (number of words to transfer) Direction (memory-to-device or device-to-memory) Port ID End of block action (interrupt request or no interrupt request). 2. The processor returns to other activities while the DMA controller starts the data transfer.

3. Each time the DMA controller accesses memory, it synchronizes this memory request with an idle period of the processor--to do this the possibilities are:
Force an immediate disabling of the processor, or Request a halt of the processor, and await an acknowledgement, or Time the DMA access to a clock interval or status signal of the

processor that signals an idle cycle. 4. When the DMA controller accesses an I/O port or memory, it uses the same functional control signals as used by the processor. I/O port activity can be performed on dedicated lines that do not have to be synchronized with the Processor. 5. At the completion of the block transfer, the DMA controller raises an interrupt request if the interrupts are "armed" and otherwise indicates completion in its status register. 6. The processor recognizes I/O completion (either by interrupt or by reading the status register); thereafter the activity between the processor and the DMA controller follows the normal post-completion activity of any I/O port. This shows that the controller is treated as a standard port before and after block transfer and during transfer the DMA must be able to synchronies with the processor. The controller improves performance especially with a built-in program for moving a stream of data between memory and an I/O port--thereby not requiring accessing the instruction from memory and executing them one by one. Some elementary actions can be performed in parallel instead of sequentially when implemented with software in the processor. For example, the controller decrements a counter each time it moves a datum. The controller can overlap the subtraction with memory access and

avoid the time penalty for the arithmetic instruction. Because of the ability to achieve higher performance for block transfers, the DMA controller is used most frequently for high speed I/O, especially disk. Fast disks move blocks of data at speeds much greater than any program can control and therefore must be interfaced to computers through DMA controllers. DMA interface operation The figure below indicates a typical direct memory-access controller interface. The I/O ports in this example under DMA control are attached only to the DMA controller. Signal lines are the same ones that normally interface the ports to the processor. Memory lines are the conventional lines except that both the processor and the DMA controller exercise the lines. The new lines are the HALT and HALT ACKNOWLEDGE lines. These lines synchronies the DMA controller to the processor. When the DMA controller needs to access the memory it requests the processor to halt by asserting the HALT signal. The processor responds with HALT ACKNOWLEDGE at a later time and then the DMA controller takes control of memory. On completion of its task the DMA controller removes its HALT request; the processor continues from its suspension and removes its HALT ALTACKNOWLEDGE .

The dotted IMMEDIATE HALT is a different type of DMA request. The HALT request may take several clock cycles for the processor to acknowledge due to the time taken for the processor reaching a state where it can suspend processing. Data held in dynamic registers that are refreshed during normal processing must be moved to status registers, or execution has moved to a point where the data is no longer necessary. The IMMEDIATE HALT line avoids this delay but has associated severe restrictions. The IMMEDIATE HALT can be used only briefly one or at most two accesses otherwise the processor may not be able to recover its state correctly and return to the suspended activity. The IDLE status line can be used by the DMA controllers that can delay data transfers until an IDLE point is reached. The IDLE in some systems can occur frequently, that is, 20 to 30% of the memory cycles. In this situation there is no need to halt the processor and the DMA can achieve high data rates with virtually no impact on processor performance.

A typical direct memory-access controller interface

DMA controllers

DMA controllers were expensive and complex subsystems with complexity comparable to a small processor. Large Scale Integration (LSI) implementation of the DMA controller has reduced the size to the stage where it can be incorporated on a single chip. DMA controller operation The figure below shows the basic structure of a DMA channel and due to it operating in a similar manner to the processor it has a full bus interface. The DMA controller has 3 independent channels; each channel contains an address register, a control register and a byte counter. To transfer a block of data between an external device or I/O port and memory the controller stores initial values in the address control and byte count registers. The DMA channel then transfers the block of information from or to memory according to the direction of the transfer encoded in the command register. The starting address of the block in memory is given by the address register, and the length of the block is given by the byte count. To make the transfer the

DMA controller has to synchronies the activities of the processor to the external device, before each transfer the controller waits for both the external device to be ready and the processor to be idle.

The structure of a typical DMA controller DMA interface with I/O Interfacing with the I/O port requires two signals per port-- TRANSFER REQUEST and TRANSFER ACK--plus the ability to generate I/O READ/WRITE L to indicate to the port the direction of the transfer. The DMA controller accepts a TRANSFER REQUEST from the port when the port has data ready to write into memory or has an empty buffer that can

accept data from memory. When a transfer is to take place, the DMA outputs the control signal TRANSFER ACK, which indicates the port should receive data from or write data into memory. Controller accessing memory As described before the DMA controller has a HALT request O/P signal and a HALT ACKNOWLEDGE I/.During the byte-by-byte transfer of a block of data, the controller watches for a TRANSFER REQUEST on channel. Then the controller asserts HALT and waits for HALT ACKNOWLEDGE. This instructs the processor relinquish the memory bus. When the processor relinquishes the bus it asserts HALT ACKNOWLEDGE and the DMA controller has access to memory. The controller simultaneously: 1. Places an address on the bus 2. Sends TRANSFER ACK to the requesting I/O port and 3. Sends the proper polarity of READ/WRITE L to memory and the complement of this signal to the I/O system. The I/O port and memory respond in opposite ways so that data moves from one to the other depending on the polarity of READ/WRITE L. At the completion of the memory cycle the DMA controller removes all of the signals placed on the bus and places its bus drivers in high impedance mode. With the HALT de asserted the processor can continue its operation from the point of suspension. In the DMA shown above there are three channels making it possible for the above operations to be multiplexed among the three separate I/O ports the microprocessor can be interrupted by the controller at the end of a block transfer? On responding to the interrupt the processor can reload the DMA registers for a new block transfer and thereby maintain the continuity often I/O flow. It is also possible to achieve the same affect by "chaining" the block transfers within the DMA controller. The " registers"

hold the address, byte count control word, plus ID channel which is the data to be used to reload the designated channel's register when that channel completes a transfer.

The 8237 DMA controller

The 8237 DMA controller supplies the memory and I/O with control signals and memory address information during the DMA transfer. The 8237 is a four-channel device that is compatible to the8086/8088 microprocessors and can be expanded to include any number of DMA channel inputs.

 The 8237 is capable of DMA transfers at rates of up to 1.6M bytes per

second.

 Each channel is capable of addressing a full 64K-byte section of

memory and can transfer up to 64K bytes with a single programming.

Some important signal pins:

DREQi (DMA request): Used to request a DMA transfer for

aparticular DMA channel.

DACKi (DMA channel acknowledge): Acknowledges a channel DMA

request from a device. HRQ (Hold request): Requests a DMA transfer. HLDA (Hold acknowledge) signals the 8237 that the microprocessor has relinquished control of the address, data and control buses. AEN (Address enable): Enables the DMA address latch connected to the 8237 and disable any buffers in the system connected to the microprocessor. (Use to take the control of the address bus from the microprocessor)

 ADSTB (Address strobe): Functions as ALE to latch address during

the DMA transfer. EOP (End of process): Signals the end of the DMA process.
IOR (I/O read): Used as an input strobe to read data from the 8237

during programming and used as an output strobe to read data from the port during a DMA write cycle. IOW (I/O write): Used as an input strobe to write data to the8237 during programming and used as an output strobe to write data to the port during a DMA read cycle. MEMW (Memory write): Used as an output to cause memory to write data during a DMA write cycle.MEMR (Memory read): Used as an output to cause memory to read data during a DMA read cycle. . INTEL 8255

 The INTEL 8255 is a device used to parallel data transfer between processor and slow peripheral devices like ADC, DAC, keyboard, 7segment display, LCD, etc. The 8255 has three ports: Port-A, Port-B and Port-C. Port-A can be programmed to work in any one of the three operating modes mode-0, mode-1 and mode-2 as input or output port. Port-B can be programmed to work either in mode-0 or mode-1 as input or output port. Port-C (8-pins) has different assignments depending on the mode of port-A and port-B. If port-A and B are programmed in mode-0, then the port-C can perform any one of the following functions. As 8-bit parallel port in mode-0 for input or output As two numbers of 4-bit parallel ports in mode-0 for input or output. The individual pins of port-C can be set or reset for various control applications. If port-A is programmed in mode- 1/mode-2 and port-B is programmed in mode-1 then some of the pins of port-C are used for handshake signals and the remaining pins can be used as input/ output lines or individually set/reset for control applications.
The read/write control logic requires six control signals. These signals

are given below. RD (low): This control signal enables the read operation. When this signal is low, the microprocessor reads data from a selected I/O port of the 8255A.

 WR (low): This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or the control register. RESET: This is an active high signal. It clears the control register and set all ports in the input mode. CS (low), A0 and A1: These are device select signals. They are, interfacing of 8255 with 8085 processor: A simple schematic for interfacing the 8255 with 8085 processor is shown in fig. Block diagram of 8255: The internal block diagram of 8255 is shown in fig:

 The INTEL 8255 is a device used to parallel data transfer between

processor and slow peripheral devices like ADC, DAC, keyboard, 7 segment display, LCD, etc. The 8255 has three ports: Port-A, Port-B and Port-C. Port-A can be programmed to work in any one of the three operating modes mode-0, mode-1 and mode-2 as input or output port. Port-B can be programmed to work either in mode-0 or mode-1 as input or output port. Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.

 If port-A and B are programmed in mode-0, then the port-C can

perform any one of the following functions.

As 8-bit parallel port in mode-0 for input or output.

As two numbers of 4-bit parallel ports in mode-0 for input or output.

The individual pins of port-C can be set or reset for various control

applications.
If port-A is programmed in mode- 1/mode-2 and port-B is

programmed in mode-1 then some of the pins of port-C are used for handshake signals and the remaining pins can be used as input/ output lines or individually set/reset for control applications. The read/write control logic requires six control signals. These signals are given below. RD (low): This control signal enables the read operation. When this signal is low, the microprocessor reads data from a selected I/O port of the 8255A. WR (low): This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or the control register. RESET: This is an active high signal. It clears the control register and set all ports in the input mode. CS (low), A0 and A1: These are device select signals. They are, Interfacing of 8255 with 8085 processor: A simple schematic for interfacing the 8255 with 8085 processor is shown in fig.

Block diagram of 8255: The internal block diagram of 8255 is shown in fig:

 The 8255 can be either memory mapped or I/O mapped in the system. In the schematic shown in above is I/O mapped in the system.
Using a 3-to-8 decoder generates the chip select signals for I/O

mapped devices. The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.
The address line A7 and the control signal IO/M (low) are used as

enable for the decoder. The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to A1 of 8255 to provide the internal addresses.
The data lines D0-D7 are connected to D0-D7 of the processor to

achieve parallel data transfer.

The I/O addresses allotted to the internal devices of 8255 are listed in

table.

PROGRAMMABLE INTERRUPT CONTROLLER - INTEL 8259 FEATURES OF 8259: It is programmed to work with either 8085 or 8086 processor. It manages 8-interrupts according to the instructions written into its control registers. In 8086 processor, it supplies the type number of the interrupt and the type number is programmable. In 8085 processor, the interrupt vector address is programmable. The priorities of the interrupts are programmable. The interrupts can be masked or unmasked individually. The 8259s can be cascaded to accept a maximum of 64 interrupts. FUNCTIONAL BLOCK DIAGRAM OF 8259: It has eight functional blocks. They are, 1. Control logic 2. Read Write logic 3. Data bus buffer 4. Interrupt Request Register (IRR) 5. In-Service Register (ISR) 6. Interrupt Mask Register (IMR) 7. Priority Resolver (PR) 8. Cascade buffer. The data bus and its buffer are used for the following activities. 1. The processor sends control word to data bus buffer through D0-D7

2. The processor read status word from data bus buffer through D0-D7 3. From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode and the processor. address (in case of 8085) through D0-D7 to

The processor uses the RD (low), WR (low) and A0 to read or write 8259. The 8259 is selected by CS (low).

The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the request is stored in IRR. It registers a request only if the interrupt is unmasked.

Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the interrupt request input are also programmable.

First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following,

1. Type of interrupt signal (Level triggered / Edge triggered). 2. Type of processor (8085/8086). 3. Call address and its interval (4 or 8) 4. Masking of interrupts. 5. Priority of interrupts. 6. Type of end of interrupts.

The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be masked. The relevant information is send by the processor through OCW.

The in-service register keeps track of which interrupt is currently being serviced.

The priority resolver examines the interrupt request, mask and inservice registers and determines whether INT signal should be sent to the processor or not.

The cascade buffer/comparator is used to expand the interrupts of 8259.

In cascade connection one 8259 will be directly interrupting 8086 and it is called master 8259.

To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be connected. The 8259s interrupting the master 8259 are called slave 8259s.

Each 8259 has its own addresses so that each 8259 can be programmed independently by sending command words and independently the status bytes can be read from it.

INTERFACING 8259 WITH 8085 MICROPROCESSOR

It requires two internal address and they are A =0 or A = 1. It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.

The low order data bus lines D0-D7 are connected to D0-D7 of 8259. The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal address.

The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for 8259.

The address lines A4, A5 and A6 are used as input to decoder. The control signal IO/M (low) is used as logic high enables for decoder and the address line A7 is used as logic low enable for decoder.

The I/O addresses of 8259 are shown in table.

Working of 8259 with 8085 processor:

First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following,

1. Type of interrupt signal (Level triggered / Edge triggered). 2. Type of processor (8085/8086). 3. Call address and its interval (4 or 8) 4. Masking of interrupts. 5. Priority of interrupts. 6. Type of end of interrupts.

Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7 it checks for its priority and also checks whether it is masked or not.

If the previous interrupt is completed and if the current request has highest priority and unmasked, then it is serviced.

For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085. In response it expects an acknowledge INTA (low) from the processor. When the processor accepts the interrupt, it sends three INTA (low) one by one.

In response to first, second and third INTA (low) signals, the 8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and loads the CALL address in PC and start executing the interrupt service routine stored in this call address.