Power Supply Analysis of a Large Area Integrated Circuit

Olivier Valorge
Institut des Nanotechnologies de Lyon Nano-Electronic Circuit Department Site INSA Lyon 7, avenue Jean Capelle 69621 VILLEURBANNE CEDEX

Walder Andr, Yvon Savaria

Department of Electrical Engineering cole Polytechnique de Montral, EPM Montral, (QC), Canada walder.andre@polymtl.ca

Yves Blaquire
Department of Computer Science Universit du Qubec Montral, UQAM Montral, QC, Canada

Abstract This paper introduces the power supply analysis of a large area integrated circuit (LAIC) used in a rapid prototyping platform for electronic systems. User integrated circuits deposited on this active LAIC surface receive power through configurable IOs. Strategies to distribute power all over a LAIC of the size of an entire wafer are described, modeled and their performances evaluated. Different scenarios have been investigated considering technological and physical constraints. A strategy has been implemented in a mature and low-cost 7metal layers CMOS 0.18 m technology. It uses advanced Through Silicon Vias (TSVs) to support up to 1000 W of power consumption. Detailed power analysis is provided. It is based on a finite element model (FEM) of the power grid. The FEM simulations allow determining the power density flowing through TSVs, as well as that flowing in the metal stripes which allows sizing these components in a way that meets electromigration and IR drop design constraints.

scale power supply structures have been done. Classical packaging techniques were just adapted to LAICs [2-3]. In this paper a novel design strategy for power supply distribution is developed and evaluated using finite element models (FEMs) with COMSOL Multiphysics [11]. The first contribution of this paper is the use of TSVs that are connected via solder balls to miniature PCBs from the backside of the wafer to supply ground and two levels of power (1.8 V and 3.3 V). The second contribution is to propose a model for the power grid that makes the power analysis possible with COMSOL in order to easily explore different design strategies: the number of power TSVs, as well as the dimension and pitch of the metal stripes to ensure good power integrity and acceptable power density. The following section briefly describes key elements of the physical structure of the configurable circuit board system first introduced in [1] and the power supply network architecture. The third section of this paper describes the power supply network architecture, while the fourth section presents the methodology for analysis of the IR drop as well as the current density in the metal grid of the proposed power supply architecture. Section V summarizes the main conclusions drawn from this work. II. THE WAFER SCALE CIRCUIT BOARD CONCEPT The WaferICTM active surface structure consists of a very dense array of very fine (tens of microns) conducting pads, with a compliant contact layer (e.g. Z-axis film, stamped metal spring contacts, anisotropic conductive film (ACF), wire embedded in elastomer, or sea of leads) [13] on top. The uICs can be placed anywhere on the wafer surface, and the NanoPads are dense enough that each component contact (e.g. solder ball) will touch several NanoPads. The active surface detects and maps the component contacts, and the internal WaferNetTM is then dynamically configured to establish any specified set of connections between the

I.

INTRODUCTION

A platform made of an active reconfigurable large area integrated circuit (LAIC) of the size of an entire wafer has been recently proposed to rapidly prototype digital systems [1]. This platform is designed to connect automatically together any integrated circuits (uICs) deposited on its surface by a user. This active surface is composed of several millions of very dense and small conducting pads, called NanoPads. When configured as a power supply, the NanoPad internal circuit provides a stable and regulated configurable VDD or ground to its uIC load. Two crucial problems in this LAIC are the power density and signal integrity. Powerful and robust power distribution structures are required to support advanced high power uICs. Designing a high performance power supply network that avoids dysfunctions of a LAIC and the uICs it supports is a significant challenge. In the past, wafer-scale integration was used to increase computational power in spite of limited available integration density [2-3]. Since then, no major developments in wafer-

pins/solder balls of those ICs, e.g. according to a user netlist. NanoPads can also connect power and ground pins of the deposited chip to the global WaferBoard power supply network. To dramatically simplify the design, a cell-based architecture was used. The Unit-Cell contains a piece of the internal connection and power networks and has NanoPads on its surface (Fig. 1). These cells are tiled within a reticle, and the WaferICTM is built from photo-repetition of this seaof-cells across the wafer, with inter-reticle stitching techniques to ensure connections between reticles [12]. The WaferIC is thus a sea of identical cells connected to each other through reconfigurable interconnect and power networks, coupled to a very dense array of NanoPads.
WaferIC

ground for all fields. Each field contains an array of TSVs, which is used to supply VDD power, ground and JTAG signals. Each miniature PCB is connected to 4 reticle image fields and has a power and ground wire for supplying current to the 3.3 V high voltage rail and to the 1.8 V low voltage rail. This miniature PCB has voltage regulators that can provide a current up to 20 A. Each NanoPad is capable of providing 100 mA to a uIC ball load.
Metal layers and power distribution uIC ball Conductive pad

ACF

Miniature side PCB Reticule image NanoPad

150m

TSV

Cu plating

Active area

Solder bump

Pitch 200 m

Figure 2: Through-Silicon Via to supply the WaferICTM from its backside. Unit Cell

Figure 1: The cell-based architecture of the WaferICTM.

III.

POWER SUPPLY NETWORK ARCHITECTURE

The prototyping platform for electronic systems explored in this project imposes a set of challenging physical constraints. For instance, its top-side active surface must be free of any custom electrical or mechanical structures to ensure good electrical contacts between balls of uICs deposited on an anisotropic conductive film (ACF) and conductive NanoPads (Fig. 2) [4]. A stratified structure that can support current flowing from a mm-scale structure (a classical printed circuit board for instance) to the micrometer scale one (the active silicon surface) is proposed. A back-side PCB is the master stage of the mechanical and power supply electrical structures [5]. It ensures a good thermo-mechanical stability but also a powerful and robust power supply and ground networks by using high conductivity metal planes, voltage regulators and discrete decoupling capacitances. Thermo-mechanical issues, not addressed here, are considered in complementary papers [6-7]. The active LAIC is soldered on an array of miniature PCBs. Through Silicon Vias (TSVs) are spread all over the LAIC to distribute power from the back-side to the top surface, as shown in Figure 2. The LAIC is divided into an array of identical reticle image fields of 17.92 mm 17.92 mm. These fields are made of 32 32 identical Unit-Cells of 560m 560 m, each of which containing a matrix of 44 conductive NanoPads (Fig. 5) [1]. At the wafer-scale, each reticle image field is independent regarding the VDD power supply, while there is a common

TSVs bring power to the active silicon surface, but other structures are needed to distribute the power to the configurable NanoPads on the whole WaferICTM surface. The NanoPads pitch (~100 microns) [1] is five times smaller than the densest ball pitch of advanced packages (~500 microns). Interleaved metal power and ground grids are used, as in digital integrated circuits [10], to connect all the configurable pads to the TSV arrays as shown in figure 3. Several configurable NanoPads can connect in parallel the deposited uIC pins to the ground or to a power supply voltage, depending on the configuration needed. Analog switches connect the power or ground IC pin to the right power metal grid.

Figure 3: Classical digital IC power grids. GND lines are shown in grey while PWR are in white.

IV.

IR DROP ANALYSIS WITH A FINITE ELEMENT METHOD

This section presents the results of a DC analysis of the power supply distribution network. Each stage of the network introduces a DC voltage drop that can be modeled by a discrete series resistance. For simplicity, the backside master PCB provides power and ground planes that are almost ideal when compared to CMOS layers as their thickness is much higher. The contribution of this backside PCB was estimated to be of the order of a few milliohms. TSV resistance has been measured in [4], and impedance of the order of 11 m per TSV have been reported. As the on-wafer power grid

provides many possible parallel paths for the current it carries, a detailed analysis is needed. To perform such a DC analysis, a complete reticle image of the LAIC has been taken into account. Four uIC power ball contacts are placed on the reticule image. Each uIC ball is assumed to be connected to 4 NanoPads. A. Current Propagation in On-Silicon Metal Grids In our proposed model for FEM simulation in COMSOL Multiphysics, the power grid is modeled by a conductive DC plane. Its resistivity depends on the power grid characteristics, such as width, thickness, pitch and conductivity of conductors composing the power rail. The conductive plane is powered by TSVs, which are represented by holes in our model, while the four contacted uIC pins are represented by 4 solid metal squares sinking of 400 mA each from the power grid. Figure 4 illustrates our model.

TABLE 1: VOLTAGE DROP AND EQUIVALENT RESISTANCE R BETWEEN THE 4 CONTACTS AND THE GLOBAL POWER NET AS A FUNCTION OF THE NUMBER OF TSVS PER RETICULE IMAGE FIELD.

Number of TSVs
1 22 33 55 88 10 10 19 19
TSV uIC Ball Contact

Voltage drop (mV)

543 482 195 88.3 68.5 64.2 41.8

Equivalent resistance (m)

1360 1205 488 221 171 161 105

IR drop

Current density

TSV Conductive plane

Contact

(a)

(b)

Figure 4: Power grid model of one reticle image for FEM simulations.

Figure 5 : An example of power grid simulation with a matrix of 88 TSVs : (a) voltage drop and (b) current density maps in a LAIC reticle image field for 400 mA per uIC power ball. TSV IR drop uIC Ball Contact Current density

The thickness of metal layers in CMOS technology is typically smaller than a micron. Thus, they cannot carry large currents. The metal grids capability can be enhanced by increasing the TSV density up to the minimum feasible PCB and TSV technology pitches. A main design parameter is the metal density that is defined as the ratio of on-silicon metal stripe width to pitch. Increasing the metal density obviously allows driving more current into the uIC power pins. However, this metal density has also an upper limit as metal layers are also used for routing. Once the model is complete, the next step is to determine the density of TSVs needed to support the maximum current. To do so, the resistance versus the density of TSVs has been extracted for a wire density of 6/30, which is the ratio of metal stripe width (6m) to pitch (30m). We used COMSOL Multiphysics to extract these values. Several simulations were done with different TSVs density. Then, the resistance of the on-silicon power metal grid was computed for each case. Our simulations results are summarized in Table 1. Figure 5 and 6 present examples of a power grid voltage drop and current densitiy maps induced by a circuit activity on a WaferICTM reticle. Based on these results, an array of 88 TSVs per reticle image field with a pitch of 2.23 mm was selected as a good engineering tradeoff solution for the actual implementation of the power supply network.

(a)

(b)

Figure 6 : An example of power grid simulation with a matrix of 1919 TSVs : (a) voltage drop and (b) current density maps in a LAIC reticle image for 400 mA per uIC power ball.

The maximum current per power pin is constrained to 400 mA. It assumes that each pin contacts with 4 NanoPads. From the computed voltage map shown in figure 5 (a), 6 (a) and table 1, it is clear that a large TSV density limits the voltage, decreasing at the same time the power and ground noise. The voltage drop over the metal grid was estimated to be only 68.5 mV when 400 mA are drawn per uIC ball (Fig. 5 (a)) [8-9]. Another limiting factor is electromigration. The current density map of figure 5 (b) shows that the maximum current density is around 0.274106 A/cm2 for a current sink

of 400 mA per uIC ball respectively. These current densities are far below the maximum allowed by the technology. According to our foundry (a CMOS 0.18m technology), a current density larger than 2106 A/cm2 for M1 (or larger than 1.106 A/cm2 for the other metal levels) can induce failures due to Joule heating. This encouraging result shows that the electromigration in the proposed power grid has a limited impact on the studied metal grid under high current stresses. B. Power Switches to Connect the Power Grids NanoPads are smart configurable IOs that can supply IC power pins. Bringing power from an IO to another IO is an innovative approach developed for the WaferBoardTM concept. For this feasibility study, basic analog switches embedded in each NanoPad connect the deposited uIC power or ground pin to the proper on-silicon grid. At first, a basic design approach is used. Those analog switches are large power MOS: pMOS to connect each uIC power pin to the WaferICTM power grid, and nMOS to connect each uIC ground pin to the ground grid. Those power MOS are controlled by the surrounding digital circuitry. The necessary power devices must be embedded in a 90 90 square microns region, the reserved part of the NanoPad area [1]. Some layout trials [1] led to a W/L transistor sizing of 2000 for the nMOS and 8400 for the pMOS driving the 1.8 and 3500 for the pMOS driving the 3.3V rails. The channel resistance is evaluated to 5 for each power MOS. Combining those four power MOS, a series resistance of 1.2 per analog switch is expected. This resistance value is almost ten times the metal grid series resistance. Therefore, the DC voltage drop in the power supply network of the WaferBoardTM is mainly due to the analog switches. A first method to reduce the analog switch series resistance is to use a finer CMOS technology to embed larger power MOS in each NanoPad. This has obvious negative consequences on cost and it impacts the maximum voltages that could be handled. A possible alternative approach to mitigate the impact of the voltage drop in the power supply distribution network is to modulate the conductance of output channel. This leads to the concept of a distributed voltage regulation included in each NanoPad that is under investigation. V. CONCLUSION A promising technology for rapid electronic system prototyping has been presented. A smart reconfigurable substrate allows connecting and powering ICs deposited on it. A new approach to analyze IR drop and current density in the power distribution network in a wafer-scale integrated circuit was presented. The power is provided through an array of Through Silicon Vias (TSVs) on the back side of this large area IC (LAIC). It is transmitted to the LAIC top active surface through a power distribution grid. It was shown that the proposed methodology based on finite element models allowed designing the power distribution grid (wire density and size) and the TSV density according to electromigration

and IR drop design constraints. This design exploration was not possible with conventional circuit simulation methods. ACKNOWLEDGMENTS The authors would like to acknowledge Gestion TechnoCap Inc, DreamWafer division Mitacs, FQRNT, NSERC, Precarn and CMC Microsystems for their support. REFERENCES
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