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DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:
Order Number DM74LS74AM DM74LS85ASJ DM74LS74AN Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram
Function Table
Inputs PR L H L H
H
Outputs D X X X H L L X Q H L Q L H
CLR H L L H
CLK X X X
H (Note 1) H (Note 1) H L Q
0
L H Q
0
X Either LOW or HIGH Logic Level L LOW Logic Level Positive-going Transition Q0 The output logic level of Q before the indicated input conditions were established. Note 1: This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (HIGH) level.
0 C to 70 C
65 C to 150 C
Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.
Parameter
Min 4.75 2
Nom 5
Max 5.25
Units V V
0.8 0.4 8 0 0 18 15 15 25 20 20 20 25 0 0 70 25 20
V mA mA MHz MHz ns
ns
Setup Time (Note 3)(Note 5) Setup Time (Note 4)(Note 5) Hold Time (Note 5)(Note 6) Free Air Operating Temperature
2 k , TA 2 k , TA 25 C, and VCC 25 C, and VCC 5V. 5V.
ns ns ns C
Note 5: The symbol ( ) indicates the rising edge of the clock pulse is used for reference. Note 6: TA 25 C and VCC 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage VCC VCC VIL VCC VIL IOL VCC VI Min, II Min, IOH Max, VIH Min, IOL Max, VIH 4 mA, VCC Max 7V Conditions 18 mA Max Min Max Min Min Data Clock Preset Clear IIH HIGH Level Input Current VCC VI Max 2.7V Data Clock Clear Preset IIL LOW Level Input Current VCC VI Max 0.4V Data Clock Preset Clear IOS ICC Short Circuit Output Current Supply Current
5V, TA 25 C. 2.125V with the minimum
Min
Typ (Note 7)
Max 1.5
Units V V
2.7
3.4 0.35 0.25 0.5 0.4 0.1 0.1 0.2 0.2 20 20 40 40 0.4 0.4 0.8 0.8
mA
mA
VCC VCC
20 4
100 8
mA mA
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedba ck from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V O and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 9: With all outputs OPEN, I isCC measured with CLOCK grounded after setting the Q and Q outputs HIGH in turn.
Switching Characteristics
at VCC Symbol 5V and TA 25 C From (Input) Parameter To (Output) CL Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time LOW -to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW -to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW -to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Clear to Q 30 35 ns Clear to Q 25 35 ns Preset to Q Preset to Q 25 30 35 35 ns ns Clock to Q or Q 30 35 ns Clock to Q or Q 25 25 15 pF Max RL 2k CL Min 20 35 50 pF Max MHz ns Units
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Ordering Code:
Order Number DM74LS74AM DM74LS85ASJ DM74LS74AN Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Los dispositivos estn tambin disponibles en cinta y carrete. Especifique aadiendo el sufijo;la letra "X" para el cdigo de pedido
Tabla de Funciones
Entradas PR L H L H H H CLR H L L H H H L CLK X X X D X X X H L X Q H L Salidas Q L H
H (Nota 1) H (Nota 1) H L Q
0
L H Q
0
X Logico Bajo o de alto nivel L Nivel logico bajo H=Nivel Logico alto Transicion pendiente positiva Q0 El nivel logico de la salida de Q fueron establecidos antes que las condiciones de entrada. Nota 1: Esta configuracin no es estable, es decir, no se mantendrn cunado cualquiera de las entradas regresan a su nivel inactivo (ALTO)
65 C to 150 C
Min 4.75 2
Nom 5
Max 5.25
Unidades V V
0.8 0.4 8 0 0 18 15 15 25 20 20 20 25 0 0 70 25 20
V mA mA MHz MHz ns
ns
Configuracion de la hora (Nota 3)(Nota 5) Configuracion de la hora (Nota 4)(Nota 5) Tiempo de espera (Nota 5)(Nota 6) Temperatura de funcionamiento al aire libre
2 k , TA 2 k , TA 25 C, and VCC 25 C, and VCC 5V. 5V.
ns ns ns C
Nota 5: El smbolo () indica que el flanco de subida del pulso de reloj se utiliza para la referencia. Nota 6: TA 25 C y VCC 5V.
Caracteristicas Electricas
Rango de temperatura ms recomendados de operacin al aire libre (a menos que se indique lo contrario) Simbolo VI VOH VOL Parametro Voltaje de entrada CLAMP Nivel Alto Voltaje de salida Nivel bajo Voltaje de salida II VCC VCC VIL VCC VIL IOL Min, II Min, IOH Max, VIH Min, IOL Max, VIH 4 mA, VCC Condiciones 18 mA Max Min Max Min Min Data Clock Preset Clear IIH Nivel alto Corriente de entrada VCC VI Max 2.7V Data Clock Clear Preset IIL Nivel bajo Corriente de eentrada VCC VI Max 0.4V Data Clock Preset Clear IOS ICC Salida de corriente de cortocircuito Corriente de suministro VCC VCC Max (Nota 8) Max (Nota 9) 20 4 0.25 0.4 0.1 0.1 0.2 0.2 20 20 40 40 0.4 0.4 0.8 0.8 100 8 mA mA mA A mA 0.35 0.5 V 2.7 3.4 Min Typ (Note 7) Max 1.5 Unidades V V
5V, TA
25 C.
Note 8: No ms de una salida debe ser corta en un momento y la duracin no debe exceder un segundo. Para dispositivos, con comentario s de las salidas, donde un cortocircuito en las salidas a tierra puede causar las salidas para cambiar el estado de la lgica una prueba equivalente pue den realizarse donde VO 2.125V con los lmites mximos y mnimos reducido por una media de sus valores establecidos. Esto es muy til cuando se utiliza equipo de prueba automtico. Note 9: Con todas las salidas abiertas,se mide con el reloj a tierra despus de ajuste de la Q y Q salidas alta alternadamente.
Caracteriticas de conmutacion
De (entrada) Simbolo at VCC 5V and TA fMAX tPLH tPHL tPLH tPHL tPLH tPHL Parametro 25 C a (salida) CL Min 25 Reloj a Q o Q 25 15 pF Max RL 2k CL Min 20 35 50 pF Max MHz ns Unidades
Frecuencia mxima de reloj tiempo de Retardo de propagacin salida bajo a alto nivel tiempo de Propagacin demora alto a bajo nivel de salida tiempo Retardo de propagacin salida bajo a alto nivel tiempo de Propagacin demora alto a bajo nivel de salida tiempo de Retardo de propagacin salida bajo a alto nivel demora de Propagacin en tiempo alto a bajo nivel de salida Clear a Q Clear a Q Preset a Q Preset a Q Reloj a Q o Q
30
35
ns
25 30
35 35
ns ns
25 30
35 35
ns ns
Circuito integrado de pequeo contorno 14-plomo (SOIC), JEDEC MS-120, 0.150 estrecho paquete nmero M14A
14-Plomo pequeo Outline Package (SOP), EIAJ tipo II, 5.3 mm ancho paquete nmero M14D