A Novel Simple And High Performance Structure For Improving CMRR: Application to Current Buffers and Folded Cascode

Ampilifier
Amir Hossein Miremadi
Islamic Azad University, West Tehran branch Tehran, Iran amirh_miremadi@yahoo.com

Hassan Faraji Baghtash

Iran University of science and technology (IUST) electrical and electronic engineering faculty/ Electronics research center Tehran, Iran hfarajii@gmail.com process signals in differential form rather than groundreference form. Another advantage of differential operation over the single-ended case is that the amplitude of the signal increases by the factor of 2[2]. An important parameter of differential active structures is the CMRR. Differential signals have the advantage of canceling common-mode interference from unwanted signals and/ or noise. So CMRR is one of the most significant parameters in many of the circuits which are processing differential signals; such as Op-amps, OTAs, current buffers, etc; hence its improving is a critical issue in these circuits. Any variation of the input stage tail current source in these circuits can significantly harm both deterministic and random components of the CMRR [3], [4]. There have been numerous attempts to improve CMRR [5]-[7]. Most of these references used schemes to increase tail output impedance such as using cascode current mirror. However most of these structures cause to increase minimum voltage requirement. Some other structures that used techniques which didnt need high output impedance tail need complicated implementation. On the other hand these structures need more power consumption and cause reduction in CMRR bandwidth. In this paper we proposed a simple and high effective cell which can be added to the circuits like folded cascode structure and it cause improvement in CMRR and PSRR; whereas it preserves CMRR bandwidths. This structure is composed of only four transistors and increases power consumption slightly. II. PROPOSED HIGH PERFORMANCE COMMON MODE
DEVIATING CELL

AbstractA novel and simple structure for improving CMRR is introduced. This structure can be added to the circuits like folded cascode amplifier, telescopic amplifier, current buffers, .etc to improve the CMRR of these circuits. This simple and effective circuit uses common mode deviating technique to improve CMRR at least 12dB while preserves CMRR bandwidth which is a novel technique in order to improve CMRR. Application of this structure in both current buffer and folded cascode structures are shown. Simulation results in TSMC 0.18m CMOS technology with HSPICE are presented to demonstrate the validity of the proposed circuit. In addition Monte Carlo analysis is performed to simulate the fabrication condition. Keywords- High cmrr; current buffer; analog circuits; mixed mode; low voltag;, low power

I.

INTRODUCTION

Today's Digital Signal Processing (DSP) is extremely on demand because of its natural benefits like reduced sensitivity to analog noise, enhanced functionality and flexibility, automated design and test, shorter design cycle, direct benefit from the scaling of VLSI technology, etc. But real world signals are analog; hence mixed-mode ICs are becoming progressively dominant i.e. System On Chip (SOC). In other words Mixed-mode signal processing attracts increasing attention since it simplifies design, enables compactness and reduces cost. However signal interference from the digital to the analog part remains a serious problem to overcome [1]; this is due to the fact that in a SOC, both analog and digital parts of circuit have the same substrate. In these circuits, analog parts must be resistant to the power supply interference coming from digital part. These variations which are caused by transient currents of digital circuits can cause undesired effects on power supply rails or analog circuits inputs as common mode. Hence both CMRR and PSRR play important roles in analog circuits. On the other hand, technology scaling imposes power supply to be lowered. Decreasing power supply imposes some restrictions on design procedure and harms common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR). Hence, for such circuits differential building blocks are accepted as a good solution. Therefore it is desired to

Fig .1 shows the conceptual schematic of the proposed common mode deviating cell. The main idea is using a circuit in parallel with signal path which has infinitive input resistance to the differential currents and zero to the commons. By using this idea we can deviates common mode currents and prevent them from going to the output. On the other hand differential currents cannot flow in this block because of infinite resistance to these signals ideally. Fig.2 shows transistor level implementing of this idea. This structure is composed of n-type transistors M1, M2, p-type transistors Md1, Md2 and current source of Ib. transistors Md1, Md2, and current source of Ib

978-1-4244-8973-2/10/$26.00 c 2010 IEEE

which form the differential pair, and transistors M1 and M2 make the deviation path for the common mode signals. Averaging property of differential pair is used to control gates of M1 and M2. When a differential signal is applied to the inputs of differential pair, its source voltage remains constant; but when its input signal is common, the circuit acts as a voltage follower and the source voltage follows its inputs. Using this property of differential pair we can control gate voltages of M1 and M2 so that, when the common signals are applied to the inputs of the proposed cell, voltage following property of differential pair aids a) transistors M1 and M2 to act as a diode and sink common mode currents; b) input impedance of Md1 and Md2 to increase because their VGS remains constant. On the other hand when a differential signal is applied to the cell inputs, gate voltage of transistors M1 and M2 doesnt change and these transistors show no action to this type of signals; this means resistivity of circuit to the differential signals is high significantly.

From (1) and (2) we can obtain common mode input impedance Rind and differential input impedance Rinc of the proposed circuit as follows.

1 Rinc = ro1,2 g m1,2 Rind = ro1,2

(3)

Where gm1,2 and ro1,2 are transconductance and output resistance of M1 (or M2) respectively.

rd = 0r rd = rc = c = 0

Figure 2. Transistor implementation of proposed common mode alienates cell

Figure 1. A conceptual schematic of proposed common mode alienates cell

Any deviation from ideal case leads to a decrease in CMRR. Here we used a simple current mirror to provide tail current of Ib. If considering small signal condition, Voutcm can be obtained from (1):

voutcm =

g md 1,2 rod 1,2 2rotail vincm 1 + g md 1,2 rod 1,2 2rotail

= (1 ) vincm
(1)

(a)

where Voutcm, Vincm, gmd1,2, rod1,2,rotail are common mode output voltage, common mode input voltage, transconductance of Md1 (or Md2 ), output resistance of Md1 (or Md2 ), output resistance of tail current source respectively, and is attenuation factor we defined here as =
1 1 + g md 1, 2 ( rod 1, 2 2 rotail )

where for differential mode input voltage Vindm and differential output voltage Voutdm , equal zero.

voutdm = 0

(b) (2)
Figure 3. (a) Conventional current buffer. (b) Proposed High CMRR current buffer.

III.

APPLICATIONS

IV.

SIMULATION RESULTS

The proposed structure is very simple, power efficient, and has low transistor number. This structure can be applied to the prevalent structures such as current buffers, folded cascode structures and cause significant improvement in CMRR and PSRR in these structures. Here we applied our proposed circuit to the current buffer and folded cascode OTA and compared the CMRR of them both. Fig .3 (a) shows a simple current buffer; differential input currents are applied to the Iin1 and Iin2 as shown in the fig .3 (a) and the output taken from Io1 and Io2. Applying proposed cell to the simple current buffer, the modified current buffer is obtained (See fig .3 (b)). For simple current buffer both differential and common mode input impedances are obtained from rin=1/gmc where for proposed current buffer we can obtain input impedance to the differential and common mode signals as rind=1/gmc and rinc =/gmc||roc where gmc and roc are transconductance and output impedance of Mc1 (or Mc2) respectively. A conventional folded cascode input stage is shown in fig .4 (a). Modified version of this is shown in fig .4 (b) (proposed). Differential and common mode input impedance for proposed OTA are the same as proposed buffer.

HSPICE simulation were performed using TSMC 0.18m CMOS technology at 1.8 V power supply. The transistors W/L are shown in table .1. Two circuits are simulated at the same condition to make comparison. Fig .5 shows frequency response of conventional and proposed current buffer. Differential and common mode input currents are applied to the both simple and proposed current buffer from in+ and inand output currents are taken from Io1 and Io2. The figure exhibits about 12 dB CMRR for proposed current buffer this is significant enhancement in CMRR value compared to its value in simple one.

Figure 5. CMRR of the proposed and conventional current buffer

Fig .6 shows the frequency response of the conventional and proposed folded cascode OTA. Differential and common mode input currents are applied to the both simple and proposed current buffer from in+ and in- and output currents are taken from Io1 and Io2. As shown in fig .6, the proposed circuit increases (up to 12 dB) the CMRR whereas it preserves CMRR bandwidth. Preserving CMRR bandwidth is very interesting feature of this circuit which is not accessible in other similar works. (a)

Figure 6. CMRR of the proposed and conventional folded cascode OTA

(b)
Figure 4. Conventional folded cascode OTA. (b) Proposed High CMRR folded cascode OTA.

Monte Carlo analysis is performed by 3% variation on transistors aspect ratio to simulate fabrication condition. Fig .7 shows Mont Carlo analysis for both simple and proposed current buffer. Comparison of Mont Carlo analysis for simple and proposed folded cascode OTA is shown in fig .8. As shown, CMRR of proposed circuits increased at least 10 dB in comparison with the conventional structures.

TABLE I. OTA ELEMENT

W Proposed L W

TRANSISTORS ASPECT RATIO Current Buffer

conventional L W Proposed L W conventional L

M1 M2 Md1 Md2 Mc1 Mc2 Mm1 Mm2 MI1 MI2 Mmp1 Mmp2

0.36 m 0.36 m 27 m 27 m 5.4 m 5.4 m 3.6 m 3.6 m 3.6 m 3.6 m 2.7 m 2.7 m

0.18 m 0.18 m 0.18 m 0.18 m 0.54 m 0.54 m 0.54 m 0.54 m 0.18 m 0.18 m 0.54 m 0.54 m

NA NA NA NA 5.4 m 5.4 m 3.6 m 3.6 m 3.6 m 3.6 m 2.7 m 2.7 m

NA NA NA NA 0.54 m 0.54 m 0.54 m 0.54 m 0.18 m 0.18 m 0.54 m 0.54 m

NA NA NA NA 5.4 m 5.4 m 3.6 m 3.6 m NA NA NA NA

NA NA NA NA 0.54 m 0.54 m 0.54 m 0.54 m NA NA NA NA

NA NA NA NA 5.4 m 5.4 m 3.6 m 3.6 m NA NA NA NA

NA NA NA NA 0.54 m 0.54 m 0.54 m 0.54 m NA NA NA NA

and cause CMRR to improve in these circuits. This simple and high effective circuit uses common mode deviating technique to improve CMRR while preserves CMRR bandwidth which is a novel technique in order to improve CMRR. Application of this structure on both current buffer and folded cascode structures are shown. Simulation results in TSMC 0.18m CMOS technology with HSPICE are presented to demonstrate the validity of the proposed circuit. Mont Carlo analysis is performed for simulating fabrication condition and corroborated the appropriate performance of the proposed circuit. ACKNOWLEDGMENT This work is supported by Islamic Azad University, West Tehran branch.
Figure 7. Monte Carlo analysis of conventional and proposed current buffer. - -) Simple. - ) Proposed

REFERENCES
[1] Shahram Minaei ,I. Cem. Go knar, Oguzhan Cicekoglu, "A new differential configuration suitable for realization of high CMRR, allpass/notch filters," Springer-Verlag, p. 317326, May 2005. Allen PE, Holberg DR, CMOS analog circuit design, 2, Ed. New York: Oxford University Press, 2002. C.-G. Yu and R. L. Geiger, "Nonideality consideration for highprecision amplifiersAnalysis of random common-mode rejection ratio," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 40, no. 1, p. 112, Jan. 1993. F. You, S. H. K. Embabi, and E. Sanchez-Sinencio, "On the commonmode rejection ratio in low voltage operational amplifiers with complementary N-P input pairs," IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process., vol. 44, no. 8, p. 678683, 1997. Vadim Ivanov, Junlin Zhou, and Igor M. Filanovsky, "A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, vol. 54, no. 5, pp. 397-401, May 2005. Vadim Ivanov, Junlin Zhou, Igor Filanovsky, "A 100 dB CMRR CMOS Operational Amplifier With Single-Supply Capability," IEEE., pp. 9-12, 2004. Jaime Rmirez-Angulo, Sandhana Balasubramanian, Antonio J. LpezMartin, and Ramn G. Carvajal, "Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, vol. 55, no. 12, pp. 1229-1233, Dec. 2008

[2] [3]

[4]

[5]

Figure 8. Monte Carlo analyses of conventional and proposed folded OTA. -) Simple. - ) Proposed

[6]

[7]

I.

CONCLUSION

A novel and simple structure for improving CMRR was introduced. As shown, this structure can be added to the circuitries like folded cascode amplifier, current buffers, etc.;