CS421ComputerPeripheraland Interfacing

8086 processor Architecture S. Tripathy IIT Patna

8086Microprocessor 8086 Microprocessor

Salient features
A 40 pin d l i li package. i dual in line k It requires +5V power supply. It is a 16 bit p. 8086 has a 20 bit address bus

operates in two modes.

Multiplexed address and data bus AD0 AD15 and A16 AD0A16 A19. It can support upto 64K I/O ports. I provides 14 16 bi registers. It id 14, 16-bit i It can prefetch upto 6 instruction bytes from memory and queues them to speed up instruction execution q p p Minimum and Maximum.

can access upto 1 MB memory locations .

Pindiagramof8086

FunctionalBlockdiagram8086 Functional Block diagram 8086

Signalsin8086 Signals in 8086

3 different sets of si nals (not standard division) 3-different signals
Common to both minimum and maximum modes Specially included in minimum configuration p y fg Specially included in maximum configuration

Si Signals Common to both MN/ MX mode l C t b th d

AD15-AD0 : These are the time multiplexed memory/ I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.

Commonsignals(Contd.) Common signals (Contd.)

A19/S6 A18/S5 A17/S4 A16/S3 : These are the time A19/S6,A18/S5,A17/S4,A16/S3 multiplexed address and status lines. During T1 these are the most significant address lines for memory operations. m m p ti ns During I/O operations, these lines are low. During memory or I/O operations, status information is g y p , available on those lines for T2,T3,Tw and T4. Status bit S6 is always logic 0 0, S5 indicates the condition of the IF flag bit S4 and S3 combined to indicate which segment register is presently being used for memory accesses

Commonsignals(Contd.)
BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus D15 D8 BHE
0 0 1 1

A0
0 1 0 1

indication
Whole word Upper byte from /to odd address Lower byte from/to even address none

BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold hold. S7 is not used currently

Commonsignals(Contd.) Common signals (Contd )

RD Read : Indicates the peripheral that the p p processor is performing a memory or I/O read f / d operation.
RD is active low and shows the state for T2 T3 Tw of T2, T3, any read cycle. The signal remains tristated during the hold acknowledge. acknowledge

READY : This is the acknowledgement from the slow device or memory that they have completed the d t t nsf th data transfer.

The signal made available by the devices is synchronized by the 8284A clock generator to provide y y p ready i d input to th 8086 th signal i active hi h t t the 8086. the i l is ti high.

Commonsignals(Contd.)
INTR-Interrupt Request : This is a level triggered input.
It is observed during the last clock cycles of each instruction to determine the availability of g y y the request. h If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag.

TEST: This input i examined b a WAIT instruction. TEST Thi i t is i d by i t ti

If the TEST pin goes low, execution will continue, else the processor remains in an idle state.

NMI- Nonmaskable interrupt : This is an edge triggered input which causes a type 2 interrupt. The NMI is not maskable internally by software interrupt software. RESET : This input causes the processor to terminate the current activity and start execution from FFFF0H CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. MN/MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode.
Its an asymmetric square wave with 33% duty cycle.

8086signals(Mn 8086 signals (Mn mode.)

M/IO Memory/IO : This is a status line logically equivalent to S2 in maximum mode.
When it is low, it indicates: the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus hold acknowledge . The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle cycle.

HOLD, HLDA: Wh n the HOLD line goes high, it indicates to HLD When th n go s h gh, t n cat s the processor that another master is requesting the bus access.

INTA DT/R, DT/R DEN, ALE

Signalpinsformaximummode
S2, S1, S0 Status Lines : These are the status lines which reflect the type of operation, being carried out by the processor processor.

LOCK : This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low. low The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction

SignalsinMXmode
QS1, QS0 Queue Status: These lines give information about the status of the code-prefetch queue.

The 8086 architecture has 6 byte instruction 6-byte prefetch queue. Thus even the largest (6bytes) instruction can be prefetched from the y ) p f f m memory and stored in the prefetch.

InternalArchitectureof8086 Internal Architecture of 8086

BIUandEU BIU and EU

8086 has two blocks BIU and EU. BIU B
performs all bus operations such as instruction fetching, reading and writing operands for memory calculating the addresses of the memory operands operands. The instruction bytes are transferred to the instruction queue. BIU contains Instruction queue, Segment registers, Instruction pointer, pointer Address adder executes instructions from the instruction system byte queue. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register

EU

Both units operate asynchronously to give the 8086 an p y y g overlapping instruction fetch and execution mechanism which is l f h d h h h called as Pipelining.
This results in efficient use of the system bus and system performance. performance

Registersin8086

FlagRegister Flag Register

Ex.: Ex : Find the status of the flags CF ,SF, AF after the following SF instructions are executed MOV AL,35H ADD Ax 0CEH Ax,0CEH

BusOperation(Simplified) Bus Operation (Simplified)

M Memory Write W
outputs the memory address on the address bus outputs the data to be written on the data bus iss s a write (WR) issues it to memory and IO/M 0 for IO/M= 8088 and M/IO = 1 for 8086

Busoperation Bus operation

All the processor bus cycles consist of at least four clock p y f f cycles. T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle s During T2, the bus is tristated for changing the direction of bus for the following data read cycle. The data transfer takes place during T3, T4 T3 T4. In case, the address device is slow NOT READY status / wait status Tw are inserted between T3 and T4. Th address l t h enable (ALE) signal i emitted d i T1 The dd latch bl i l is itt d during by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN/MX input Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4 T4.

Blockdiagramof8086MPU(Minimummode)

BusoperationinMinimummode Bus operation in Minimum mode

Blockdiagramof8086MPU(Maximummode)

MemoryReadCycle(Maximummode)

MemorySegmentation Memory Segmentation

E h address i 20 bit Each dd is
But address registers are only 16 bits long. l l There are four types of memory segments. data, d code, stack and another data segment called the d t s m nt c ll d th extra segment CS DS SS ES CS,DS,SS,ES

SegmentsandCorrespondingRegisters UsedforSpecifyingOffSets

Memoryorganization
Total memory size is 1MB Program memory:
Program, data and stack occupies the space P Processor can effectively use 16-bit address, so 64KB ff ti l 16 bit dd Program can be located anywhere in memory. It can be called through short jump in currently located 64KB segment or far jump through 1MB Processor can access data in any one of 4 available segments (using segment_name:, DS:). So limit upto 256KB Stack can be any where in the memory y y 0000h - 03FFh are reserved for interrupt vectors.
Each interrupt vector is a 32-bit pointer in format segment:offset.

Data memory:

Stack Memory:

Reserved memory:

FFF0h - FFFFh : After reset the processor starts from FFFF0