Design Rules & Fabrication

Somayyeh Koohi
Department of Computer Engineering Sharif University of Technology
Adapted with modifications from lecture notes prepared by author

Topics
Design rules and fabrication SCMOS scalable design rules Stick diagrams

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Why we need design rules

Masks are tooling for manufacturing Manufacturing processes have inherent limitations in accuracy Design rules specify geometry of masks which will i l if f k hi h ill provide reasonable yields
Spacing Minimum-width rule Avoid small negative feature

Design rules are determined by experience

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Manufacturing problems
Photoresist shrinkage tearing Variations in material mask Variations in temperature Variations i oxide thi k V i ti in id thickness
Variation in Vt

Impurities Variations between lots

Lot consists of multiple wafer

Variations across a wafer

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Transistor problems
Variations in threshold voltage:
oxide thickness ion implantation poly variations

Changes in source/drain diffusion overlap

Variation in effective channel length

Variations in substrate
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Wiring problems
Diffusion:
Changes in doping variations in resistance, capacitance variations in resistance,

Poly, metal:
Variations in height, width capacitance

Shorts and opens:

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Oxide problems
Variations in height Lack of planarity step coverage
metal 2 metal 2 metal 1

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Via problems
Via may not be cut all the way through Undersize via has too much resistance Via may be too large and create short

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Topics
Design rules and fabrication SCMOS scalable design rules Stick diagrams

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MOSIS SCMOS design rules

1. Designed to scale across a wide range of technologies 2. 2 Designed to support multiple vendors 3. Designed for educational use Therefore, fairly conservative

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and design rules

2 is the size of a minimum feature Specifying particularizes the scalable rules Parasitics are generally not specified in units m-based design vs. -based design

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Scaling
Scale all chip parameters by x:
W -> W/x, L -> L/x, V -> V/x, etc.

Transistor current shrinks:

I/I = 1/x (EQ. 2-28) ( )

Capacitance shrinks Resistance unchanged

So chip speeds up (CV/I)/(CV/I) = 1/x

Shrinking makes chip faster and smaller

More later
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Wires
6 3 3 3 2 metal 3 metal 2 metal 1 pdiff/ndiff poly

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Transistors
2 3 2 3 1 5

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Vias
Types of via:
metal1/diff metal1/poly metal1/metal2
4 1 2 4

No direct connection between metal2/metal3 and poly

Connection through metal1
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Metal 3 via
Type: metal3/metal2 Rules:
cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2
5 1 3

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Tub tie
Tub to power supply
4 1

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Spacings
Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 y Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4 Diffusion/tub wall: 5
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Topics
Design rules and fabrication SCMOS scalable design rules Stick diagrams

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Stick diagrams
Is a cartoon of a layout Shows
All components/vias (except possibly tub ties) Relative placement

Not show
Exact placement Transistor sizes Wire lengths Wire widths Tub boundaries
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Stick diagrams (contd)

Just horizontal & vertical lines Crossing materials:
Similar: Connected Dissimilar: Unconnected
Unless connection is established through a via

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Stick diagrams (contd)

m2
Short O O O O

m1
O Short O O O

poly
O O Short O O

ndiff
O O NMOS Short O

pdiff
O O PMOS illegal Short

m2 m1 poly ndiff pdiff

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Stick layers
metal 3 metal 2 metal 1 poly ndiff pdiff

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Dynamic latch stick diagram

VDD

in

out

VSS

phi

phi
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Sticks design of multiplexer

Start with NAND gate:
+

out b a

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NAND sticks
VDD a out

VSS
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One-bit mux sticks

VDD
ai bi select a out t a out t a out

N1 (NAND)
b

N1 (NAND)
b

select

N1 (NAND)
b

VSS
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3-bit mux sticks

select ai bi select select select VDD oi VSS VDD oi VSS VDD oi VSS a2 b2

m2(one-bit-mux)

o2

a1 b1 a0 b0

ai bi ai bi

select

select

m2(one-bit-mux)
select select

o1

m2(one-bit-mux)

o0

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Layout design and analysis tools

Layout editors are interactive tools
Magic L-edit

Design rule checkers are generally batch

identify DRC errors on the layout

Circuit extractors extract the netlist from the layout Connectivity verification systems (CVS) compare
extracted and original netlists
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Automatic layout
Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea-of-gates layout creates layout cell/sea of gates from pre-designed cells + custom routing
Sea-of-gates allows routing over the cell

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Standard cell layout

routing area routing area rea

routing area ting area

routing area

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