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# VLSI Lab Part B (06ECL77)

EXPERIMENT-1

INVERTER
1.1 Schematic design using S-Edit:

Design Description:
In digital logic an Inverter or a NOT gate is a logic gate which implements logical negation.

TSpice Commands:
.tran 10n 100n .dc lin source v1 0 5 0.1 .lib "C:\Tanner\vtuexperiments\INV\Generic_025.lib" TT v1 a GND BIT ({10101}) v2 vdd GND 5 .print tran v(a) v(y) .print dc v(y) .op .end

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1.4 Waveform:

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EXPERIMENT-2

## SINGLE STAGE AMPLIFIER

2.1 Schematic design using S-Edit:

Design Description:
The need of the amplifier is to amplify the weak input signal coming from transducers so that while traveling a longer distance signal or power would not get distorted and at the output stage we want, if we required lesser gain we will go for single stage amplifier. The predicted output gain of single stage amplifier should be 35 dB.

Tspice Commands:
v1 vdd GND 5 v2 vref GND 0.8 v3 vinn GND 1.3 v4 vinp vinn SIN (0 2m 1k) AC 1 .tran .5m 5m .dc lin source v4 -5 5 .1 .ac dec 10 10 10g .print tran v(out) v(vinp) .print dc v(out) .print ac vdb(out) .lib "C:\IMS\Technology_file\Generic_025.lib" TT .op .end

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Design:

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2.3 Waveform:

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EXPERIMENT-3

COMMON SOURCE

## 3.1 Schematic design using S-Edit:

Design Description:
A common-source amplifier, which amplifies the input voltage about 30 times. The gain of this amplifier is determined partly the transconductance of the MOSFET. This depends on the bias point in the circuit. This means that a change in the gate voltage causes a change in the drain current. The drain current goes through a resistor. The capacitor connected to the source is supposed to act as a short circuit at the input frequency, so it and the source resistor can be ignored. A change in input causes a change in drain voltage. The predicted output gain is of common source amplifier should be 56.18 dB.

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## VLSI Lab Part B (06ECL77)

TSpice Commands:
v1 vdd GND 5 v2 vref GND 3.87 v3 vinm GND 3.2 v4 vinp vinm SIN (0 2m 1k) AC 1 .tran .01m 5m .dc lin source v4 -5 5 .1 .ac dec 10 1 10g .lib "C:\IMS\Technology_file\Generic_025.lib" TT .print tran v(out) v(vinp) .print ac vdb(out) vp(out) .print dc v(out) .op .end

Design:

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3.3 Waveform:

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## VLSI Lab Part B (06ECL77)

EXPERIMENT-4

COMMON DRAIN
4.1 Schematic design using S-Edit:

Design Description:
Common-drain amplifier is also known as source follower or grounded drain amplifier the voltage at the source follows that the gate giving the circuit its popular name of source follower. It finds application in situation in which we need to connect a voltage signal source that is providing a signal of reasonable magnitude but has a very high internal resistance to much smaller load resistance that has a unity gain voltage buffer amplifier. The predicted output gain is of common drain amplifier should be 57dB.

TSpice Commands:
v1 vdd GND 5 v2 vref GND 3.79 v3 vinm GND 3.1 v4 vinp vinm SIN (0 2m 1k) AC 1 .tran .01m 5m .dc lin source v4 -5 5 .1 .ac dec 10 1 10g .lib "C:\IMS\Technology_file\Generic_025.lib" TT
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## VLSI Lab Part B (06ECL77)

.print tran v(y) v(vinp) .print ac vdb(y) vp(y) .print dc v(y) .op .end

Design:

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4.3 Waveform:

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## VLSI Lab Part B (06ECL77)

EXPERIMENT-5

R-2R DAC
5.1 Schematic design using S-Edit:

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## VLSI Lab Part B (06ECL77)

Design Description:
An alternative to the binary weighted-input DAC is so called R/2R DAC which uses fewer unique resistor values. DAC design required several different precise input resistor values :one unique value per binary input bit. The bits, either at 0 or operating voltage, enter the network via a resistor of a double value than the rest of the network. Each bit contributes its part to the resulting voltage on the output

TSpice Commands:
v1 vdd GND 5 v2 vin GND 2.5 v3 b0 GND PULSE (5 0 0 1n 1n 500n 1000n) v4 b1 GND PULSE (5 0 0 1n 1n 1000n 2000n) v5 b2 GND PULSE (5 0 0 1n 1n 2000n 4000n) v6 b3 GND PULSE (5 0 0 1n 1n 4000n 8000n) .tran 10n 8500n .print tran v(y) .lib "C:\IMS\Technology_file\Generic_025.lib" TT .op .end

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5.3 Waveform:

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## VLSI Lab Part B (06ECL77)

APPENDIX
PROCEDURES FOR SCHEMATIC EDIT Open the S Edit Go to File New New Design Design Name Browse My Computer Create new folder Folder name OK Go to cell New Cell View OK Go to file Open file add library My computer c:\tanner\VTU Experiments\Inv\libraries\All\All.tanner OK Window will be displayed on the screen.[zoom in for and zoom out for +] Draw the schematic diagram by using Devices and Miscellaneous(misc) Save Go to file Export Export Spice Browse Open your folder [F or D or E] name and file name save it with .spc extension file Export Minimize the window. Open the T Spice file.[Open drive F or D or E:\foldername\Filename] Go to insert command insert command in the T Spice file Save Run Checkout the waveform in W-Edit. PROCEDURES FOR LAYOUT EDIT [L - EDIT] Open the L Edit Close the Cell window appear on the screen Go to File New file Select layout (.tdb) Browse c:\tanner \ vtu experiments \ inverter\layout\generic_0.25\generic 0.25.tdb\ OK Go to cell copy or press c in the keyboard Browse c;\tanner\vtu experiments\auto layout\auto layout\select particular experiment name OK Go to cell Instance or Press I in the keyboard Select particular experiment name OK Layout will be displayed on the screen Go to cell Flatten Yes Go to tools Extract or setup extract icon Select Extract Standard rule set Click on the pencil symbol General Browse c:\tanner\vtu experiments\inv\ayoutganeric_0.25.ext Select open
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## VLSI Lab Part B (06ECL77)

General Browse my computer Goto layout folder select the location for layout spice file (.spc) & save it. Output Spice include statement [Delete the content in the Box] OK Extract the layout details Click on EXT Open the T Spice file Insert the command in the T Spice Save Run Check out the waveform in W-Edit. PROCEDURES FOR LAYOUT VERSUS SCHEMATIC ( LVS EDIT) Open the LVS Edit File New LVS setup OK In Layout net- list browse the Layout T Spice file In Schematic net-list browse the schematic T Spice Run Check whether Circuits are equal.

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