A Design of Network Remote Control System

Wang Tao

Gong Cheng

College of Physics and Electronic Engineering Taizhou University TaiZhou, China Twang61@sina.com
3

College of Physics and Electronic Engineering Taizhou University TaiZhou, China robotlu@126.com

Li Hai-xia

Department of Mathematics Taizhou Junior Middle School Linhai, China Lihaixia_79@163.com

AbstractThis paper describes a design of network remote control based on Ethernet controller RTL8019AS and FPGA chip EP3C25Q240C8N. It's through the Altera NIOS II soft-core processor and a simplified TCP/IP protocol LWIP to complete the Ethernet Communication Protocol, and FPGA can configure and control RTL8019AS. Then the information can be communication between FPGA and PC, in order to achieve network remote control and information transmission. Keywords-Network Remote Control;FPGA;RTL8019AS

Zhang Yun* School of Information Science and Technology Zhejiang A&F University Linan, China Zcc-jdd@163.com
using Altera's NIOS II soft-core processor and a simplified TCP/IP protocol to implement Ethernet communication protocol LWIP, enabling FPGA to control and configure RTL8019AS. Then the information can be communication between FPGA and PC machines, and achieving network remote control. This method of using software to realize network protocol has space-saving and lower cost advantages. More importantly, you can always configure or modify a variety of protocols, and can follow the development of future through software upgrade. The overall circuit diagram of the system shown in Figure 1.

I.

INTRODUCTION

With the development of computer technology, network everywhere. In order to make better use of network resources, the various devices are added with the network ports; let's access the network anytime, anywhere. Its from the PC network system to the PDA witch can be connected to network, and is widely used in the application of MCU network system can be seen, there is now the requirements of the network connection is not satisfied, but for the networked devices more intelligent and more compact. Embedded system is a good choice, the combination of embedded systems with Ethernet idea has a long time, the main difficulty that was the Ethernet speed and a great lack of certainty, can not meet the requirements of industrial communication network. In addition, the TCP/IP protocol of existing Internet technology is complex, very rich, mainly used in connection with the PC, if applied to the embedded system is its memory capacity and computing speed requirements such as relatively high, embedded systems Apart from some more than 32-bit processors, can not meet this requirement, so the extensive use of industrial automation is far too expensive, does not apply. Therefore, decreasing hardware costs, simplify TCP/IP protocol implementation has a special practical significance. II. SYSTEM HARDWARE DESIGN The design uses FPGA chips EP3C25Q240C8N, FLASH chip JS28F640, SDRAM chip HY57V641620, LCD1602, nixie tubes and LED to compose FPGA system. Then the FPGA system with network control chip RTL8019AS and network interface RJ45 build the design of the hardware platform. And

Figure 1. System circuit diagram.

III.

SYSTEM SOFTWARE DESIGN

First we create a project using Quarter II software, and then customize a NIOS II kernel by SOPC Builder. The kernel is mainly adding the following system components: NIOS CPU, the timer component, Avalon tri-state bus bridge, Flash, SDRAM and Ethernet components RTL8019AS, etc. Add Ethernet component RTL8019AS is different from other components, because in NIOS system comes with only the CS8900 and LAN91C111 two Ethernet controllers, but not

978-1-61284-459-6/11/$26.00 2011 IEEE

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RTL8019AS component, so we must own to add this component. Follow these steps to add components: in the File menu, click New Component command to start the New Component tool, click the header on the dialog box, enter the Signals page, click the Add Signal button to add the 7 signals; into the Interface page, in the Type column select Avalon_tristate_slave option, in Avalon slave addressing section select the registers (native) option, units selected ns, step is set to "100", read wait and write wait is set to "150", hole is set to "100"; back to the signals page of each signal nam , signal type, width, direction setting as shown in Figure 2, A for the address lines, D for data lines, CS_n for the chip select signal, irq is the interrupt request signal, iro_n as read command signal, iow_n to write command signal, rst for the reset signal; into the component wizard page, component name is set to ctrl_rtl8019, component group is set to my component, click the finish button, generate a new element; back Sopc builder, look at my component group ctrl_rtl8019 components, added to the system, and named. SOPC Builder appoints a default base address for each IP block of users system. The IP module's base address of the design is specified by the system automatically [1]. Add the design of each module shown in Figure 3.

Figure 2. Set the Ethernet component

diagram.

A. RTL8019AS Initialization The RTL8019AS registers can be divided into two groups based on the address and function: a set of NE2000compatible, and the other on the plug and play. The main use of this design is the first set of compatible NE2000 registers. Include four pages: Page 0 Page 3. The design mainly Initialize the relevant register of page 0 and page 1, the register of page 2 is read-only, and can not set; the register of page 3 is not compatible with NE2000, do not set. The system used in the registers and their configuration values are as follows: CR=0X21, is command register, select page 0 register; TSR=0X45, is send status register, send the page start page address, initialized to point to the first send buffer page, i.e. 0X40; PSTART=0X4C, PSTOP = 0X80, build buffer ring: 0X4C ~ 0X80; BNRY=0X4C, set the pointer; RCR=0XCC, is receive configuration register, set the receive configuration register, use the receive buffer, only to receive their address data reporting (and the broadcast address packets) and multicast address packets, dropped packets is less than 64 bytes, the school wrong test does not receive the packet; TCR=0XE0, is send configuration register, enable CRC automatic generation and automatic check, work in normal mode; DCR=0XC8, is set data configuration register, use the FIFO buffer, normal mode, 8-bit data DMA; IMR=0X00, set the interrupt mask register, mask all interrupts; CR=0X61, select register of Page 1; CURR=0X4D, CURR is RTL8019AS write memory pointer, point the next page of current writing page, initialization is referring to its sum 0X4C+1=0X4D; MAR0-MAR5, all set to 0X00; PAR0-PAR5, set LAN address register, the node-based MAC address; CR=0X22, is register of select Page 1, enter the normal working condition [3]. B. TCP Sending Process The application program intends to send the TCP data stream, the first calls tcp_write(). Tcp_write() will check the connection status at this time, to send data corresponding to the current connection to be effective in the state, if the state is invalid error, code is returned, then tcp_write() transfers control to the tcp_enqueue(). Tcp_enqueue() first checks the length of the data to be transmitted. Because the data to be sent to wait in line, so the amount of data on the queue to be sent per connection buffer size limit, too much data will be queued to tcp_enqueue() failed to return; and then the send data to be broken into the appropriate size of the TCP segment, primarily for sending data to be assigned a certain number of pbuf and tcp_seg data structure, and make links the pbuf to tcp_seg buffer list; Finally, place these TCP segments into the transmission queue of current connection, ready to transfer. Tcp_output() check the current connected TF_ACK_NOW identifier is valid or not, if the identifier is valid and the

Figure 3. Add the IP block diagram

Because NIOS and SDRAM require the same clock, so the design uses a set of PLL. So that we can compensate SDRAM input clock by PLL, the SDRAM work. The design also uses a delay module to reset the system stability. All of these modules will be added to the corresponding interface, and ultimately to build a complete NIOS system [2]. After building NIOS system, write programs that run in its. In this description because of space limitations only describing the realization of network communication, the process is as follows.

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transmit queue is empty or does not allow the window, immediately construct ACK response and send; transmission queue has data to be sent and the window allows, then call the function tcp_output_segment() to send the data with ACK, and finally send the data into the connection control block "does not answer ((Unasked)" queue. Next the awaiting send packet will be processed by the function ip_route() and ip_output_if(). First need to specify a network interface for data output, ip_route() function is used in the network interface list to linear search for a suitable network interface, if there is no matching interface, use the default network interface. Once the output interface is determined, then send the interface as a parameter to ip_output_if(), which is used to send IP packets on the network interface. The function structures the IP header and calculates the IP header checksum. If the source IP address is NULL, then the output of the network interface IP address as the source IP address to be filled in. After the data format is constructed, we can call the send program of network driver to send the data to the network [3]. C. TCP Receiving Process We call the receiving program of network driver by interrupt, and send the received network data to the above layer function ip_input(). Ip_input() test IP version number, the header degrees, first calculate and test the header checksum, restructure the sectionalized IP packet and so on. Next, the function search network interface list linearly, compare each network interface IP address of list and the purpose IP address of data packets, if found matched network interface, then the network interface as a parameter and packet submitted to the top together, or call ip_forward () to forward IP packets. Tcp_input() initialize the TCP input. Look up every protocol control block, find the received segment belong to which active TCP connections, and send the characterization of the connection protocol control block as an argument to tcp_process(). The function implements the TCP state machine, and to achieve a state of transition. If the current connection is the state of receiving data from the network, then call the corresponding data reception function tcp_receive(), its main task is to pass segment to the upper application program. However, the function first t checking the received segment whether a data ACK. If it is, recover the storage space which occupied by data of waiting for a response. Then place the segment into the receiving queue, passed to the application program. If a data ACK is received at that time, in order to receive more data we need to send confirm ACK and call the function tcp_output() [4]. D. LWIP Protocol LWIP protocol is a set of open source TCP/IP protocol stack for embedded systems. LWIP can be transferred to the operating system, also can be stand alone without operating system. LWIP TCP/IP to achieve the focus is on keeping the main function of TCP protocol based on the reduction of RAM occupation. Generally it requires tens of K of RAM and 40K ROM can run around, which makes LWIP protocol stack suitable for use in low-end embedded systems. In this design, all TCP/IP protocol stacks are in a process, so TCP/IP protocol stack and operating system kernel are

separated. The application layer program can be either a separate process and also reside in TCP/IP process. If the application is a separate process, we can communicate with TCP/IP process through the operating system mailboxes, message queues, etc. If the application layer program resides in the TCP/IP process, that the application layer program use the internal callback function interface (Raw API) and TCP/IP protocol stack to communicate. Process is a system task. LWIP achieve TCP/IP protocol stack the most basic function, to send, receive, forward packets, support IP fragmentation and can handle some IP options. LWIP protocol initialization process is as follows: first call the initialize stack, and through the HAL system code calls the initialization function, and then calls initialize the device driver, then call get_mac_addr() to set up MAC address, the last call get_ip_addr() to establish IP address [5]. IV. THE COMMISSIONING RESULTS The design of PC-IP address is 210.33.190.178, the IP address of FPGA platform is 210.33.190.117, connecting them into the network. Then we download custom NIOS core to the FPGA by Quartus II software, and download the program running on the NIOS core to the FLASH by NIOS II IDE platform. Network is connected, the network indicator light are on. RX, TX indicator light are not on, link indicator light is on. We run Debug as NIOS II Hardware in NIOS II IDE platform. At the command prompt (CMD) user interface, we can view the connectivity situation of PC and FPGA platform. Enter the ping 210.33.190.117-t in the CMD interface, then show connectivity situation in the CMD. The results shown in Figure 4.

Figure 4.

Ping command results diagram.

At this time, once every ping, the RX and TX indicator lights are on for a minute. LED scroll from 0000 to 9999. Display settings network IP address on the LCD 1602. Use telnet command: telnet 210.33.190.117 30 into the telnet control interface, and then type 0 to 3 respectively, can in turn control the four bright LED lights off. By typing S, can control whether the LED scroll; type U, we can see the content to be displayed in the NIOS IDE's Console: www.tzc.edu.cn. Type

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Q, exit telnet interface. The results shown in Figure 5.

With the development of science and technology for the remote control system stability and reliability requirements continue to increase, continue to simplify its program requires constant, practical, and intelligent, people for the telecommunications system of the network will continue to depth.

REFERENCES
[1] Hong-bo Zhang, Zi-shan Dai,SOPC Applied System Research and Design Based on NIOS Processor, Electron Mass, vol.1, 2003, pp. 8486. Da Liu,Jian-rong Gong, System-programmable Chip(SOPC) Design and Development Strategies, Modern Electronic Technology, Nov,2002, pp.76-77. Zhi-xue Wang,Hai-rong Wang,Jun-hua Song,The Application of RTL8019AS Network Card Chip in Ethernet Communication, Modern Instruments, vol.4, 2009, pp. 15-17. Han-lun Lun,Internet Access for Embedded Systems, Industrial Control and Computer, vol.3,2005, pp. 117-164. Wei Hu,Research and Application of Embedded Network Based on SOPC Technology, System Platform and Network Communication,vol.6,2007, pp. 40-75.

[2]

[3] Figure 5.

Debug interface of remote control.

[4]

V.

CONCLUSION

Design of Internet access based on FPGA is becoming a trend, the future of various home appliances, personal consumer goods will be connected to the Ethernet. People can remotely monitor real-time homes, factories, shops and other environments, network remote control will be more extensive.

[5]

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