2009 IEEE Computer Society Annual Symposium on VLSI

Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate

Himanshu Thapliyal and Nagarajan Ranganathan Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA E-mail : {hthapliy,ranganat}@cse.usf.edu Abstract
Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates. applications of reversible logic is in quantum computers [3, 4]. A quantum computer consists of quantum logic gates. The quantum logic gates perform elementary unitary operation on one, two or more two state quantum systems called qubits. In quantum computing qubit represents the elementary unit of information corresponding to the classical bit values 0 and 1. Any unitary operation is reversible in nature and hence quantum computers must be built from reversible logical components [4]. Arithmetic units such as adders, subtractors, multipliers form the essential component of a computing system. Dedicated subtractor units are required in a number of digital signal processing (DSP) applications [19, 21]. Several works can be found in the literature on the design of reversible adders and reversible BCD arithmetic units [13, 14, 15, 23]. However, there is not much existing work on reversible binary subtractors except the designs described in [16]. In [16], several designs for binary subtractors are investigated based on the Fredkin and Feynman gates [9, 10]. These gates are popularly use in reversible logic design. In this work, we propose a novel reversible gate called TR gate as an alternative to the Fredkin and Feynman gates, specifically to be used in the design of binary subtractors. It is shown that the reversible subtractor designs based on TR gate are efficient in terms of number of reversible gates, garbage outputs and quantum cost. Garbage outputs are the unutilized outputs in reversible circuits which exist just to maintain reversibility but do not perform any useful operations. Minimization of the number of reversible gates, quantum cost and garbage outputs is the focus of research in reversible logic synthesis [ 6, 7, 18, 20, 25]. The reversible subtractors proposed in this work will be useful in a number of DSP applications where dedicated subtractor units are required. The paper is organized as follows. Section 2 deals with the introduction of basic reversible gates.
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1. Introduction
Reversible logic is emerging as a promising computing paradigm with applications in emerging technologies such as quantum computing, quantum dot cellular automata, optical computing, etc. [3, 4, 5, 12, 22, 26]. Reversible circuits are those circuits that do not lose information and reversible computation in a system can be performed only when the system comprises of reversible gates. These circuits can generate unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping between the input and output vectors. Landauer has shown in [1] that for irreversible logic computations, each bit of information lost, generates kTln2 joules of heat energy, where k is Boltzmanns constant and T the absolute temperature at which computation is performed. Bennett showed that kTln2 energy dissipation would not occur, if a computation is carried out in a reversible way [2], since the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation. This makes reversible logic in demand for low power VLSI circuits working even beyond the thermodynamic limits of computation [8, 17]. One of the emerging

978-0-7695-3684-2/09 $25.00 2009 IEEE DOI 10.1109/ISVLSI.2009.49

Section 3 deals with the proposed TR reversible gate. Section 4 deals with designs of reversible subtractor units using TR gate. Section 5 provides the conclusions of this work.

2.3 Toffoli Gate

Toffoli Gate (TG) is a 3*3 two-through reversible gate as shown in Fig. 3 [10]. Two-through means two of its outputs are same as the inputs with the mapping (A, B, C) to (P=A, Q=B, R=A.B C), where A, B, C are the inputs and P, Q, R are the outputs, respectively. Toffoli gate is one of the most popular reversible gates and has quantum cost of 5 as shown in Fig.4 [20]. Its quantum cost is 5 as it requires 2V gates, 1 V+ gate and 2 CNOT gates.

2. Basic Reversible Gates

There are a number of existing 3x3 reversible gates such as Fredkin gate, Toffoli gate and Peres gate. Each reversible gate has a cost associated with it called quantum cost [20, 24]. The quantum cost of a reversible gate is the number of 2x2 reversible gates or quantum logic gates required in designing it. The quantum cost of all reversible 2x2 gates is taken as unity. The cost of all the 1x1 reversible gates such as NOT gate is assumed to be zero [20]. Thus any reversible gate is realized by using 1x1 NOT gates and 2x2 reversible gates, such as V and V+ (V is a squareroot-of NOT gate and V+ is its hermitian) and Feynman gate which is also known as Controlled NOT gate (CNOT). The V and V+ quantum gates have the following properties: V x V= NOT V x V+ = V+ x V =I V+ x V+ = NOT The more details of the V and V+ can be found in [20]. In simple terms, the quantum cost of a reversible gate can be calculated by counting the number of V, V+ and CNOT gate used in implementing it except in few cases [20].

Figure 3. Toffoli gate

Figure 4. Quantum implementation of Toffoli gate with quantum cost= 5 [20]

2.1 NOT gate

NOT gate is a 1x1 gate represented as shown in Fig. 1. Since it is a 1x1 gate, its quantum cost is zero.

2.4 Peres Gate

Peres gate is a 3 inputs 3 outputs (3*3) reversible gate having the mapping (A, B, C) to (P=A, Q=A B, R= (A.B) C), where A, B, C are the inputs and P, Q, R are the outputs, respectively [11]. Figure 5 shows the Peres gate and Fig. 6 shows the quantum implementation of the Peres gate (PG) with the quantum cost of 4 [20]. Its quantum cost is 4 since it requires 2 V+ gate, 1 V gate and 1 CNOT gate in implementing it. In the existing literature, among the 3*3 reversible gate, Peres gate has the minimum quantum cost.

Figure 1. NOT gate

2.2 Feynman Gate (CNOT gate )

Feynman gate (FG) is a 2 inputs 2 outputs reversible gate having the mapping (A, B) to (P=A, Q=A B) where A, B are the inputs and P, Q are the outputs, respectively [10]. Since it is a 2x2 gate, it has a quantum cost of 1 [20].

Figure 5. Peres gate Figure 2. Feynman or CNOT gate

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B passed in complemented form by using a NOT gate. Since NAND is a universal gate, it demonstrates the universal nature of the proposed TR gate. It is quite complex to determine the quantum cost of a reversible gate. Thus, we have estimated the quantum cost of TR gate from the quantum implementation of Toffoli gate, i.e., by realizing the TR gate from 1 Toffoli gate, 2 NOT gates and 1 CNOT gate as shown in Figure 11. Thus, the proposed quantum cost of TR gate will be quantum cost of 1 CNOT gate+ quantum cost of 1 Toffoli gate =6 (quantum cost of NOT gates are zero). We want to emphasize that this is not an efficient method of determining the quantum cost of TR gate. For example, Peres gate can be derived from Toffoli gate, by cascading a CNOT gate at the outputs P and Q of Toffoli gate as shown in Fig. 12. In this manner, the quantum cost of Peres gate should be quantum cost of 1 Toffoli gate + quantum cost of 1 CNOT gate= 6. But in optimal quantum realization as shown previously in Fig.6, the quantum cost of Peres gate is 4 which is 1 less than the cost of the Toffoli gate. Thus, it can be expected that the optimal quantum cost of TR gate will be lower than or equal to the proposed implementation but in any case will not be higher than 6. In this work, the main purpose of estimating the quantum cost of TR gate is to have the comparison of the subtractors designs based on it, with the existing reversible binary subtractor designs in literature.

Figure 6. Quantum implementation of Peres gate with quantum cost= 4 [20]

2.5 Fredkin gate

Fredkin gate is a (3*3) conservative reversible gate, having the mapping (A, B, C) to (P=A, Q=AB+AC, R=AB+AC), where A, B, C are the inputs and P, Q, R are the outputs, respectively [9]. It is called a 3*3 gate because it has three inputs and three outputs. Figure 7 shows the Fredkin gate and Figure 8 shows its quantum implementation with quantum cost of 5 [20]. Please note that each dotted rectangles in Fig. 8 is equivalent to a 2*2 Feynman gate and so the quantum cost of each dotted rectangle is 1 [20]. Hence Fredkin gate cost consists of 2 dotted rectangles, 1 V gate and 2 CNOT gate making its quantum cost as 5.

Figure 7. Fredkin gate

Figure 8. Quantum implementation of Fredkin gate with quantum cost=5 [20]

Figure 9. Proposed Reversible TR gate

3. Proposed Reversible TR Gate

The proposed reversible TR gate is a 3 inputs 3 outputs gate having inputs to outputs mapping as (P=A, Q=A B, R=(A.B) C), where A, B, C are the inputs and P, Q, R are the outputs, respectively. Figure 9 shows the proposed TR gate and Table 1 shows its truth table. The proposed TR gate can be used to realize the NAND gate as shown in Fig. 10 with input

Table 1. Truth Table of TR gate

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 P 0 0 0 0 1 1 1 1 Q 0 0 1 1 1 1 0 0 R 0 1 0 1 1 0 0 1

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Figure 10. TR gate working as a NAND gate

have done our comparison with the designs in [16] as to the best of our knowledge; it is the only work in literature describing the designing of reversible binary subtractors. Thus proposed design achieves 50% reduction in number of reversible gates and 66% reduction in number of garbage outputs with quantum cost, as same as, of the design in [16]. Table 2. Truth Table of Half Subtractor
A 0 0 1 1 B 0 1 0 1 Borr 0 1 0 0 Diff 0 1 1 0

Figure 11. Proposed Quantum Cost estimation of TR gate by using 1 Toffoli gate, 2 NOT gate and 1 CNOT gate

Figure 12. Realization of Peres gate from 1 Toffoli gate + 1 CNOT gate

Figure 13. Proposed TR gate Based Design of Reversible Half Subtractor Table 3. A Comparison of Reversible Half Subtractors
# of Gates # of Garbage Outputs 2 3 1 50% 1 66% Quantum cost 6 6 Same cost

4. Design of Reversible Subtractors using TR gate

We used TR gate to design the binary subtractors such as half subtractor, full subtractor and parallel subtractor. The cost of the designs is also estimated in terms of number of reversible gates, garbage outputs and quantum cost.

Existing Circuit [16] Proposed Design Improvement

4.1 Half Subtractor

Let A and B are two binary numbers. The half subtractor performs A-B operation. Table 2 shows the truth table of the half subtractor. The output of XOR gate produces the difference between A and B. The output of AND gate (A'B) produces a Borrow. Thus, the output function will be Burr=AB; Diff=A B. We can see that proposed TR gate can singly work as a reversible half subtractor as shown in Fig. 13. Thus, TR gate implements the reversible half subtractor with 1 reversible gate, 1 garbage output and quantum cost of 6. The existing design in literature [16] is implemented with 2 reversible gates, 3 garbage outputs and quantum cost of 6. A comparison of the reversible half subtractors is shown in Table 3. We
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4.2 Full Subtractor

To subtract three binary numbers, one can use full subtractor which realizes the operation Y=A-B-C. The truth table of the full subtractor is shown in Table 4. This gives the equation of the borrow and difference as follows: Diff= A B C; Borr= AB ((A B). C) Before showing the proposed design of the reversible full subtractor, we want to show its lower bound in terms of number of garbage outputs. Theorem 4.1. A reversible full-subtractor circuit can be realized with at least two garbage outputs. Proof. From truth table, we can see that for the three inputs combinations(0,0,0),(1,0,1) and (1,1,0), the output is same (Borrow=0, Difference=0). Addition of 1 garbage output can resolve only two output positions

since 1 bit can produce only two distinct output combinations. Since (22=4) >3, thus it will require at least 2 garbage outputs to have 3 different output combinations for the inputs (0,0,0),(1,0,1) and (1,1,0). Table 4. Truth Table of Full Subtractor
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Borr 0 1 1 1 0 0 0 1 Diff 0 1 1 0 1 0 0 1

4.3 Parallel Subtractor

The parallel subtractor subtracts an n bit number Y from an n bit number X. Thus, it can be designed from 1 reversible half subtractor (RHS) and n-1 reversible full subtractors (RFS). Figure 15 shows the proposed reversible design of 4 bit parallel subtractor subtracting 4 bit number Y from 4 bit number X (here RHS and RFS refers to reversible half subtractor and reversible full subtractor, respectively, designed from TR gate, g1 to g7 represents the garbage outputs). In the design B1 to B4 represent the borrow and D0 to D3 represent the difference. Thus using the proposed approach of designing n bit parallel subtractor using the TR reversible gate requires 2n-1 reversible gates, 2n-1 garbage outputs and quantum cost of 12n-6. The existing design in literature requires 5n-3 reversible gates, 9n-6 garbage outputs with quantum cost of 17n11. A comparison between the proposed approach and existing approach in literature is shown in Table 6 for 4 bit parallel subtractor. Thus the proposed approach achieves the improvement ratio of 64.7%, 77% and 20% in terms of number of reversible gates, garbage outputs and quantum cost, respectively, compared to existing design in [16].

The proposed design of the reversible full subtractor is shown in Fig.14. It requires two TR gates to design a reversible full subtractor with only two garbage outputs and quantum cost of 12. Thus the proposed TR gate realizes the full subtractor with bare minimum of two garbage outputs. The existing design in literature [16] requires 5 reversible gates, 9 garbage outputs and quantum cost of 17. A comparison of reversible full subtractors is shown in Table 5. From Table 5, we can see that proposed design based on TR gate has an improvement ratio of 60% in terms of number of reversible gates, 77% in terms of garbage outputs and 30% in terms of quantum cost compared to existing design in literature.

Figure 15. Proposed TR gate Based Design of Reversible Parallel Subtractor Table 6. A Comparison of Reversible Parallel Subtractor Figure 14. Proposed TR gate Based Design of Reversible Full Subtractor
# of Gates 17 7 64.7% # of Garbage Outputs 30 7 77% Quantum cost 55 42 20%

Existing Circuit [16] Proposed Design Improvement Ratio

Table 5. A Comparison of Reversible Full Subtractors

# of Gates Existing Circuit [16] Proposed Design Improvement Ratio 5 2 60% # of Garbage Outputs 9 2 77% Quantum cost 17 12 30%

5. Conclusions
We have designed efficient reversible subtractors using a novel reversible TR gate. The quantum cost of the TR gate is also estimated. The proposed reversible subtractor designs are shown better than the existing
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one in literature in terms of number of reversible gates, garbage outputs and quantum cost. The proposed work shows that in reversible logic, the design of a specific reversible gate for a particular function can be very much beneficial. This can help in achieving the reductions in number of reversible gates, garbage outputs and quantum cost, and can be considered an important contribution of this work to the reversible logic community along with the design of efficient binary subtractors.

[15]

[16]

6. References
[1] R. Landauer, Irreversibility and Heat Generation in the Computational Process, IBM J. Research and Development, 5, pp. 183-191, 1961. [2] C.H. Bennett, Logical Reversibility of Computation, IBM J. Research and Development, pp. 525-532, November 1973. [3] A.N. Al-Rabadi, Reversible Logic Synthesis: From Fundamentals to Quantum Computing, SpringerVerlag, New York, First Edition, 2004 [4] V. Vedral, A. Bareno and A. Ekert, Quantum Networks for Elementary Arithmetic Operations. arXiv:quant-ph/9511018 v1. (nov 1995) [5] H. Thapliyal and N. Ranganathan, "Reversible Logic Based Concurrently Testable Latches for Molecular QCA", To appear IEEE Trans. on Nanotechnology, 2009. [6] D. Maslov, "Reversible Logic Synthesis", Phd. Thesis, University of New Brunswick, Canada, Oct 2003. [7] K. Patel, I. Markov, and J. Hayes, ``Optimal Synthesis of Linear Reversible Circuits,'' Quantum Information and Computation, vol. 8, no. 3-4, pp. 282-294, 2008. [8] A. D. Vos and Y. Van Rentergem, Power consumption in reversible logic addressed by a ramp voltage, Proc. of the 15th Intl. Workshop Patmos 2005, Lecture Notes of Computer Science, vol. 3728, pp. 207-216, SpringerVerlag, Oct 2005. [9] E. Fredkin, T Toffoli, Conservative Logic, Int. J. Theor. Phys, vol. 21, no. 34, pp. 219253, 1982 [10] T. Toffoli, Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980). [11] A. Peres, Reversible logic and quantum computers, Phys. Rev. A, Gen. Phys., vol. 32, no. 6, pp. 3266 3276, Dec. 1985. [12] H. Thapliyal and N. Ranganathan, "Testable Reversible Latches for Molecular QCA", Proc. of the 8th Intl. Conf. on Nanotechnology, Arlington, TX, Aug 2008, pp. 699-702. [13] J. Mathew, H. Rahaman, B.R. Jose, D.K. Pradhan, "Design of Reversible Finite Field Arithmetic Circuits with Error Detection", Proc. of the 21st Intl. Conf. on VLSI Design, Hyderabad, India, Jan 2008, pp.453-459. [14] J.W. Bruce, M.A. Thornton, L. Shivakumariah, P.S. Kokate and X.Li, "Efficient Adder Circuits Based on a Conservative Logic Gate", Proc. of the IEEE Computer
234

[17] [18] [19] [20]

[21]

[22]

[23] [24]

[25]

[26]

Society Annual Symposium on VLSI, April 2002, Pittsburgh, PA, USA, pp 83-88. H. M. H. Babu, M. R. Islam, S.M. Ali Chowdhury and A. R.Chowdhury, "Synthesis of Full-Adder Circuit Using Reversible Logic", Proc. of the 17th International Conference on VLSI Design (VLSI Design 2004), January 2004, Mumbai, India,pp-757-760. H. Thapliyal, M.B Srinivas and H.R Arabnia, Reversible Logic Synthesis of Half, Full and Parallel Subtractors, Proc. of the 2005 Intl. Conf. on Embedded Systems and Applications, June 2005, Las Vegas, pp.165-181. M.P Frank, Introduction to reversible computing: motivation, progress, and challenges, Proc. of the 2nd Conf. on Computing Frontiers, 2005, pp 385390. D. Maslov and G. W. Dueck, Reversible Cascades with Minimal Garbage, IEEE Trans. on CAD, vol. 23(11), pp. 1497-1509, Nov. 2004 Digital Signal Processing (DSP) Blocks in Stratix Devices, available online at www.altera.com W.N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, "Optimal Synthesis of Multiple Output Boolean Functions Using a Set of Quantum Gates by Symbolic Reachability Analysis", IEEE Trans. Computer-Aided Design, Vol. 25, No. 9,pp.1652-1663, Sep 2006. C. Chavet, C. Andriamisaina, P. Coussy, E. Casseau, E. Juin, P. Urard, E. Martin, "A design flow dedicated to multi-mode architectures for DSP applications", Proc. of the IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD07), San Jose, CA, Nov. 2007,pp.604611 H. Thapliyal and N. Ranganathan, "Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits", Proc. of the 22nd Intl. Conf. on VLSI Design, New Delhi, India, Jan 2009, pp. 511516 M.K. Thomsen and R. Glck, "Optimized reversible binary-coded decimal adders", Vol.54, no.7, pp.697706, Jul 2008. J. A. Smolin, D. P. DiVincenzo, Five Two-Bit Quantum Gates are Sufficient to Implement the Quantum Fredkin Gate, Physical Review A, 53, 1996, pp.2855-2856. P. Gupta, A. Agarwal, and N. K. Jha, An Algorithm for Synthesis of Reversible Logic Ciruits, IEEE Trans. Computer-Aided Design, vol. 25, no. 11, pp. 23172330, Nov. 2006 X. Ma, J. Huang, C. Metra, F.Lombardi, Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA, Springer Journal of Electronic Testing, Vol. 24, No. 1-3, pp.297-311, Jan 2008.