VHDL Complete File

EXPERIMENT NO.
1(a)
AIM
To verify AND gate using VHDL.
TOOLS AND VERSION USED

Xilinux version 8.1
CIRCUIT DIAGRAM AND TRUTH TABLE
VHDL CODE
--Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: b = Behavioral --Project name: --Target devices: --Tool version: --Description: ---Revision: --Revision 0.01 = File Created --Additional Comments:
-------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity b is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end b; architecture Behavioral of b is begin c <= a and b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 1(b)

AIM
To verify OR gate using VHDL.

Xilinx version 8.1
VHDL CODE
--Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: p = Behavioral --Project name: --Target devices: --Tool version: --Description: ---Revision: --Revision 0.01 = File Created --Additional Comments:
-------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity p is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end p; architecture Behavioral of p is begin c <= a or b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 1(c)

AIM
To verify NOT gate using VHDL.

Xilinx version 8.1
VHDL CODE
------------------------------------------------------------------------------Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: y = Behavioral --Project name: --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity y is Port( a : in STD_LOGIC; b : out STD_LOGIC); end y; architecture Behavioral of y is begin c <= a not b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 1(d)

AIM
To verify NAND gate using VHDL.

Xilinx version 8.1
A 0 0 1 1
VHDL CODE
--Company --Engineer
B 0 1 0 1
C 1 1 1 0
---Create date: 08:32:42 08/04/2011 --Design name: --Module name: h = Behavioral --Project name: --Target devices: --Tool version: --Description: ---Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity h is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end h; architecture Behavioral of h is begin c <= a nand b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 1(e)
AIM
To verify XOR gate using VHDL.

Xilinux version 8.1
VHDL CODE
--Company
--Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: d = Behavioral --Project name: --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity d is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end d; architecture Behavioral of d is begin c <= a xor b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 1(f)
AIM
To verify NOR gate using VHDL.

Xilinx version 8.1
VHDL CODE
--Company
--Engineer ---Create date: 08:32:42 08/04/2011 --Design name: --Module name: d = Behavioral --Project name: --Target devices: --Tool version: --Description: ---Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity d is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end d; architecture Behavioral of d is begin c <= a xor b; end Behavioral;
SYSTHESIS RESULT
SIMULATION
EXPERIMENT NO. 2(a)
AIM
To verify Half Adder using VHDL.

Xilinx version 8.1
VHDL CODE
--Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: dd = Behavioral --Project name: --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity dd is Port( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC ); end dd; architecture Behavioral of dd is begin s <= a xor b; c <= a and b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 2(b)
AIM
To verify Full Adder using VHDL

Xilinux version 8.1
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
Z 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
C 0 0 0 1 0 1 1 1
VHDL CODE
-----------------------------------------------------------------------------
--Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: yy = Behavioral --Project name: --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity yy is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : in STD_LOGIC; ca : out STD_LOGIC); end yy; architecture Behavioral of yy is begin s <= a xor b xor c; ca <= (a and b) or ( c and ( a xor b)); end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 3(a)
AIM
To verify the Half Adder circuit using Structural Modelling.

Xilinx Version : 8.1
A 0 0 1 1
B 0 1 0 1
S 0 1 1 0
C 0 0 0 1
VHDL CODE
--Company --Engineer --Create date:
08:32:42 08/04/2011
--Design name: --Module name: d = Behavioral --Project name: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all entity ha is port (A,B: in bit; Sum,Carry:out bit); end ha;
architecture halfadd structure of halfadd is component AND2 port(IN1,IN2:in bit; out2: out bit); end component;
component XOR2 port(IN3,IN4: in bit; OUT2: out bit); end component; begin
A1:AND2 port map(A,B,Sum); X1:XOR2 port map(A,B,Carry); end Halfadd;
SYNTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 3(b)

AIM
To verify the Full Adder circuit using Structural Modelling.

Xilinx Version : 8.1
X 0 0 0 0 1
Y 0 0 1 1 0
Z 0 1 0 1 0
S 0 1 1 0 1
C 0 0 0 1 0
1 1 1
0 1 1
1 0 1
0 0 1
1 1 1
VHDL CODE
Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --use UNISIN.VCcomponents.all entity fa is port (A,B,CIN: in bit; S,C:out bit); end fa; architecture fulladd structure of halfadd is component XOR3 port(IN1,IN2,IN3:in bit; out1: out bit); end component;
component AND2 port(IN4,IN5: in bit; out2: out bit); end component;
component OR3
port(IN6,IN7,IN8: in bit; out3; out bit); end component;
signal x,y,z:bit; begin X0:XOR3 port map(A,B,CIN,S); A0:AND2 port map(A,B,X); A1:AND2 port map(B,CIN,Y); A2:AND2 port map(A,CIN,Z); O0;OR3 port map(X,Y,Z,C); end fulladd;
SYNTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 4(a)

AIM
To verify Half Subtractor using VHDL.

Xilinx version 8.1
a
0 0 1 1
b
0 1 0 1
diff
0 1 1 0
c
0 1 0 0
VHDL CODE
--Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: dd = Behavioral --Project name: --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating
----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity hs is Port( a : in STD_LOGIC; b : in STD_LOGIC; dif : out STD_LOGIC; c : out STD_LOGIC ); end hs; architecture Behavioral of hs is begin dif <= a xor b; c <= ( not a) and b; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 4(b)

AIM
To verify Full Subtractor using VHDL

Xilinux version 8.1
a
0 0 0 0 1 1 1 1
b
0 0 1 1 0 0 1 1
c
0 1 0 1 0 1 0 1
ca
0 1 1 0 1 0 0 1
diff
0 1 1 1 0 0 0 1
VHDL CODE
------------------------------------------------------------------------------Company --Engineer --Create date: 08:32:42 08/04/2011 --Design name: --Module name: yy = Behavioral --Project name: --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created
--Additional Comments:
------------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; Entity fusu is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; diff : in STD_LOGIC; ca : out STD_LOGIC); end fusu; architecture Behavioral of fusu is begin s <= a xor b xor c; ca <= ((not a ) and (b xor c)) or (b and c); end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 5
AIM
Design 4* 1 MUX using if else statement.

Xilinx version 8.1
S1 0 0 1 1
S2 0 1 0 1
Y i1 i2 i3 i4
VHDL CODE
Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; library ieee; use ieee.std_logic_1164.all; entity mux is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0);
o : out std_logic); end mux; architecture archi of mux is begin process (a, b, c, d, s) begin if (s = "00") then o <= a; elsif (s = "01") then o <= b; elsif (s = "10") then o <= c; else o <= d; end if; end process; end archi;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 6
AIM
To design a 8*3 Encoder using VHDL.

Xilinx version 8.1
VHDL CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Encoder is Port ( a : in STD_LOGIC_VECTOR(7 downto 0);
q : out STD_LOGIC_VECTOR(2 downto 0)); end Encoder; architecture Beh of Encoder is begin q <= "000" when a="10000000" else "001" when a="01000000" else "010" when a="00100000" else "011" when a="00010000" else "100" when a="00001000" else "101" when a="00000100" else "110" when a="00000010" else "111"; end Beh;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 7
AIM
To design a 3*8 Decoder using VHDL.

Xilinx version 8.1
i1
0 0 0 0 1 1 1 1
i2
0 0 1 1 0 0 1 1
i3
0 1 0 1 0 1 0 1
a
1 0 0 0 0 0 0 0
b
0 1 0 0 0 0 0 0
c
0 0 1 0 0 0 0 0
d
0 0 0 1 0 0 0 0
e
0 0 0 0 1 0 0 0
f
0 0 0 0 0 1 0 0
g
0 0 0 0 0 0 1 0
h
0 0 0 0 0 0 0 1
VHDL CODE
Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all;
entity decoder1 is Port ( i1 : in STD_LOGIC; i2 : in STD_LOGIC; i3 : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC; h : out STD_LOGIC); end decoder1; architecture Behavioral of decoder1 is begin a <= (not i1) and (not i2) and (not i3); b <= (not i1) and (not i2) and i3; c <= (not i1) and i2 and (not i3); d <= (not i1) and i2 and i3; e <= i1 and (not i2) and (not i3); f <= i1 and (not i2) and i3; g <= i1 and i2 and (not i3); h <= i1 and i2 and i3; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 8
AIM
To design a J-K Flip Flop using VHDL Modelling.

Xilinx version 8.1
VHDL CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity jkff is Port ( j : in STD_LOGIC; k : in STD_LOGIC; s : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end jkff; architecture Behavioral of jkff is begin process (j,k,s,clk) begin if(clk ='1') then q <= ((not k) and s) or (j and (not s)); else q <='0'; end if; end process; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 9
AIM
To design a S-R Flip Flop using VHDL Modelling.

Xilinx version 8.1
VHDL CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity srff is Port ( s : in STD_LOGIC; r : in STD_LOGIC; d : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end srff; architecture Behavioral of srff is begin process (s,r,d,clk) begin if(clk ='1') then q <= (nor r) and (d or s); end if; end process; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 10
AIM
To design a D Flip Flop using VHDL Modelling.

Xilinx version 8.1
VHDL CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC); end dff; architecture Behavioral of dff is begin process (d,clk) begin if(clk ='1') then q <= d; end process; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 11
AIM
To design a T Flip Flop using VHDL Modelling.

Xilinx version 8.1
VHDL CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tff is Port ( t : in STD_LOGIC; s : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC); end tff; architecture Behavioral of tff is begin process (t,s,clk) begin if(clk ='1') then q <= t xor s; end if; end process; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 12
AIM
Design a Comparator using VHDL Modelling.

Xilinx version 8.1
a
0 0 1 1
b
0 1 0 1
a>b
0 0 1 0
a<b
0 1 0 0
a=b
1 0 0 1
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --use UNISIM.VComponents.all; entity comp is Port ( a : in STD_LOGIC_VECTOR(0 to 1); b : in STD_LOGIC_VECTOR(0 to 1); aeb : out STD_LOGIC; alb : out STD_LOGIC; agb : out STD_LOGIC); end comp; architecture Behavioral of comp is begin process(a,b) begin if(a>b) then agb<='1'; aeb<='0'; alb<='0'; elsif (a=b) then agb<='0'; aeb<='1'; alb<='0'; elsif (a<b) then agb<='0'; aeb<='0'; alb<='1'; end if; end process; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 13
AIM
Design gray to binary code converter

Xilinx version 8.1
g0 0
g1 0
g2 0
g3 0
b0 0
b1 0
b2 0
b3 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VHDL CODE
--Company --Engineer
--Create date: 08:32:42 08/04/2011 --Target devices: --Tool version: --Description: --Revision: --Revision 0.01 = File Created --Additional Comments:
------------------------------------------------------------------Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; entity converter1 is xxx Port ( g0 : in STD_LOGIC; g1 : in STD_LOGIC; g2 : in STD_LOGIC; g3 : in STD_LOGIC; b0 : inout STD_LOGIC; b1 : inout STD_LOGIC; b2 : inout STD_LOGIC; b3 : out STD_LOGIC); end converter1; architecture Behavioral of converter1 is begin b3 <= g3; b2 <= g3 xor g2; b1 <= b2 xor g1; b0 <= b1 xor g0; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 14
AIM
Design a binary to grey code converter.

Xilinx version 8.1
b0 0
b1 0
b2 0
b3 0
g0 0
g1 0
g2 0
g3 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
VHDL CODE
Library IEEE;
Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; ---- uncomment the following library declaration if instantiating ----any Xilinx primitive in this code --library UNISIN; --use UNISIN.VCcomponents.all; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity converter is Port ( b0 : in STD_LOGIC; b1 : in STD_LOGIC; b2 : in STD_LOGIC; b3 : in STD_LOGIC; g0 : out STD_LOGIC; g1 : out STD_LOGIC; g2 : out STD_LOGIC; g3 : out STD_LOGIC); end converter; architecture Behavioral of converter is begin g3 <= b3; g2 <= b3 xor b2; g1 <= b2 xor b1; g0 <= b1 xor b0; end Behavioral;
SYSTHESIS RESULT
SIMULATION RESULT
EXPERIMENT NO. 15(a)
AIM
To verify AND gate using CPLD

Xilinux version 8.1
VHDL CODE
Library IEEE; Entity b is
Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end b; architecture Behavioral of b is begin c <= a and b; end Behavioral;
HARDWARE IMPLEMENTED
EXPERIMENT NO. 15 (b)
AIM
To verify OR gate using CPLD.

Xilinx version 8.1
VHDL CODE
Library IEEE; Entity p is
Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end p; architecture Behavioral of p is begin c <= a or b; end Behavioral;
EXPERIMENT NO. 15 (c)

AIM
To verify NOT gate using CPLD

Xilinx version 8.1
VHDL CODE
Library IEEE; Entity y is Port( a : in STD_LOGIC; b : out STD_LOGIC); end y; architecture Behavioral of y is begin c <= a not b; end Behavioral;
EXPERIMENT NO. 15 (d)

AIM
To verify NAND gate using CPLD

Xilinx version 8.1
A 0 0 1 1
B 0 1 0 1
C 1 1 1 0
VHDL CODE
Library IEEE; Entity h is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end h;
architecture Behavioral of h is begin c <= a nand b; end Behavioral;
EXPERIMENT NO. 15 (e)

AIM
To verify XOR gate using CPLD.
Xilinux version 8.1
VHDL CODE
Library IEEE; Entity d is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end d; architecture Behavioral of d is begin c <= a xor b; end Behavioral;
EXPERIMENT NO. 15 (f)

AIM
To verify NOR gate using CPLD.

Xilinx version 8.1
VHDL CODE

AIM
To verify AND gate using FPGA.

Xilinx version 8.1
VHDL CODE
Library IEEE; Entity b is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end b; architecture Behavioral of b is begin c <= a and b; end Behavioral;

AIM
To verify OR gate using FPGA.
Xilinx version 8.1
VHDL CODE
Library IEEE; Entity p is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end p; architecture Behavioral of p is begin c <= a or b; end Behavioral;
EXPERIMENT NO. 16 (c)

AIM
To verify NOT gate using FPGA.

Xilinx version 8.1
VHDL CODE
Library IEEE; Entity y is Port( a : in STD_LOGIC; b : out STD_LOGIC); end y; architecture Behavioral of y is begin c <= a not b; end Behavioral;
EXPERIMENT NO. 16 (d)

AIM
To verify NAND gate using FPGA.

Xilinx version 8.1
A 0 0 1 1
B 0 1 0 1
C 1 1 1 0
VHDL CODE
Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; Entity h is Port( a : in STD_LOGIC;
b : in STD_LOGIC; c : out STD_LOGIC); end h; architecture Behavioral of h is begin c <= a nand b; end Behavioral;
EXPERIMENT NO. 16 (e)

AIM
To verify XOR gate using FPGA.

Xilinx version 8.1
VHDL CODE
EXPERIMENT NO. 1(f)

AIM
To verify NOR gate using FPGA.

Xilinx version 8.1
VHDL CODE

AIM
To verify Half Adder using CPLD.

Xilinx version 8.1
VHDL CODE
Entity dd is Port( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC ); end dd; architecture Behavioral of dd is begin s <= a xor b; c <= a and b; end Behavioral;

AIM
To verify Full Adder using CPLD.

Xilinux version 8.1
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
Z 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
C 0 0 0 1 0 1 1 1
VHDL CODE
Library IEEE; Use IEEE_STD_LOGIC_::64.ALL; Use IEEE_STD_LOGIC_ARITH.ALL; Use IEEE_STD_LOGIC_UNSIGNED.ALL; Entity yy is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : in STD_LOGIC;
ca : out STD_LOGIC); end yy; architecture Behavioral of yy is begin s <= a xor b xor c; ca <= (a and b) or ( c and ( a xor b)); end Behavioral;
EXPERIMENT NO. 18 (a)

AIM
To verify Half Subtractor using CPLD.

Xilinx version 8.1
a
0 0 1 1
b
0 1 0 1
diff
0 1 1 0
c
0 1 0 0
VHDL CODE
Entity hs is Port( a : in STD_LOGIC; b : in STD_LOGIC; dif : out STD_LOGIC; c : out STD_LOGIC ); end hs; architecture Behavioral of hs is begin dif <= a xor b; c <= ( not a) and b; end Behavioral;

AIM
To verify Full Subtractor using CPLD

Xilinux version 8.1
a
0 0 0 0 1 1 1 1
b
0 0 1 1 0 0 1 1
c
0 1 0 1 0 1 0 1
ca
0 1 1 0 1 0 0 1
diff
0 1 1 1 0 0 0 1
VHDL CODE
Library IEEE; Entity fusu is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; diff : in STD_LOGIC; ca : out STD_LOGIC); end fusu; architecture Behavioral of fusu is begin
s <= a xor b xor c; ca <= ((not a ) and (b xor c)) or (b and c); end Behavioral;
EXPERIMENT NO. 19 (a)

AIM
To verify Half Adder using FPGA.

Xilinx version 8.1
VHDL CODE
Entity dd is Port( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC ); end dd; architecture Behavioral of dd is begin s <= a xor b; c <= a and b;
end Behavioral;

AIM
To verify Full Adder using FPGA

Xilinux version 8.1
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
Z 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
C 0 0 0 1 0 1 1 1
VHDL CODE
Entity yy is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : in STD_LOGIC; ca : out STD_LOGIC); end yy; architecture Behavioral of yy is
begin s <= a xor b xor c; ca <= (a and b) or ( c and ( a xor b)); end Behavioral;

AIM
To verify Half Subtractor using FPGA.

Xilinx version 8.1
a
0 0 1 1
b
0 1 0 1
diff
0 1 1 0
c
0 1 0 0
VHDL CODE
Entity hs is Port( a : in STD_LOGIC; b : in STD_LOGIC; dif : out STD_LOGIC; c : out STD_LOGIC ); end hs; architecture Behavioral of hs is begin dif <= a xor b; c <= ( not a) and b;
end Behavioral;

AIM
To verify Full Subtractor using FPGA

Xilinx version 8.1
a
0 0 0 0 1 1 1 1
b
0 0 1 1 0 0 1 1
c
0 1 0 1 0 1 0 1
ca
0 1 1 0 1 0 0 1
diff
0 1 1 1 0 0 0 1
VHDL CODE
Entity fusu is Port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; diff : in STD_LOGIC; ca : out STD_LOGIC); end fusu; architecture Behavioral of fusu is
begin s <= a xor b xor c; ca <= ((not a ) and (b xor c)) or (b and c); end Behavioral;

VHDL Complete File

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EXPERIMENT NO.

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 1(b)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 1(c)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 1(d)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 1(e)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 1(f)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 2(a)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 2(b)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 3(a)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

A1:AND2 port map(A,B,Sum); X1:XOR2 port map(A,B,Carry); end Halfadd;

EXPERIMENT NO. 3(b)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

component AND2 port(IN4,IN5: in bit; out2: out bit); end component;

port(IN6,IN7,IN8: in bit; out3; out bit); end component;

EXPERIMENT NO. 4(a)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 4(b)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

To design a 3*8 Decoder using VHDL.

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE

EXPERIMENT NO. 15(a)

TOOLS AND VERSION USED

CIRCUIT DIAGRAM AND TRUTH TABLE