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5.

Les circuits spcifiques a une application


5.1 Introduction

Il existe une loi empirique, appele loi de Moore, qui dit que la densit dintgration dans les circuits intgrs numriques base de silicium double tous les 18 24 mois. Cette loi sest rvle remarquablement exacte jusqu' ce jour. Durant les annes 60, au dbut de l're des circuits intgrs numriques, les fonctions logiques telles que les portes, les registres, les compteurs et les ALU, taient disponibles en circuit TTL. On parlait de composants SSI (Small Scale Integration) ou MSI (Medium Scale Integration) pour un tel niveau d'intgration.

Dans les annes 70, le nombre de transistors intgrs sur une puce de silicium augmentait rgulirement. Les fabricants mettaient sur le march des composants LSI (Large Scale Integration) de plus en plus spcialiss. Par exemple, le circuit 74LS275 contenait 3 multiplieurs de type Wallace. Ce genre de circuit n'tait pas utilisable dans la majorit des applications. Cette spcialisation des botiers segmentait donc le march des circuits intgrs et il devenait difficile de fabriquer des grandes sries. De plus, les cots de fabrication et de conception augmentaient avec le nombre de transistors. Pour toutes ces raisons, les catalogues de composants logiques standards (srie 74xx) se sont limits au niveau LSI. Pour tirer avantage des nouvelles structures VLSI (Very Large Scale Integration), les fabricants dvelopprent trois nouvelles familles : Les microprocesseurs et les mmoires RAM et ROM : les microprocesseurs et les circuits mmoires sont attrayants pour les fabricants. Composants de base pour les systmes informatiques, ils sont produits en trs grandes sries. Les circuits programmables sur site : n'importe quelle fonction logique, combinatoire ou squentielle, avec un nombre fixe d'entres et de sorties, peut tre implante dans ces circuits. A partir de cette simple ide, plusieurs variantes d'architecture ont t dveloppes (PAL, EPLD, FPGA,). Les ASIC programms chez le fondeur : le circuit est conu d'un point de vue logiciel par l'utilisateur, puis il est ralis par le fondeur.

A l'heure actuelle, la majorit des circuits numriques est issue de ces trois familles. Cependant, le catalogue standard (famille 74xx) est toujours utilis.

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Plus simplement, on peut distinguer deux catgories de circuits intgrs : les circuits standards et les circuits spcifiques une application : Les circuits standards se justifient pour de grandes quantits : microprocesseurs, contrleurs, mmoires, Les circuits spcifiques sont destins raliser une ou un ensemble de fonctions dans un systme bien particulier.

La figure suivante reprsente une classification des circuits intgrs numriques.

CIRCUIT STANDARD
conu et ralis par le fabricant

Circuit spcifique l'application

ASIC

Full-custom

Semi-custom

PLD
Circuit la demande Circuit base de cellules Circuit prdiffus Circuit programmable

Circuit compil

Circuit prcaractris

Rseau mer de portes

Rseau prdiffus classique

FPGA PROM PLA PAL EPLD ou CPLD

Dans la littrature, le terme ASIC (Application Specific Integrated Circuit) est employ pour dcrire lensemble des circuits spcifiques une application. Or, dans le langage courant, le terme ASIC est presque toujours utilis pour dcrire les circuits raliss chez un fondeur. On dsigne, par le terme gnrique PLD (Programmable logic Device), lensemble des circuits programmables par lutilisateur.

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Parmi les circuits numriques spcifiques une application, il faut distinguer deux familles : les circuits conus partir dune puce de silicium "vierge" (Full-custom), les circuits o des cellules standards sont dj implantes sur la puce de silicium (Semicustom).

Dans le premier groupe, les circuits appels "Full custom", on trouve les circuits la demande et ceux base de cellules. Le fondeur ralise l'ensemble des masques de fabrication. Dans le second groupe, les circuits appels "Semi-custom", on trouve les circuits prdiffuss et les circuits programmables. Les cellules standards, dj implantes sur la puce de silicium, doivent tre interconnectes les unes avec les autres. Cette phase de routage est ralise, soit par masquage chez le fondeur (prdiffus), soit par programmation. Avant daborder le dtail de la classification des circuits numriques spcifiques une application, un aperu est donn sur les mthodes de ralisation des interconnexions pour les circuits "Semi-custom". 5.2 Technologie utilise pour les interconnexions

Les cellules standards implantes dans les circuits "Semi-custom" vont de la simple porte jusqu' une structure complexe utilisant un grand nombre de transistors. Il existe deux manires dinterconnecter ces cellules : 1. Dans les ASIC, les lignes dinterconnexions sont cres par masque (fondeur). 2. Dans les PLD, les lignes dinterconnexions existent dj dans le circuit (gnralement sous forme de lignes et de colonnes traversant le composant). Il ne reste donc plus qu raliser les bonnes liaisons pour raliser le chemin voulu afin de relier les cellules logiques. Ces liaisons peuvent se faire : par anti-fusible, par cellule mmoire : fusible, EPROM, EEPROM, flash EPROM et SRAM. 5.2.1 Interconnexion par masque Le fondeur ralise les interconnexions des circuits prdiffuss par mtallisation en crant le ou les derniers masques de fabrication. 5.2.2 Interconnexion par anti-fusible Avec cette technique, c'est l'opration inverse du fusible qui est ralise. On ne coupe pas une liaison, mais on l'tablit. L'anti-fusible isole deux lignes mtalliques places sur deux niveaux diffrents grce une fine couche d'oxyde de silicium. Si on applique une impulsion leve 245

(21V) calibre en temps (moins de 5 ms), la couche d'oxyde est troue et les deux lignes se retrouvent en contact. La rsistance entre les deux lignes passe alors de 100 M 100. Lanti-fusible occupe une faible surface de silicium mais comme pour la technique du fusible, le botier n'est programmable qu'une seule fois par l'utilisateur.

5.2.3 Interconnexion par cellule mmoire La liaison entre les deux lignes peut tre effectue avec les cellules mmoires courantes ( lexception de la cellule DRAM). On trouve donc des PLD bass sur les technologies fusibles, EPROM, E2PROM, flash EEPROM et SRAM. Mais en fait, les trois technologies les plus utilises aujourdhui pour raliser des PAL, des EPLD et des FPGA sont lEEPROM (flash ou non), la SRAM et lanti-fusible. 5.3 Les circuits full custom

Les circuits intgrs appels full-custom ont comme particularit de possder une architecture ddie chaque application et sont donc compltement dfinis par les concepteurs. La fabrication ncessite la dfinition de l'ensemble des masques pour la ralisation. Les temps de fabrication de ces masques et de production des circuits sont de ce fait assez long. Ces circuits sont ainsi appropris pour des sries moyennes ou grandes.

L'avantage du circuit full-custom rside dans la possibilit d'avoir un circuit ayant les fonctionnalits strictement ncessaires la ralisation des objectifs de l'application. Parmi les circuits full-custom, on distingue : les circuits la demande, les circuits base de cellules. 246

5.3.1 Les circuits la demande Ces circuits sont directement conus et fabriqus par les fondeurs. Ils sont spcifiques car ils rpondent l'expression d'un besoin pour une application particulire. Le demandeur utilise le fondeur comme un sous-traitant pour la conception et la ralisation et n'intervient que pour exprimer le besoin. Ces circuits spcifiques utilisent au mieux la puce de silicium. Chaque circuit conu et fabriqu de cette manire doit tre produit en trs grande quantit pour amortir les cots de conception. 5.3.2 Les circuits base de cellules Les circuits base de cellules (CBIC : Cell Based Integrated Circuit) permettent des complexits d'intgration allant jusqu'au million de portes. Dans cette catgorie de circuits, on distingue les circuits base de cellules prcaractrises et les circuits base de cellules compiles. 5.3.2.1 les cellules prcaractrises

Les cellules prcaractrises sont des entits logiques plus ou moins complexes. Il peut s'agir de cellules de base (portes, bascules, etc.) mais aussi de cellules mmoires (ROM, RAM) ou encore de sous-systmes numriques complexes (UART, coeur de microprocesseur, PLA, ...). Toutes ces cellules ont t implantes et caractrises au niveau physique (d'o la notion de cellules prcaractrises) par le fondeur. La fonctionnalit globale de l'application raliser s'obtient en choisissant les cellules appropries dans une bibliothque fournie par le fondeur. Sur le plan topologique, 2 types de cellules prcaractrises existent : les cellules de hauteur fixe et de largeur variable, les cellules de hauteur et de largeur variables.

Dans le premier cas, l'association des cellules permet de dfinir des canaux pour les interconnexions ; le routage alors est simplifi. Dans le second cas, les canaux ne sont pas bien dlimits, ce qui complique le placement-routage. 5.3.2.2 Les circuits base de cellules compiles

Les circuits base de cellules compiles sont en fait bass sur l'utilisation de cellules prcaractrises. A la diffrence des circuits prcaractriss, les cellules ne sont pas utilisables directement mais au travers de modules paramtrables ou modules gnriques. Chaque module est cr par la juxtaposition de n cellules de mme type. La diffrence entre 247

circuits prcaractriss et circuits compils provient essentiellement de l'outil utilis pour gnrer les dessins des masques de fabrication. Ces outils sont appels des compilateurs de silicium. 5.4 Les circuits semi-custom

Dans la famille des circuits semi-custom, on distingue deux groupes : les circuits prdiffuss, les circuits programmables. 5.4.1 Les circuits prdiffuss Parmi les circuits prdiffuss, on distingue les prdiffuss classiques (ou "gate-array") et les rseaux mer-de-portes ("sea of gates"). 5.4.1.1 Les circuits prdiffuss classiques

Les circuits prdiffuss classiques possdent une architecture interne fixe qui consiste, dans la plupart des cas, en des ranges de portes spares par des canaux d'interconnexion. L'implantation de l'application se fait en dfinissant les masques d'interconnexion pour la phase finale de fabrication. Ces masques d'interconnexion permettent d'tablir des liaisons entre les portes et les plots d'entres/sorties. Alors que pour un circuit standard ou "fullcustom" 11 15 masques particuliers sont ncessaires, la fabrication des prdiffuss ne ncessite que la dfinition des 3 derniers masques pour chaque application ; les autres masques dfinissant l'architecture sont fixes. Cette technique permet de diminuer les dlais car les rseaux prdiffuss sont fabriqus au pralable ; seule manque la couche d'interconnexion qui va particulariser chaque circuit. Par contre, les portes non utilises sont perdues. Cette mthode est moins efficace qu'un full-custom en terme d'utilisation de la surface de silicium.

Les circuits prdiffuss classiques intgrent de 50000 1000000 portes logiques et sont intressants pour des grandes sries. Pour des prototypes ou de petites sries, ils sont progressivement abandonns au profit des circuits programmables haute densit d'intgration, comme les FPGA. En effet, ceux-ci ont l'avantage indniable dtre programmable sur site, c'est--dire sans faire appel au fondeur. La figure suivante donne un exemple de structure pour un prdiffus classique. Les cellules internes sont de taille fixe et organises en ranges ou colonnes spares par les canaux d'interconnexion. 248

5.4.1.2

Les circuits mer-de-portes

Contrairement aux prdiffuss classiques, les circuits mer-de-portes ne possdent pas de canaux d'interconnexion, ce qui permet d'intgrer plus d'lments logiques pour une surface donne. Les portes peuvent servir, soit comme cellules logiques, soit comme interconnexions. En fait, si ces circuits possdent la structure logique quivalente 250000 portes, pratiquement, le nombre moyen de portes utilisables est de l'ordre de 100000, ce qui donne un taux d'utilisation de 40% 50%. En effet, si les canaux d'interconnexion ne sont pas imposs ils sont nanmoins ncessaires. Le gain des structures mer-de-portes est ralis parce que ces interconnexions ne sont pas imposes par l'architecture. En pratique, le taux d'utilisation dpasse rarement 75%. 5.4.2 Les circuits programmables Tous les circuits spcifiques dtaills jusqu' prsent ont un point commun ; il est ncessaire de passer par un fondeur pour raliser les circuit, ce qui introduit un dlai de quelques mois dans le processus de conception. Cet inconvnient a conduit les fabricants proposer des circuits programmables par l'utilisateur (sans passage par le fondeur) qui sont devenus au fil des annes, de plus en plus volus. Rassembls sous le terme gnrique PLD, les circuits programmables par l'utilisateur se dcomposent en deux familles : 1. les PROM, les PLA, les PAL et les EPLD, 2. les FPGA.

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PLD (Circuit logique programmable)

PROM

PLA ou PAL (bipolaire non effaable)

PLD effaable (circuit logique effaable)

FPGA (rseaux de portes programmables)

PAL CMOS ou GAL

EPLD ou CPLD

FPGA de type RAM

FPGA anti-fusibles

5.4.2.1

Les PROM

Nous allons voir dans ce paragraphe la PROM sous langle de la ralisation dune fonction logique. Mme si elle nest plus utilise pour cela aujourdhui, elle est la base de la famille de PLA, des PAL et des EPLD.

Convention de notation Afin de prsenter des schmas clairs et prcis, il est utile d'adopter une convention de notation concernant les connexions fusibles. Les deux figures suivantes reprsentent la fonction ET 3 entres. La figure b) n'est qu'une version simplifie du schma de la figure a).
a b a b c a.b.c c a.b.c

a)

b)

Un exemple de notation est donn sur la figure ci-contre. La fonction ralise est S = (a . c) + (b . d). Une croix, une intersection, indique la prsence d'une connexion fusible non claqu. L'absence de croix signifie que le fusible est claqu. La liaison entre la ligne 250

horizontale et verticale est rompue. La sortie S ralise une fonction OU des 2 termes produits (a.c) et (b.d).
a b c d

Les premiers circuits programmables apparus sur le march sont les PROM bipolaires fusibles. Cette mmoire est l'association d'un rseau de ET fixes, ralisant le dcodage d'adresse, et d'un rseau de OU programmables, ralisant le plan mmoire proprement dit. On peut facilement comprendre que, outre le stockage de donnes qui est sa fonction premire, cette mmoire puisse tre utilise en tant que circuit logique. La figure ci-dessous reprsente la structure logique d'une PROM bipolaire fusibles.

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Chaque sortie Oi peut raliser une fonction OU de 16 termes produits de certaines combinaisons des 4 variables A, B, C et D. Avec les PROM, les fonctions logiques programmes sont spcifies par les tables de vrits. Le temps de propagation est indpendant de la fonction implante. 5.4.2.2 Les PLA

Le concept du PLA a t dvelopp il y a plus de 20 ans. Il reprend la technique des fusibles des PROM bipolaires. La programmation consiste faire sauter les fusibles pour raliser la fonction logique de son choix. La structure des PLA est une volution des PROM bipolaires. Elle est constitue d'un rseau de ET programmables et d'un rseau de OU programmables. Sa structure logique est la suivante :

Chaque sortie Oi peut raliser une fonction OU de 16 termes produits des 4 variables A, B, C et D. Avec cette structure, on peut implmenter n'importe quelle fonction logique combinatoire. Ces circuits sont videmment trs souples d'emploi, mais ils sont plus difficiles utiliser que les PROM. Statistiquement, il s'avre inutile d'avoir autant de possibilit de programmation, d'autant que les fusibles prennent beaucoup de place sur le silicium. Ce type 252

de circuit n'a pas russi pntrer le march des circuits programmables. La demande s'est plutt oriente vers les circuits PAL. 5.4.2.3 Les PAL

Contrairement aux PLA, les PAL (Programmable Array Logic) imposent un rseau de OU fixes et un rseau de ET programmables. La technologie employe est la mme que pour les PLA. La figure qui suit reprsente la structure logique d'un PAL o chaque sortie intgre 4 termes produits de 4 variables.

L'architecture du PAL a t conue partir d'observations indiquant qu'une grande partie des fonctions logiques ne requiert que quelques termes produits par sortie. L'avantage de cette architecture est l'augmentation de la vitesse par rapport aux PLA. En effet, comme le nombre de connexions est diminu, la longueur des lignes d'interconnexion est rduite. Le temps de propagation entre une entre et une sortie est par consquent rduit.

En revanche, il arrive qu'une fonction logique ne puisse tre implante, car une sortie particulire n'a pas assez de termes produits. Prendre un botier plus gros, peut tre 253

prjudiciable en terme de rapidit, le temps de propagation tant proportionnel la longueur des lignes d'interconnexion du rseau de ET et donc au nombre dentres. Pour remdier cette limitation, il a fallu modifier les entres/sorties du circuit. Le PAL possde toujours des entres simples sur le rseau de ET programmables, mais aussi des broches spciales (voir figure ci-dessous) qui peuvent tre programmes : en entre simple en faisant passer le buffer de sortie trois tats en haute impdance, en sortie rinjecte sur le rseau de ET. Cela permet daugmenter le nombre de termes produits disponibles sur les autres sorties.

Les structures prsentes jusqu' maintenant ne font intervenir que de la logique combinatoire. Les architectures des PAL ont volu vers les PAL registres. Dans ces PAL, la sortie du rseau de fusibles aboutit sur l'entre d'une bascule D. La sortie Q peut aller vers une sortie, la sortie Q tant rinjecte sur le rseau via un inverseur/non inverseur.

Avec cette structure, la sortie ne peut tre utilise comme entre sur le rseau. L'exemple d'un PAL registres 16R8 est donn la page suivante. Il implmente 8 termes produits de 16 variables par sortie. D'aprs la notation employe par les fabricants, la rfrence 16R8 signifie : 16 : nombre d'entres au niveau du rseau de ET. R : PAL registres. 8 : nombre de sorties. Les plus gros PAL standards sont les 20R8 et 20L8. 254

Le PAL versatile (polyvalent), dont le membre le plus connu est le 22V10, prsente une volution des PAL vers les circuits logiques programmables de plus haut niveau. En effet, ils continuent de respecter le principe de fonctionnement nonc prcdemment, mais ils utilisent une structure de cellule de sortie qui sapparente un EPLD. D'aprs la figure suivante, on remarque que la cellule de sortie dispose d'une bascule D pr-positionnable associe deux multiplexeurs programmables. Les connexions S0 et S1 sont ralises grce des fusibles internes.

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Cette sortie peut adopter plusieurs configurations (do le terme polyvalent), le 22V10 pouvant donc tre utilis la place de tous les PAL bipolaires classiques: sortie combinatoire active au niveau bas, sortie combinatoire active au niveau haut, sortie registre active au niveau bas, sortie registre active au niveau haut. Les premiers PAL pouvaient tre assez facilement programms la main. Toutefois, la ralisation de fonctions complexes est devenue rapidement inextricable. Des logiciels de dveloppement sont donc apparus afin de faciliter ce travail. Il en existe de nombreux, les plus connus tant PALASM (socit AMD) et ABEL (socit DataIO). Au-del dun certain niveau de complexit, lutilisation de leur simulateur intgr permet une mise au point rapide de la fonction raliser. Tous les PAL disposent d'un fusible ou bit de scurit. Ce fusible, une fois claqu, interdit la relecture d'un composant dj programm. En effet, il arrive que des entreprises indlicates soient tentes de copier les PAL dvelopps par leurs concurrents. Un des inconvnients des circuits bipolaires fusibles, est qu'ils ne peuvent pas tre tests la sortie de l'usine. Pour tester leur fonctionnement, il faudrait en effet claquer les fusibles, ce qui interdirait toute programmation ultrieure. A l'origine, les premiers PAL taient bipolaires puisqu'ils utilisaient la mme technologie que les PROM bipolaires fusibles. Il existe maintenant des PAL en technologie CMOS (appels GAL (Generic Array Logic) par certains fabricants), programmables et effaables lectriquement, utilisant la mme technologie que les mmoires EEPROM. Comme ils sont en technologie CMOS, ils consomment beaucoup moins, en statique, que les PAL bipolaires de complexit quivalente. 256

5.4.2.4

Les EPLD

Les EPLD (Erasable Programmable logic Device) sont des circuits programmables lectriquement et effaables, soit par exposition aux UV pour les plus anciens, soit lectriquement. Ces circuits, dvelopps en premier par la firme ALTERA, sont arrivs sur le march en 1985. Les EPLD sont une volution importante des PAL CMOS. Ils sont bass sur le mme principe pour la ralisation des fonctions logiques de base. Les procds physiques d'intgration permis par les EPLD sont nettement plus importants que ceux autoriss par les PAL CMOS. En effet, les plus gros EPLD actuellement commercialiss intgrent jusqu' 24000 portes logiques dont 12000 sont rellement accessibles l'utilisateur. On peut ainsi loger dans un seul botier, l'quivalent d'un schma logique utilisant jusqu' 50 100 PAL classiques.

Comme les PAL CMOS, les EPLD font appel la notion de macro-cellule qui permet, par programmation, de raliser de nombreuses fonctions logiques combinatoires ou squentielles. Le schma type de la macro-cellule de base d'un EPLD est prsent ci-dessous. On remarque que le rseau logique est compos de 3 sous ensembles : le rseau des signaux d'entres provenant des broches d'entres du circuit, le rseau des signaux des broches d'entres/sorties du circuit, le rseau des signaux provenant des autres macro-cellules.

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Outre la logique combinatoire, la macro-cellule possde une bascule configurable ( bascule D, T, RS ou JK). Cette bascule peut tre dsactive par programmation dun multiplexeur. Le signal d'horloge peut tre commun toutes les macro-cellules, ou bien provenir d'une autre macro-cellule via le rseau logique.

Quelque soit la famille d'EPLD, la fonctionnalit de la macro-cellule ne change gure. En revanche, plus la taille des circuits augmente, plus les possibilits d'interconnexions et le nombre de macro-cellules augmentent. On voit ci-dessous la structure dun EPLD de la famille MAX 5000 dALTERA

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Il existe plusieurs types d'EPLD en technologie CMOS : Les circuits programmables lectriquement et non effaables. Ce sont les EPLD de type OTP (One Time Programmable). Les circuits programmables lectriquement et effaables aux UV. Les circuits programmables lectriquement et effaables lectriquement dans un programmateur. Les circuits programmables lectriquement et effaables lectriquement sur la carte (ISP : In Situ Programmable), utilisant une tension unique de 5 V. Les plus rapides des EPLD ont des temps de propagation (entre vers sortie sans registre) de l'ordre de 12 ns. En revanche, comme ils sont en technologie CMOS, leur consommation crot avec l'augmentation de la frquence de fonctionnement. Le taux d'utilisation des ressources d'un EPLD dpasse rarement 80 %. Avec les EPLD, il est possible de prdire la frquence de travail maximale d'une fonction logique, avant son implmentation. On rencontre parfois le terme CPLD (Complex Programmable Logic Device). Ce terme est gnralement utilis pour dsigner des EPLD ayant un fort taux d'intgration. 5.4.2.5 Les FPGA

Lanc sur le march en 1984 par la firme XILINX, le FPGA (Field Programmable Logic Device) est un circuit prdiffus programmable. Le concept du FPGA est bas sur l'utilisation d'un multiplexeur comme lment combinatoire de la cellule de base. La figure suivante reprsente la cellule type de base d'un FPGA. Elle comprend un multiplexeur 8 vers 1 permettant de raliser nimporte quelle fonction logique combinatoire de 4 variables (appel LUT : Look Up Table ou encore gnrateur de fonction). La bascule D permet la ralisation de fonctions logiques squentielles. La configuration du multiplexeur 2 vers 1 de sortie autorise la slection des deux types de fonction.
D0 O1 D0 D1 D2 D3 D4 D5 D6 D7 D1 S

DATA

C S0 S1 S2 S0 S1 S2 clock select

QN

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Les cellules de base d'un FPGA sont disposes en ranges et en colonnes. Des lignes d'interconnexions programmables traversent le circuit, horizontalement et verticalement, entre les diverses cellules. Ces lignes d'interconnexions permettent de relier les cellules entre elles, et avec les plots d'entres/sorties. Les connexions programmables sur ces lignes sont ralises par des transistors MOS dont l'tat est contrl par des cellules mmoires SRAM. Ainsi, toute la configuration d'un FPGA est contenue dans des cellules SRAM.

Contrairement aux EPLD, on ne peut pas prdire la frquence de travail maximale d'une fonction logique, avant son implmentation. En effet, cela dpend fortement du rsultat de l'tape de placement-routage.

Tous les FPGA sont fabriqus en technologie CMOS, les plus gros d'entre eux intgrent jusqu' 1000000 portes logiques utilisables. Il faut noter que la surface de silicium d'un FPGA est utilise au 2/3 pour les interconnexions et au 1/3 pour les fonctions logiques. Le taux d'utilisation global des ressources ne dpasse pas 80 %.

Par rapport aux prdiffuss classiques, les interconnexions programmables introduisent des dlais plus grands que la mtallisation. Par contre, les cellules logiques fonctionnent la mme vitesse. Pour minimiser les dlais de propagation dans un FPGA, il faut donc rduire le nombre de cellules logiques utilises pour raliser une fonction. Par consquent, les cellules logiques dun FPGA sont plus complexes que celles dun prdiffus.

5.4.2.6

Les FPGA anti-fusibles

Commercialiss partir de 1990, ce FPGA, programmable une seule fois, est bas sur la technologie des interconnexions anti-fusibles. Sa structure s'apparente celle d'un prdiffus mer-de-portes, c'est--dire qu'il dispose de cellules lmentaires organises en ranges et en colonnes. Les lignes d'interconnexions programmables traversent le circuit, horizontalement et verticalement, entre les diverses cellules. La technologie anti-fusibles permet de rduire considrablement la surface prise par les interconnexions programmables, par rapport aux interconnexions base de SRAM. La cellule lmentaire diffre d'un fabricant un autre, mais elle est gnralement compose de quelque portes logiques. Le nombre de ces cellules est gnralement trs important.

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Alors que le FPGA SRAM est utilis pour des prototypes ou des petites sries, le FPGA anti-fusibles est destin pour des plus grandes sries, en raison de son cot de fabrication moins lev. Il est gnralement conu avec des outils de synthse de type VHDL.

5.4.2.7

Conclusion

Le tableau suivant donne les caractristiques principales de 4 circuits programmables par l'utilisateur.

Rfrence Fabricant Type Technologie

AmPAL22V10 AMD PAL

EPM7256E ALTERA EPLD

XC4025E XILINX FPGA

A54SX32 ACTEL FPGA mer-deportes anti-fusibles

bipolaire fusibles EEPROM CMOS SRAM CMOS

nombre de I/O

I = 22 max O = 10 max

164 I/O max

256 I/O max

249 I/O max

nombre de portes nombre de cellules

500 portes 1 cellule

10 000 portes 256 cellules

25 000 portes 1024 cellules

32 000 portes 2 880 cellules

Pour claircir les ides, on peut classer les circuits numriques spcifiques une application suivant l'architecture du circuit. C'est--dire quels sont le ou les constituants de base mis la disposition de l'utilisateur et quelles sont les possibilits d'interconnexion de ces constituants et par quelle technique? On parle en gnral de la granularit de l'architecture. La figure suivante reprend la classification des circuits spcifiques une application suivant leur architecture.

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5.5

Implmentation

Les PLD et les prdiffuss sont des circuits spcifiques dont les puces de silicium ont dj des cellules implantes. Durant l'tape d'implmentation, il faut rsoudre les problmes du placement de la logique dans les cellules de base puis des interconnexions. L'implmentation est ralise une fois la saisie du design termine. Le design peut tre entr, soit graphiquement (schmatique), soit sous forme de langages de programmation (VHDL, quations boolennes, ...). Les tapes de l'implmentation sont :

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1. La translation. L'tape de translation consiste tablir une liste d'interconnexions, appele netlist, partir du design. Cette netlist est un fichier texte qui rpertorie toutes les fonctions logiques de base ainsi que leurs interconnexions. 2. L'optimisation. L'tape d'optimisation reprend la netlist pour liminer les portes inutiles et la logique redondante. 3. Le partitionnement. Le design, une fois optimis, est partitionn en blocs logiques pouvant tre implment dans les cellules de base du circuit spcifique. 4. Le placement-routage. Le placement dtermine la position de chaque bloc logique partitionn l'intrieur du circuit spcifique. Les algorithmes de placement fonctionnent par itrations. Ils essaient de raliser le meilleur placement possible, c'est--dire qu'ils regroupent dans une mme zone du circuit une fonction ncessitant plusieurs cellules de base, ceci afin de limiter les temps de propagation. Cependant, le rsultat du placement n'est pas toujours idal, principalement dans le cas des FPGA. Il est souvent ncessaire de placer manuellement une partie du design (c'est le Floorplanning ). Une fois la phase de placement termine, l'tape de routage doit tre effectue. Elle utilise les ressources de routage du circuit pour raliser les interconnexions entre les diffrentes cellules et les broches d'entre/sortie. Aprs l'tape de placement-routage, l'implmentation est termine ; le circuit spcifique peut tre programm partir d'un fichier binaire de configuration obtenu. 5.6 Comparaison entre les FPGA et les autres circuits spcifiques

La comparaison et donc le choix entre les diffrentes technologies est une tape dlicate car elle conditionne la conception mais aussi toute lvolution du produit concevoir. De plus, elle dtermine le cot de la ralisation et donc la rentabilit conomique du produit. Gnralement, les quantits produire imposent leurs conditions de rentabilit, dans le domaine du grand public par exemple. Par contre, dans le matriel professionnel, toutes les options sont ouvertes. Il faut tablir un rapport cot / souplesse dutilisation le plus souvent avec des donnes partielles (pour les quantits produire par exemple). Nous allons nous contenter dans ce paragraphe de comparer ce qui est comparable (PLD / ASIC, EPLD / FPGA) et de donner une mthode de calcul des cots des familles ASIC et PLD. 5.6.1 Comparaison entre les PLD et les ASIC. Un premier choix doit tre fait entre les ASIC et les PLD. Les avantages des PLD par rapport aux ASIC sont les suivants :

263

ils sont entirement programmables par l'utilisateur, Ils sont gnralement reprogrammables dans l'application, ce qui facilite la mise au point et garantit la possibilit d'volution, les dlais de conception sont rduits, il n'y a pas de passage chez le fondeur.

En revanche, les inconvnients des PLD par rapport aux ASIC sont les suivants : ils sont moins performant en terme de vitesse de fonctionnement (dun facteur 2 3), le taux d'intgration est moins lev (dun facteur 10 environ), les ressources d'interconnexion utilisent en gnral les 2/3 de la surface de silicium.

De plus, le cot de lASIC est beaucoup plus faible que le cot du PLD (quoique les choses voluent trs rapidement dans ce domaine, notamment dans la comptition entre FPGA et prdiffuss). Au del dune certaine quantit, lASIC est forcement plus rentable que le PLD. Toute la question est donc de savoir quelle est cette quantit ? 5.6.2 Comparaison entre les FPGA et les EPLD Si un PLD est choisi, il faut savoir si on doit utiliser un EPLD ou un FPGA. Les avantages des FPGA par rapport aux EPLD sont les suivants : le taux d'utilisation des ressources peut atteindre 80 %, ce qui est meilleur qu'un EPLD, ils consomment moins fonctionnalit identique ( < 10 mA par 1000 portes), les fonctions ralisables sont plus complexes.

Les inconvnients des FPGA par rapport aux EPLD sont les suivants : les EPLD sont plus performants pour certaines fonctions arithmtiques rapides, les frquences de fonctionnement sont variables suivant la mthode de placement routage retenue. Les EPLD ont des frquences de travail "prdictibles".

En fait, le domaine d'utilisation des FPGA est celui des prdiffuss, par exemple les fonctions logiques ou arithmtiques complexes ou le traitement du signal. Le domaine d'utilisation des EPLD est plutt celui des PAL, par exemple les machines d'tat complexes. Il est noter qu'un march important des PAL et des EPLD est la correction des erreurs de conception dans les ASIC afin d'viter un aller-retour coteux chez le fondeur.

264

5.6.3 Seuil de rentabilit entre un FPGA et un ASIC Avec un taux d'intgration de plus en plus important, les FPGA deviennent trs intressants pour des productions en srie par rapport aux ASIC. La question qui se pose au concepteur est la suivante : combien d'units doit on produire, pour que l'ASIC soit plus rentable que le FPGA ?

Le facteur principal qui dtermine le cot dun circuit intgr est la surface de la puce ou encore le nombre de puces que lon peut fabriquer sur une tranche de silicium. On travaille aujourdhui avec des tranches de 200 mm de diamtre et le plus grosses puces sont de dimension 20x20 mm. Deux lments peuvent fixer la taille de la puce : le nombre de portes utilises pour raliser la fonction logique et le nombre dentres-sorties. Jusqu' la technologie 0.5 m, cest la fonction logique qui dtermine la taille de la puce et donc son prix. Cest la raison pour laquelle, fonctionnalit identique, le circuit full-custom est le moins cher alors que le PLD est le plus coteux produire. Mais avec des circuits de plusieurs centaines de broches, la taille de la puce tend tre fixe de plus en plus par les E/S et les diffrences de prix sestompent (notamment entre les FPGA et les prdiffuss).

Sans entrer dans les dtails, une analyse rapide peut donner un ordre de grandeur du seuil de rentabilit entre un FPGA et un ASIC. Prenons comme exemple un botier de 10 000 portes. L'tude se base sur des donnes fournies par la socit d'tudes de march DATAQUEST en 1995. La formule de base du seuil de rentabilit est la suivante :

seuil de rentabilit = NRE + (dveloppement et outils) + ( X units * prix l'unit)

Les NRE (Non Recurring Expenses) sont les frais fixes de mises en uvre. On obtient pour les ASIC et les FPGA les deux formules suivantes :

ASIC = $25 000 (NRE) + $79 000 (dveloppement et outils) + ( X units * $13) FPGA = 0 NRE + $25 000 (dveloppement et outils) + ( X units * $79)

Il n'y a pas de NRE pour un FPGA. Les NRE sont imputs chaque fois que l'on fait appel un fondeur. A partir des 2 quations ci-dessus, le seuil de rentabilit est atteint pour 1 196

265

units. Le FPGA devient plus cher produire qu'un ASIC au del de 1 196 units. En fait, il existe d'autres facteurs qui influent grandement sur le seuil de rentabilit : Le time to market (temps de mise sur le march). C'est le temps coul entre le dbut de l'tude et la phase de production. Prendre du retard sur le lancement d'un produit sur le march, en raison d'un cycle de dveloppement et de mise au point trop long, a des effets ngatifs en terme de rentabilit. Le cycle moyen de dveloppement d'un FPGA est de 11 semaines, il passe 32 semaines pour un ASIC. La correction des erreurs. Environ 30 % des ASIC retournent chez le fondeur pour des modifications (11 % sont des erreurs du fondeur et 19 % sont des modifications du design). Ce nouveau cycle de dveloppement introduit un dlai supplmentaire de 12 semaines. Pour un FPGA, une modification du design est trs rapide, et n'apporte pratiquement pas de surcot. Les FPGA masqus. Les interconnexions programmables de ces FPGA sont remplacs par des interconnexions fixes chez le fabricant (sries Hardwire chez Xilinx par exmple). Le circuit n'est alors plus reprogrammable. Ils sont compatibles, broche broche, avec les FPGA programmables du mme fabricant mais ils sont environ 50 % moins chers, les NRE tant beaucoup moins levs que pour les ASIC. La mthode consiste dvelopper le prototype avec un FPGA programmable puis envoyer le fichier de configuration final chez le fondeur. Celui-ci produit les FPGA Hardwire avec la configuration souhaite mais il y a une quantit minimum de quelques milliers dunits commander.

Les chiffres permettant de quantifier les seuils de rentabilit entre les familles de circuits sont difficiles obtenir et parfois hautement subjectifs. Les ordres de grandeur des seuils de rentabilit sont les suivants :

jusqu' 5000 pices PLD

entre 5000 et 50000 prdiffus

entre 50000 et 500000 prcaractris

plus de 500000 full-custom

Il est important de noter quil existe une nette tendance visant remplacer le prdiffus par le FPGA, certains fabricants (comme Xilinx) prtendant commercialiser des FPGA moins cher que des prdiffuss pour des quantit de 100000 pices. Il est difficile davoir une opinion tranche car les deux familles voluent trs rapidement.

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5.7

Exercices

Exercice 5.1 Soit le PAL ci-dessous :

On dsire implmenter, l'aide de ce circuit, les fonctions suivantes : O3 = A.B.C.D, O2 = A+B+C+D, O1 = A.B.C.D et O0 = A B C . 1. Quels sont les caractristiques des fonctions que l'on peut raliser avec ce PAL (nombre de termes produits) ? 2. Une croix reprsente un fusible non-claqu. Supprimer les croix ncessaires afin de raliser les fonctions souhaites.

Exercice 5.2 On dsire raliser un convertisseur code BCD code Gray 4 entres. 267

1. Donner la table de vrit du systme. 2. Simplifier les quations logiques laide des tableaux de Karnaugh. 3. On souhaite utiliser le PAL dont le schma se trouve l'exercice 25.1. Supprimer les croix ncessaires afin de raliser les fonctions souhaites.

Exercice 5.3 On souhaite raliser un comparateur travaillant sur deux bits. Il possde deux entres sur deux bits appeles AB et CD et 4 sorties : AB = CD (EQ), AB CD (NE), AB < CD (LT) et AB > CD (GT). 1. Donner la table de vrit du circuit. 2. Simplifier les quations logiques laide des tableaux de Karnaugh. 3. On souhaite utiliser le PAL dont le schma se trouve l'exercice 25.1. Supprimer les croix ncessaires afin de raliser les fonctions souhaites.

Exercice 5.4 On souhaite raliser un dcodeur hxadcimal pour afficheur 7 segments suivant le schma (les LED ralisant lafficheur sont allumes si la cathode est 0 V) :
C0 C5 C4 C6 C3 C1 C2

C 0 C 1 C2 C 3 C 4 C 5 C 6 TA (test afficheur) EA (extinction afficheur)

Convertisseur Hxa -7 segments D3 D2 D1 D0

1. Donner la table de vrit du circuit. 2. Simplifier les quations logiques laide des tableaux de Karnaugh. 3. On souhaite utiliser un PAL 16L8 (voir schma ci-aprs). Quelles sont ses caractristiques ? 4. Placer les croix ncessaires sur le schma suivant afin de raliser les fonctions souhaites.

268

Exercice 5.5 On souhaite raliser un registre dcalage universel 8 bits (en fait, il s'agit d'une rotation gauche). Il possde 3 entres de contrle S2, S1 et S0 indiquant le nombre de dcalage gauche effectuer sur les bits de donnes D7, D6, ..., D0. La donne dcale gauche est disponible sur les sorties O7, O6, ..., O0. 1. Donner la table de vrit du circuit.

269

2. Donner les quations logiques des sorties. 3. On souhaite utiliser un PAL 20R8 (voir schma ci-dessous). Quelles sont ses caractristiques ? 4. Placer les croix ncessaires sur le schma afin de raliser les fonctions souhaites.

270

6. Conversion analogique/numrique
Les systmes de traitement numrique acceptent en entre et restituent des grandeurs physiques qui voluent le plus souvent de manire analogique. On peut parfois capter ou restituer directement ces grandeurs en numrique (comme par exemple dans le cas dune camra CCD ou dun cran plat LCD) mais il faut gnralement convertir le signal analogique dentre en signal numrique puis convertir aprs traitement le signal numrique en signal analogique. Ce paragraphe va traiter des circuits assurant ces conversions. 6.1 Principes fondamentaux

6.1.1 Introduction Malgr les nombreuses possibilits dutilisation des convertisseurs, on peut tablir le schma typique dune chane de traitement de linformation.
Entre analogique Filtre passe-bas anti-repliement Sortie analogique Traitement numrique Conversion numrique/ analogique Filtre passe-bas de lissage

Conversion analogique/numrique Echantillonnage Quantification

On trouve toujours dans une telle chane trois oprations principales : Le passage du signal analogique au signal numrique, cest--dire le filtrage passe-bas anti-repliement, lchantillonnage et la quantification. Les deux dernires tapes forment la conversion analogique/numrique. Le traitement numrique. Le passage du signal numrique au signal analogique, cest--dire la conversion analogique/numrique et le filtrage passe-bas de lissage.

Cette chane conduit dfinir trois types de signaux : 1. Le signal analogique. Cest un signal dont lamplitude varie de manire continue en fonction du temps. 2. Le signal chantillonn. Cest un signal dont lamplitude varie de manire discontinue avec le temps. Son amplitude est gale celle du signal analogique tous les instants n.Te et vaut 0 ailleurs. Ce signal est donc constitu dune suite dchantillons espacs de Te, la priode dchantillonnage. 271

amplitude

Signal analogique Signal chantillonn

temps -Te 0 Te 2Te 3Te 4Te 5Te 6Te 7Te 8Te 9Te

3. Le signal quantifi (ou signal numrique). Lamplitude de chaque chantillon du signal prcdent est un nombre rel de prcision infini (par exemple, 7.2354 volts). Pour pouvoir traiter un chantillon en numrique, il faut commettre une approximation sur son amplitude pour pouvoir utiliser un nombre fini de bits. Cest la quantification. Le signal quantifi est converti par exemple sur 8 bits, ce qui signifie que chaque chantillon rel est cod avec 8 bits. Le signal numrique est donc une suite de nombres binaires cods sur 8 bits qui reprsente le signal analogique de dpart.

Tout le problme est de savoir sous quelles conditions le signal numrique reprsente fidlement le signal analogique. 6.1.2 Echantillonnage La premire question qui se pose est la valeur de la frquence dchantillonnage Fe. Plaonsnous dans le cas suivant :

Signal analogique dentre Convertisseur analogique/numrique CAN N bits

Signal analogique restitu Convertisseur numrique/analogique CNA

Fe = Frquence dchantillonnage

272

Le thorme de Shannon dit que, pour que le signal analogique restitu soit identique au signal analogique dentre (avec des convertisseurs parfaits), il est ncessaire que :

Fe > 2.Fb, Fb tant la frquence la plus leve du signal chantillonner. Par exemple, dans le cas dun signal sinusodal de frquence 1 kHz, la frquence dchantillonnage doit tre suprieure 2 kHz pour que lon puisse rcuprer le signal originel aprs conversion numrique/analogique.

Des signaux plus complexes comme le son ou limage ont un spectre trs large (voir mme thoriquement infini). Il est donc ncessaire de les filtrer pour limiter la bande des frquences quils occupent avant de pouvoir les chantillonner. Le filtre passe-bas utilis pour cette opration est appel filtre anti-repliement car le non respect du thorme de Shannon provoque des repliements de spectre dans le signal analogique. Par exemple, dans le cas du disque compact audio, la bande passante du son est limite 20 kHz pour une frquence dchantillonnage gale 44.1 kHz.

Lorsque nous avons dfinit le signal chantillonn, la dure de chaque chantillon tait suppose trs faible (voire mme nulle). Or, la valeur de lchantillon doit tre maintenue suffisamment longtemps pour que la quantification puisse avoir lieu. On appelle cette opration le blocage. Le schma suivant montre le signal en sortie dun chantillonneurbloqueur.

amplitude

Signal analogique Signal chantillonn-bloqu

temps -Te 0 Te 2Te 3Te 4Te 5Te 6Te 7Te 8Te 9Te

Le schma synoptique dun montage chantillonneur-bloqueur (E/B) et son fonctionnement sont plutt simples :
273

amplitude

Vana Vech

Vana

Vech 0 Te 2Te 3Te

temps

I ferm, charge de C

I ouvert, C reste charg

Au moment de lchantillonnage, linterrupteur I se ferme et la capacit C se charge la valeur de lamplitude du signal analogique dentre Vana. Aprs le temps ncessaire cette charge, linterrupteur souvre et la valeur chantillonne est disponible aux bornes de C pour la quantification. En fait, le fonctionnement est plus complexe cause de limperfection de linterrupteur analogique (Ron 0 et Roff ) et de limpdance dentre du quantificateur (Ze ).
6.1.3 Quantification

Lespace des amplitudes du signal chantillonn est divis en intervalles qui peuvent tre :
De mme hauteur. Cest la quantification linaire qui est utilise dans le cas gnral. De hauteur diffrentes. On parle alors de quantification non-linaire (en particulier en

fonction de lois logarithmiques comme la loi A ou la loi utilises en tlphonie pour coder avec plus de prcision les amplitudes faibles que les amplitudes leves).

La valeur numrique de lchantillon quantifier sobtient en prenant le numro de code associ au niveau le plus proche. Les codages les plus utiliss sont le codage binaire, BCD, Gray Dans ce cours, on ne traitera que de la quantification linaire avec codage en binaire naturel comme sur la figure suivante : 274

amplitude 1V

Codes binaires 111 110 101 100 011 010 001

Niveau de quantification

Signal chantillonn-bloqu

Signal quantifi

011 0V 0 Te

101

110

101

010 5Te

000

temps

2Te

3Te

4Te

Lcart entre deux niveaux de quantification successifs (ou encore la hauteur dun intervalle) est appel pas de quantification . Dans lexemple prcdent, on a 8 niveaux (codage sur 3 bits) entre 0 et 1 Volt soit 7 intervalles. Le pas de quantification est donc gal 0.143 Volt (1/7). On peut maintenant dfinir la fonction de transfert dun convertisseur analogique/numrique (3 bits) en plaant lamplitude analogique du signal en abscisse et les valeurs numriques obtenues aprs conversion en ordonne.
Valeurs numriques 111 110 101 100 011 010 Vcod 001 000 0V Vanalogique Vref 2Vref 3Vref 4Vref 5Vref 6Vref 7Vref Vref 8 8 8 8 8 8 8

275

Vous noterez que lon a cr 9 niveaux analogiques compris entre 0 V et Vref afin dobtenir 8 intervalles cods de 000 111. A chaque valeur analogique convertir est associe une valeur numrique de sortie qui correspond au niveau de quantification le plus proche. Dans cette configuration, le pas de quantification pour un convertisseur N bits est gal :
= Vref [V]. 2N

La tension continue de rfrence Vref est gale lamplitude maximale du signal analogique lentre du convertisseur. Soit un mot binaire B = bN-1, bN-2, b1, b0. bN-1 est appel le bit le plus significatif (MSB : Most Significant Bit) et b0 le bit le moins significatif (LSB : Least Significant Bit). La tension analogique correspondant la valeur numrique B est gale :
b b b N 1 b N 2 b N 3 0 + 1 + 2 + ... + N1 2 + N01 2 2 2 2 2

Vcod =

Vref 2

Prenons par exemple un codage sur 4 bits et une tension de rfrence de 5 V. Le pas de quantification est gal 312.5 mV, une valeur numrique 1010 correspond une tension analogique gale 3.125 V. La conversion analogique/numrique seffectue en considrant lappartenance de la tension dentre un intervalle centr sur les valeurs de Vcod. Il y a donc naturellement une diffrence entre la valeur de la tension code et la valeur du signal dentre. Cest lerreur de quantification ou erreur de conversion. Elle est aussi appele tension de rsidu. Plus la conversion est prcise et plus la valeur du rsidu est faible puisque :

Vanalogique = Vcod + Vrsidu La fonction de transfert dun convertisseur vue prcdemment nest valable quentre 0 et Vref (ou Vref/2, +Vref/2). Si la tension analogique sort de cette plage, la valeur numrique de sortie ne change plus. Les caractristiques dun convertisseur analogique/numrique ne sont dfinies que sur sa plage de tension dentre. Lchantillonnage est une opration qui ne change pas la valeur du signal analogique. Par contre, la quantification introduit un bruit rsultant de la diffrence entre la valeur analogique et la valeur numrique code. En appliquant lentre du convertisseur 3 bits vu prcdemment une tension variant linairement entre 0 et Vref, ce bruit (la tension de rsidu) varie selon la forme en dents de scie suivante :

276

erreur 2 2 0V Vref 2Vref 3Vref 4Vref 5Vref 6Vref 7Vref Vref 8 8 8 8 8 8 8 Vanalogique

Lerreur de quantification vaut au maximum la moiti du pas de quantification, cest dire

1 LSB . Ce bruit de quantification ajout au signal analogique peut tre gnant pour 2 certaines applications. En fait, il est inversement proportionnel au nombre de bits utiliss pour effectuer la conversion. Une formule couramment utilise lie le nombre de bits au rapport signal sur bruit (SNR) de la conversion :

V S [dB] = 20.log10 analogique efficace = 6.N + 1,76 dB V N bruit efficace

Par exemple, on a gnralement un SNR gal 50 dB en tlvision. On doit donc utiliser un convertisseur 8 bits (6x8 + 1,76 50 dB) pour travailler dans ce domaine. Cette formule est calcule avec une tension sinusodale pleine chelle (entre 0 et Vref) lentre du convertisseur. Il faut bien comprendre que le bruit de quantification ne dpend que du nombre de bits utiliss pour la conversion, mais pas de lamplitude du signal dentre. Si vous nutilisez pas toute la plage disponible (la dynamique dentre), le SNR diminue dans les mmes proportions que le signal dentre. Si la dynamique est par exemple de 1 V et que le signal analogique ne fait que 500 mV crte crte damplitude, le SNR est divis par 2, soit SNR = 6.N 4,24 dB.
6.1.4 Reconstruction du signal analogique

Thoriquement, un simple filtre passe-bas suffit pour restituer le signal aprs chantillonnage. La quantification impose cependant lutilisation dun convertisseur numrique/analogique (CNA) pour passer dune suite de nombres binaires un signal similaire au signal chantillonn-bloqu vu prcdemment. Le CNA doit tre cadenc par une horloge de mme frquence que celle utilise pour le CAN. Le signal suivant est obtenu en sortie du CNA :

277

amplitude Signal en marches descalier

temps -Te 0 Te 2Te 3Te 4Te 5Te 6Te 7Te 8Te 9Te

Soit le mot binaire B = bN-1, bN-2, b1, b0. Lamplitude de lchantillon correspondant B en sortie du CNA est gale :
b b b N 1 b N 2 b N 3 0 + 1 + 2 + ... + N1 2 + N01 2 2 2 2 2

Vrestit =

Vref 2

On en dduit la fonction de transfert dun CNA (3 bits) :

Vrestitue Vref 7Vref 8 6Vref 8 5Vref 8 4Vref 8 3Vref 8 2Vref 8 Vref 8 0V 000 001 010 011 100 101 110 111 Valeurs numriques

278

La tension de sortie volue entre 0 et

7.Vref , la tension continue de rfrence Vref ntant 8

pas ncessairement gale celle utilise pour le CAN.

Il reste maintenant passer du signal en marches descalier au signal analogique rel. Il faut pour cela passer le signal dans un filtre passe-bas appel filtre de lissage . Pour un signal analogique dont le spectre est compris entre 0 et Fb, la frquence de coupure du filtre de lissage doit tre gale Fb. La slectivit de ce filtre (comme dailleurs celle du filtre antirepliement) doit tre leve.
6.2 Caractristiques des convertisseurs

6.2.1 Introduction

Le bruit de quantification est inhrent la conversion analogique/numrique. Ce nest cependant pas la seule source derreurs entre lentre et la sortie de notre chane de traitement de linformation. Les circuits convertisseurs analogique/numrique (CAN ou ADC en anglais) et convertisseurs numrique/analogique (CNA ou DAC en anglais) introduisent des distorsions supplmentaires. Le but dune conception soigne sera de minimiser ces erreurs et de se rapprocher autant que possible du rapport signal sur bruit thorique (d la seule quantification).
6.2.2 Les CNA

Les caractristiques statiques (mesures en continu) suivantes sappliquent aux CNA : La rsolution est la plus petite variation de sortie induite par un changement du mot code numrique en entre. Exprime en pourcentage de la variation pleine chelle (%FSR : % Full Scale Range), elle est gale 1 x100 %FSR. Elle est aussi souvent dfinie comme 2N

tant le nombre de bits N utiliss pour la conversion. La prcision (accuracy) tient compte de toutes les erreurs du CNA. Elle caractrise lcart maximal entre la valeur lue et la valeur vraie, rapport la tension pleine chelle. Elle est exprime en LSB. Lerreur de dcalage (offset error) caractrise lcart entre la courbe de transfert et la courbe idale. Elle est exprime en LSB.

279

Vrestitue Vref

Courbe idale

Courbe relle offset 0V 000 111 Valeurs numriques

Lerreur de gain (gain error) est due la diffrence de pente entre la fonction de transfert du convertisseur et la courbe idale. Cet cart est mesur pour la valeur numrique maximale, lerreur de dcalage tant compense. Il est exprim en LSB.

Vrestitue Vref

Courbe idale Erreur de gain Courbe relle

0V 000 111

Valeurs numriques

La non-linarit diffrentielle (differential nonlinearity) est la diffrence entre le pas de quantification q et la valeur V du signal de sortie rellement obtenue entre deux valeurs numriques adjacentes. V est mesur pour chaque code et on prend la valeur |V q| maximale exprime en LSB, les erreurs de dcalage et de gain tant compenses.

Vrestitue Vref V

Courbe idale

Courbe relle q

0V 000

011 100

111

Valeurs numriques

280

La non-linarit intgrale (integral nonlinearity) est le plus grand cart entre la fonction de transfert et la droite de conversion idale. Elle sexprime en LSB, les erreurs de dcalage et de gain tant compenses. La monotonie est une consquence de la linarit du CNA. Un convertisseur est monotone si un changement de valeur binaire lentre provoque une variation de la tension de sortie de mme signe. Par exemple, lapplication de codes binaires croissants sur le CNA doit correspondre en sortie avec des tensions croissantes. Un convertisseur nest pas monotone si la non-linarit diffrentielle est suprieure ou gale 1 bit ou encore si la pente de la fonction de transfert du convertisseur est ngative.

Vrestitue Vref

Courbe idale

Courbe relle

0V 000 111

Valeurs numriques

Le temps dtablissement (Settling time) ou temps de conversion est le temps ncessaire au convertisseur pour rpondre une variation pleine chelle du signal. On passe du mot code 000 au mot code 111 et on mesure le temps ncessaire pour que le convertisseur atteigne sa valeur finale en sortie avec une prcision de LSB.

Vrestitue 1 LSB Valeur finale

Temps dtablissement

0V
Changement de code

temps

281

La frquence de conversion (conversion rate) est le nombre maximal de conversions par seconde pour lequel les spcifications du CNA sont respectes.

Les CNA rapides ont des caractristiques dynamiques (mesures en alternatif) telles que : la distorsion harmonique totale (total harmonic distorsion THD). Lors de la conversion dune tension sinusodale, des sinusodes parasites ayant des frquences multiples de la frquence fondamentale sont cres. La THD mesure, en dB, le rapport entre la puissance des sinusodes parasites et celle de la sinusode principale. le rapport signal sur bruit (signal to noise ratio SNR). Par rapport la formule thorique, cette mesure incorpore toutes les distorsions et bruits du convertisseur. le nombre effectif de bits (Effective number of bits ENOB) est calcul partir de la mesure prcdente en appliquant la formule thorique du cours.

Le CNA possde aussi, comme le CAN, les caractristiques gnrales dun circuit intgr comme la tension dalimentation, la consommation ou le cot ainsi que la sensibilit des caractristiques la tension dalimentation et la temprature.
6.2.3 Les CAN

Les caractristiques du CAN ne sont valables qu lintrieur de sa plage de tension dentre. Certaines dentre elles sont dfinies de manire identique celles du CNA avec parfois quelques variantes : La rsolution dun CAN est la plus petite variation du signal dentre qui fait changer le mot binaire en sortie. La prcision (dfinition identique celle du CNA). Les dfinitions des erreurs de dcalage, de gain, de linarit (diffrentielle et intgrale) ainsi que la monotonie sont identiques celle du CNA, mais avec la fonction de transfert du CAN. Voici par exemple une erreur de gain :

282

Valeurs numriques 111

Courbe idale Erreur de gain Courbe relle

000 0V Vref

Vanalogique

Le temps dtablissement dun CAN est le temps ncessaire pour rpondre une variation pleine chelle du signal dentre. La frquence de conversion (conversion rate) est le nombre maximal de conversions par seconde support par le CAN. Les performances dynamiques comme la distorsion harmonique totale (total harmonic distorsion THD), le rapport signal sur bruit (signal to noise ratio SNR) ainsi que le nombre effectif de bits (Effective number of bits ENOB) sont dfinies de la mme manire que pour le CNA.

Les CAN possdent aussi des caractristiques qui diffrent de celles des CNA :

Lerreur dhystrsis. Les tensions de transition entre les niveaux peuvent tre diffrents selon le sens dans lequel la fonction de transfert est parcourue lors de conversions successives.
Valeurs numriques

000 0V

Vanalogique

283

Le dlai douverture (aperture delay) ou temps douverture est le temps qui spare la commande de conversion (gnralement sur le front actif de lhorloge) de la lecture effective de la tension analogique dentre. La dynamique dentre sans parasites (spurious-free dynamic range) est le rapport en dB entre la tension minimale et la tension maximale discernable par un CAN. Par exemple,

212 pour un CAN 12 bits, la dynamique dentre est gale : SFDR = 20log10 1 = 72,2 dB .
6.2.4 Problmes technologiques 6.2.4.1 Technologie employe

La supriorit de la technologie CMOS sexprime pleinement dans les domaines des traitements purement numriques ou bien pour intgrer des condensateurs. Mais quand il sagit dappairer des transistors (dans le cas dun amplificateur oprationnel AOP) ou de raliser plusieurs rsistances identiques (dans le cas des convertisseurs), la technologie bipolaire reste la meilleure. La technologie BicMOS peut aussi tre utilise pour raliser des convertisseurs puisquelle combine les avantages des technologies bipolaires et CMOS.

La technologie bipolaire est plutt utilise pour raliser des CNA et CAN rapides comme les CAN modles flash ou les CNA bass sur un rseau de rsistances. La technologie CMOS est utilise soit dans les convertisseurs lents tels que les convertisseurs approximations successives ou bien dans des convertisseurs plus rapides bass sur des capacits comme les CAN redistribution de charges.
6.2.4.2 Cblage

Un CAN se prsente gnralement sous la forme suivante :


AVCC AGND

Partie analogique

Vref Vana

CAN

Partie numrique

Horl DVCC

donnes

DGND

284

Le circuit intgr comprend deux parties distinctes, la partie analogique et la partie numrique. On trouve en gnral les broches suivantes :

Deux broches AVCC et AGND pour alimenter et mettre la masse la partie analogique. Deux broches DVCC et DGND pour alimenter et mettre la masse la partie numrique. Une entre analogique pour la tension de rfrence Vref (qui peut tre gnre en interne). Cette tension est de lordre de quelques volts. Une entre numrique dhorloge (cest lhorloge dchantillonnage). Une entre pour le signal analogique. Le bus de donnes en sortie.

Les lignes dalimentation des parties analogique et numrique doivent tre spares et la tension de rfrence et AVCC doivent tre dpourvues de bruit. Il est prfrable de se reporter la notice du constructeur pour raliser le circuit imprim autour du convertisseur si la frquence dchantillonnage est suprieure au MHz. La consquence dun cblage impropre du CAN est une diminution notable du SNR (ou de la dynamique dentre), diminution dautant plus grande que la frquence dchantillonnage est leve.

Un CNA se prsente quand lui sous la forme suivante :

AVCC

AGND

Partie analogique

Vref

CNA

Vana

Partie numrique

donnes Horl DVCC

DGND

Il comprend aussi deux parties distinctes, la partie analogique et la partie numrique. On trouve gnralement les broches suivantes :

Deux broches AVCC et AGND pour alimenter et mettre la masse la partie analogique. Deux broches DVCC et DGND pour alimenter et mettre la masse la partie numrique.

285

Une entre analogique pour la tension de rfrence Vref (qui peut tre gnre en interne). Cette tension est de lordre de quelques volts. Une entre numrique dhorloge (cest lhorloge dchantillonnage). La sortie analogique pour le signal. Deux cas peuvent se prsenter, le CNA sortie en courant et le CNA sortie en tension. Dans le premier cas, il faut obligatoirement mettre en sortie du circuit un amplificateur oprationnel externe pour rcuprer la tension du signal alors que cet AOP est intgr au circuit dans le deuxime cas (avec une diffrence de prix).

Le bus de donnes en entre. Les donnes doivent tre synchrones avec lhorloge.

Les lignes dalimentation des parties analogique et numrique doivent tre spares et la tension de rfrence et AVCC doivent tre dpourvues de bruit. Il est prfrable de se reporter la notice du constructeur pour raliser le circuit imprim autour du convertisseur si la frquence dchantillonnage est suprieure au MHz. La consquence dun cblage impropre du CAN est une diminution notable du SNR, diminution dautant plus grande que la frquence dchantillonnage est leve. Cette diminution est toutefois beaucoup moins sensible que pour un CAN.
6.3 Familles de CAN

6.3.1 Gnralits

Parmi tous les fabricants de convertisseurs gnralistes comme Burr-Brown, National Semiconductor, Maxim et les autres, Analog Devices est celui qui possde le catalogue le plus fourni. Mme si certains fabricants spcialiss peuvent tre plus performants dans un domaine particulier (par exemple Philips ou Brooktree pour la vido), cette socit est la pointe de la technique dans quasiment tous les domaines. Cest pourquoi nous nous servirons de ses circuits comme exemples de CNA et de CAN.

On trouve chez Analog Devices une trs grande gamme de CAN allant de 6 24 bits et de quelques chantillons par seconde (SPS : Samples Per Second) 150 MSPS (la frquence de conversion est faible quand la rsolution est leve). Certains CAN contiennent plusieurs convertisseurs ou encore un seul convertisseur associ un multiplexeur analogique afin de raliser un systme dacquisition multi-voies. Dautres paramtres de choix sont importants, comme le nombre de tensions ncessaires pour alimenter le botier ainsi que la ncessit de 286

fournir une tension de rfrence externe. Le tableau suivant donne quelques exemples reprsentatifs de CAN :

Rfrence Nombre Alimentation de bits AD7821 AD7870 AD7710 AD9066 AD9002 AD7828 8 12 24 6 8 8 5 V, 5 mA

Temps de conversion Vref (ou frquence) 660 ns 100 KSPS 20 ms 60 MSPS 150 MSPS 1 MSPS interne non oui oui oui non non

divers

Sans E/B

5 V, 13 mA 5 V, 13 mA
5 V, 80 mA -5.2 V, 145 mA 5 V, 20 mA

Sigma-delta, 2 voies double CAN ECL 8 voies

Voyons maintenant les principales techniques utilises pour effectuer la conversion analogique/numrique. Vous noterez que lchantillonneur-bloqueur lentre du convertisseur nest pas toujours reprsent car il nest dailleurs pas obligatoirement prsent.
6.3.2 Convertisseurs rampe

La famille des convertisseurs rampe est parmi les plus anciennes et tait utilise pour les mesures prcises de signaux variant trs lentement. Elle a permis datteindre une rsolution de 20 bits mais a t supplante par la famille des convertisseurs sigma-delta dont ltude sort du domaine de ce cours. Son principe demeure toutefois intressant tudier mais ne prsente plus aujourdhui quun intrt historique.

Le convertisseur simple rampe est la premire version de cette architecture. La tension convertir Ex est compare une rampe de tension Vr de pente connue. Quand les deux sont gales, un comparateur stoppe un compteur qui avait dmarr au dbut de la conversion. Connaissant le temps coul t1 et la pente, on peut en dduire la valeur de la tension dentre.

287

sortie numrique Ex comparateur compteur Vr Ex gnrateur de rampe RC t t1


RAZ

Vr horloge

RAZ

horloge dchantillonnage

La prcision de ce montage dpend principalement de la prcision de la pente, cest--dire de celle du gnrateur de rampe. Le convertisseur double rampe permet de sen affranchir.

Durant la premire partie de la conversion double rampe, la tension Ex est intgre pendant un temps constant t0. La tension intgre Vs croit linairement avec le temps. La seconde partie va consister faire diminuer Vs avec une pente constante S jusqu son retour 0, ce qui prend un temps t1. Connaissant t0, t1 et S, on en dduit la tension dentre Ex.

Vs pente fixe S

t temps fixe t0 t1

Comme cest le mme intgrateur qui sert pour les deux phases, ses lments RC ninterviennent plus dans le calcul. Dautres modles plus compliqus permettent damliorer encore la prcision de la conversion (modle triple rampe et quadruple rampe).
6.3.3 Convertisseurs approximations successives

Cette mthode de conversion est base sur la gnration de valeurs numriques qui sont compares la tension analogique convertir de faon encadrer de plus en plus finement le rsultat final (mthode par dichotomie). Pour effectuer la comparaison, il est ncessaire

288

dutiliser un convertisseur numrique/analogique dont les caractristiques ne doivent pas introduire de non-linarits qui provoqueraient des erreurs dans le rsultat.

Soit B = bN-1, bN-2, b1, b0, la sortie numrique. La conversion commence en mettant 1 le MSB et 0 les autres bits de B. Cette valeur numrique 10000 est ensuite convertie en analogique pour donner Vana, puis elle est compare Ex. Si Ex est infrieure Vana, on remet le MSB 0 sinon on le garde 1. Il faut ensuite traiter successivement les autres bits de poids infrieur (mise 1, puis valuation). La conversion est finie quand le LSB a t trait.

horloge comparateur Ex Registre B : sortie numrique convertisseur numrique/analogique

Vana

Prenons lexemple dun convertisseur 4 bits dont la plage dentre est gale [0, 1 V]. La rsolution est donc de 62.5 mV. Le tableau suivant dcrit les diffrents cycles de la conversion dune tension Ex = 0.7 V.

cycle 1 2 3 4

B 1000 1100 1010 1011

Vana [V] 0.5 0.75 0.625 0.6875

> Ex non oui non non

dcision bit reste 1 bit mis 0 bit reste 1 bit reste 1

Il y a calcul dun bit supplmentaire chaque cycle, pour arriver au rsultat final : 1011. Ce type de convertisseur est lent mais peu coteux. Son implmentation en CMOS fait appel un la redistribution des charges sur un rseau de capacits (voir : exercice 6.5).

289

LAD676 de chez Analog Devices est un exemple de convertisseur 16 bits approximations successives (montage redistribution de charges avec E/B intgr) ralis en technologie BICMOS. Son diagramme de blocs est le suivant :

Aliment en 5 V et 12 V, il consomme typiquement 360 mW. Sa tension de rfrence externe peut varier entre 5 et 10 V et il dispose dun systme dautocalibration interne. Il est disponible en botier DIP 28 broches. Ses caractristiques principales (typiques) sont les suivantes (FSR : Full Scale Range) :

paramtre rsolution frquence de conversion erreur de dcalage erreur de gain non-linarit diffrentielle non-linarit intgrale temps dtablissement temps douverture distorsion harmonique totale THD rapport signal bruit SNR

valeur 16 bits 100 KSPS 0.005 %FSR 0.005 %FSR le CAN est monotone

1 LSB
2 s 6 ns - 96 dB 89 dB

Il faut encore noter que, du fait de sa structure, il faut autant de coups dhorloges que de bits de rsolution entre lacquisition de lchantillon et sa sortie numrique, cest--dire 16 cycles pour ce circuit. 290

6.3.4 Convertisseurs algorithmiques

Cest la mthode de conversion la plus utilise en CMOS car elle est particulirement conomique. Le principe du convertisseur algorithmique recirculation est dappliquer sur la tension convertir Ex une suite doprations rptitives (lalgorithme) pour effectuer la conversion. Dans sa version la plus simple, la conversion se fera bit par bit en comparant Ex avec la tension de rfrence Vref. Selon le signe du rsultat, le rsidu est calcul en soustrayant ou non Vref/2. Ce rsidu est ensuite considr comme une nouvelle tension convertir et lopration recommence. Le schma suivant montre le schma de principe de ce convertisseur :

horloge

Ex Ve

E/B Vref 2

Vrsidu

2.Vrsidu

comparateur b

Vref 2

Les tapes suivantes sont ncessaires pour assurer une conversion : 1. Acquisition de lchantillonneur/bloqueur, Ve = Ex. 2. Si Ve > Vref/2, alors b = 1 sinon b = 0. 3. Si b = 1, alors Vrsidu = Ve Vref / 2, sinon Vrsidu = Ve. 4. Acquisition de lchantillonneur/bloqueur, Ve = 2.Vrsidu. On reprend ltape 2.
291

Prenons lexemple dun convertisseur 4 bits avec Vref = 2 V et Ex = 0.6 V. Les quatre cycles suivants sont obtenus :

1 2 3 4

Ve = 0.6 V Ve = 1.2 V Ve = 0.4 V Ve = 0.8 V

< Vref / 2 > Vref / 2 < Vref / 2 < Vref / 2

B3 = 0
B

Vrsidu = 0.6 V Vrsidu = 0.2 V Vrsidu = 0.4 V Vrsidu = 0.8 V

B2 = 1
B

B1 = 0
B

B0 = 0
B

Il est possible dutiliser ce principe pour effectuer la conversion de P bits chaque cycle au lieu dun seul bit. Dans ce cas, il faut remplacer le comparateur par un CAN P bits et il faut utiliser un CNA P bits pour calculer le rsidu. Il faut galement remplacer la multiplication par 2 du rsidu par une multiplication par 2P.

La vitesse de la conversion de cette architecture est limite par le fait quil faut N cycles pour arriver au rsultat. Dans le montage pipeline, il ny a pas de rebouclage de 2.Vrsidu sur Ve au niveau du CAN lmentaire. Le schma suivant montre la nouvelle structure dun tage sur 1 bit.

horloge

CAN +

Ve

E/B Vref 2

Vrsidu

2.Vrsidu

Vref 2

b Le CAN algorithmique pipeline est constitu de N tages, N tant le nombre de bits de rsolution (4 bits sur le schma suivant). Lorsque le deuxime tage effectue son calcul sur le rsidu Vr1 du premier tage, celui-ci peut commencer calculer une nouvelle valeur. Une fois la conversion du premier symbole S1 commence, il faut attendre 4 cycles (le temps que 292

la valeur traverse les 4 tages) pour obtenir la valeur numrique, mais la seconde valeur numrique (correspondant au deuxime symbole S2) arrive pendant le cycle suivant (une fois que le pipeline est amorc).

Ex

E/B

CAN Vr1 b3 S4

E/B

CAN Vr2 E/B b2

CAN Vr3 E/B b1

CAN b0

S3 S2 S1 H

S3 S2 S1 H S2 S1 H S1

registres Sortie numrique Supposons que lon envoie la squence de symboles suivante lentre du montage : S1, S2, S3, S4, S5. on obtient la squence de remplissage du pipeline suivante :

cycle 1 2 3 4 5

tage 1 S1 S2 S3 S4 S5

tage 2 X S1 S2 S3 S4

tage 3 X X S1 S2 S3

tage 4 X X X S1 S2

Chaque tage traitant un symbole fournit le bit correspondant son rang. A un instant donn, il nest donc pas possible de prendre directement les sorties de chaque tage pour constituer la valeur binaire correspondant un symbole. Pour remettre les 4 bits en phase, il faut insrer des registres dcalage dont la taille dcrot avec le rang de ltage. Les retards apports par ces registres correspondent exactement aux retards des tages de conversion suivants. Comme pour le convertisseur recirculation, il est possible de traiter plusieurs bits par tage.
293

LAD876 est un exemple de convertisseur 10 bits algorithmique structure pipeline ralis en technologie CMOS. Son diagramme de blocs est le suivant :

Aliment en 5 V, il consomme typiquement 160 mW. Sa tension de rfrence externe est de lordre de 4 V. Il est disponible en botier SOIC et SSOP 28 broches ainsi quen TQFP 48 broches. Ses entres/sorties numriques sont compatibles 5 V et 3.3 V, les sorties pouvant tre mises ltat haute impdance. Ses caractristiques principales (typiques) sont les suivantes :

paramtre rsolution frquence de conversion erreur de dcalage erreur de gain non-linarit diffrentielle non-linarit intgrale temps douverture THD SNR nombre effectif de bits ENOB dynamique dentre SFDR

valeur 10 bits 20 MSPS 0.1 %FSR 0.1 %FSR

0.1 LSB 0.3 LSB


4 ns - 60 dB 47 dB 7.5 bits -65 dB

Il faut encore noter que, du fait de sa structure en pipeline, il y a un temps de latence de 3.5 priodes dhorloge entre lacquisition de lchantillon et sa sortie numrique. Mais contrairement lAD676, lAD876 sort une nouvelle donne chaque coup dhorloge.

294

6.3.5 Convertisseurs flash

Le principe de ce convertisseur (structure flash) consiste comparer la tension dentre Ex n tensions de rfrence simultanment. La figure suivante donne lexemple dun convertisseur 3 bits. 8 nombres diffrents peuvent tre reprsents laide de 7 comparateurs. Les 7 tensions de rfrence sont ralises laide dun diviseur rsistif.

Vref = 8 V 3R/2 Ex = 3 V 13/2 V R 11/2 V R 9/2 V R 7/2 V R 5/2 V R 3/2 V R 1/2 V R/2 1 1 1 0 dcodeur B : sortie numrique 0 0 comparateurs 0

295

Avec Ex = 3 V et Vref = 8 V, les trois premiers comparateurs sont 1 alors que les autres sont 0. Le dcodeur transforme la position du bit de poids le plus lev mis 1 en un code binaire (ici, le code 3). Cette structure de convertisseur est la plus rapide, elle atteint facilement plusieurs centaines de MSPS. Limplantation pose de nombreux problmes du fait du grand nombre de comparateurs (2N-1 pour un mot de N bits). Sa rsolution dpasse donc rarement 8 bits et sa consommation est leve. Il nest gnralement pas ncessaire de lassocier un chantillonneur/bloqueur.

Pour 8 bits, il faut 255 comparateurs monts en parallle. Pour toute augmentation de la rsolution dun bit, le nombre de comparateurs double, ce qui amne rapidement des surfaces de silicium trop grandes. La structure semi-flash (subranging) cherche garder la rapidit de la structure flash tout en rduisant le nombre de comparateurs. Lunit de conversion est divise en deux sous units flash travaillant en srie. La premire unit va calculer les bits de poids forts qui sont ensuite convertis en analogique puis soustraits la tension convertir pour obtenir le rsidu de cette conversion. Ce rsidu est ensuite converti dans le deuxime tage flash pour gnrer les bits de poids faibles. Le principe de base est donc en fait celui de la conversion algorithmique, mais appliqu sur un plus grand nombre de bits. Par rapport la structure flash, il faut un chantillonneur/bloqueur (E/B) et un CNA de plus, mais le nombre de comparateurs est fortement diminu. Prenons lexemple dun CAN 12 bits semi-flash :

Ex

E/B

Flash 4 bits

Bits 11 8

CNA 4 bits

Flash 8 bits comparateur

Bits 7 0

Il ne contient plus que 24 - 1 + 28 - 1 = 260 comparateurs au lieu de 212 - 1 = 4095 avec une structure flash.
296

LAD9002 est un exemple de convertisseur 8 bits flash ralis en technologie bipolaire. Son diagramme de blocs est le suivant :

Aliment en - 5.2 V, il consomme typiquement 750 mW. Sa tension de rfrence externe est comprise entre - 3.5 et + 0.1 V et il est disponible en botier DIP et PLCC 28 broches. Ses entres/sorties numriques sont compatibles ECL. Ses caractristiques principales (typiques) sont les suivantes :

paramtre rsolution frquence de conversion erreur de dcalage non-linarit diffrentielle non-linarit intgrale temps douverture SNR ENOB

valeur 8 bits 150 MSPS 8 mV 0.6 LSB 0.6 LSB 1.3 ns 47.6 dB 7.6 bits

Il faut encore noter quil ny a plus quun retard dune priode dhorloge entre lacquisition de lchantillon et sa sortie numrique. 297

6.4

Familles de CNA

6.4.1 Gnralits

On trouve chez Analog Devices une trs grande gamme de CNA allant de 8 18 bits et de quelques centaines dchantillons par seconde 400 MSPS (la frquence de conversion est faible quand la rsolution est leve). Les CNA sont disponibles en sortie courant (ncessitant un AOP externe) ou en sortie tension et contiennent jusqu 8 convertisseurs. Certains modles incorporent une fonction de multiplication. Il suffit dentrer une tension analogique sur Vref et la tension de sortie du CNA devient gale :
Nombre binaire Vsortie = Vref. 2N

On injecte par exemple une tension sinusodale damplitude crte crte 4 V sur lentre Vref dun convertisseur 8 bits. On obtient en sortie la mme tension sinusodale dont lamplitude varie entre 0 et 4. 255 1 Vcc par pas de 4. Vcc selon le nombre binaire appliqu sur le 256 256

CNA. Dautres paramtres de choix sont importants, comme le nombre de tensions ncessaires pour alimenter le botier ainsi que la ncessit de fournir une tension de rfrence externe. Le tableau suivant donne quelques exemples reprsentatifs de CNA :

Rfrence # bits AD7537 AD760 AD768 AD9720 AD8600 12

Alimentation 12/15 V, 2 mA

Tconversion sortie Vref ou Fconversion I/V interne 1.5 s 10 s 30 MSPS 400 MSPS 2 s I V I I V non oui oui oui non

divers 2 CNA multiplieurs auto-calibration, srie-// multiplieur ECL 16 CNA multiplieurs

16/18 15 V, 5 V, 600 mW 16 10 8

5 V, 465 mW
-5.2 V, 210 mA 5 V, 35 mA

298

Voyons maintenant les principales techniques utilises pour effectuer la conversion numrique/analogique.
6.4.2 Convertisseurs base de rsistances 6.4.2.1 CNA rseau de rsistances pondres

La structure rseau de rsistances pondres est des plus simples. Le rseau ralise une conversion tension/courant de la tension de rfrence. Seuls les courants des branches dont les bits de commande sont 1 sont ensuite somms, le total tant reconverti en tension par lAOP.

2R 4R 8R

bN-1 bN-2 bN-3 R

Vref

2NR

b0
AOP +

Vs

La sortie vaut donc :

1 1 1 Vs = R Vref .b N 1 + .b N 2 + ... + N .b 0 4R 2 R 2R = b b Vref b N 1 + N 2 + ... + N0-1 2 2 2

Cette structure de convertisseur ncessite des rapports de rsistances importants (de R 2N.R pour une conversion sur N bits). Or, plus les rapports augmentent et plus la prcision entre lments est difficile obtenir.

299

6.4.2.2

CNA rseau de rsistances R-2R

Il est donc plus intressant, du point de vue de la prcision, de nutiliser que des petits rapports avec un rseau de rsistances R-2R (voir : exercice 6.6). Le montage sur 4 bits ainsi obtenu est le suivant :

2R

2R

2R

2R

2R

b3 Vref

b3

b2

b2

b1

b1

b0

b0

Vs

Le rseau est construit de manire ce que, quelques soient les valeurs des bits, le courant circulant dans les rsistances soit toujours le mme. Si un bit est 1, le courant est dirig sur lentre de lAOP (qui est une masse virtuelle), sinon il va sur la masse. De plus, entre chaque nud du rseau et la masse, il y a une impdance quivalente R. Le courant circulant dans le rseau se partage donc en deux en chaque nud et on obtient finalement :

1 1 1 1 Vs = R Vref .b 3 + .b 2 + .b1 + .b 0 4R 8R 16R 2R = Vref 2 b b b b3 + 2 + 1 + 0 2 4 8

LAD7524 est un exemple de convertisseur numrique/analogique 8 bits rseau de rsistances R-2R ralis en technologie CMOS. Son diagramme de blocs est le suivant :

300

Il consomme de 5 30 mW selon la tension dalimentation comprise entre 0 et 17 V. Sa tension de rfrence externe est comprise entre 25 V et il est disponible en botier DIP et SOIC 16 broches ou PLCC 20 broches. Le bus de donnes et ses signaux de contrle sont conus pour tre interfac avec un microprocesseur. Le chronogramme dcriture est le suivant :

Ses caractristiques principales (typiques en 15 V) sont :

paramtre rsolution Prcision relative erreur de gain non-linarit Temps dtablissement

valeur 8 bits 1/2 LSB 1.25 LSB 1/2 LSB (monotone) 250 ns

301

6.4.2.3

CNA chelle de rsistances

Une dernire architecture de CNA base de rsistances utilise un principe identique celui de CAN flash : une chelle de rsistances qui sert gnrer toutes les valeurs possibles de la tension de sortie. La tension correspondant la valeur de lchantillon est envoy sur la sortie par lintermdiaire dun multiplexeur form de commutateurs analogiques commands par la valeur numrique.

bN-1 bN-2 Vref dcodage R

b0 2N signaux de commande
2N-1.Vref 2N 4.Vref 2N

3.Vref 2N 2.Vref 2N Vref 2N AOP +

Vs

R
0

Ce montage, pour une prcision de N bits, utilise 2N-1 rsistances qui doivent tre implantes de manire minimiser la dispersion des valeurs, ce qui limite la rsolution des valeurs faibles. En pratique, on trouve ce type de montage associ un autre CNA pour atteindre des rsolutions plus leves comme dans lexemple suivant.

LAD7846 est un convertisseur numrique/analogique 16 bits architecture segmente ralis en technologie CMOS. Les 4 bits de poids fort sont traits par deux convertisseurs chelle de rsistances mis en parallle (sortie A1 et A2) alors que les 12 bits de poids faible sont traits par un CNA 12 bits R-2R. Son diagramme de blocs est le suivant :

302

Il est aliment en 15 V et 5 V avec une consommation typique de 100 mW. LAOP de sortie est intgr et permet une sortie analogique unipolaire (0 5 V 0 10 V) ou bipolaire (5 V 5 V -10 10 V) avec possibilit de multiplication. Ses tensions de rfrence externes sont comprises entre 10 V et il est disponible en botier DIP et PLCC 28 broches. Le bus de donnes et ses signaux de contrle sont conus pour tre interfac avec un microprocesseur. Le chronogramme dcriture est le suivant :

Ses caractristiques principales (typique avec sortie bipolaire) sont:

paramtre rsolution Prcision relative erreur de dcalage erreur de gain non-linarit diffrentielle Temps dtablissement 303

valeur 16 bits 6 LSB 6 LSB 6 LSB 1 LSB (monotone) 7 s

6.4.3 Convertisseurs courants pondrs

La vitesse de la conversion est limite par le temps dtablissement de lAOP de sortie mont en sommateur. Pour augmenter cette vitesse, on peut remplacer les rsistances par des sources de courant pondres dont la valeur est fonction de Vref et du poids de la source. Le temps de conversion ne dpend plus alors que du temps de commutation des sources. Deux solutions sont possibles pour les sources: On utilise des sources de courant pondres de taille croissante avec le poids des bits. Linconvnient est alors la faible prcision due aux dispersions entre les sources de valeurs diffrentes. On utilise des sources identiques dune valeur correspondant un LSB, ces sources tant ensuite sommes pour atteindre la valeur requise. La prcision est bien meilleure avec comme inconvnient un grand nombre de sources implanter (2N-1) et de nombreux signaux de commande.

Une combinaison des deux solutions peut tre retenue pour raliser un convertisseur 8 bits (Is est proportionnel Vref qui nest pas reprsente sur le schma). Cette solution utilise 63 sources de courants identiques pour la conversion des 6 bits de poids fort et deux sources de courant pondres pour les deux bits de poids faible.
VCC

Vs

63 sources identiques (6 MSB) b7,, b2 courant LSB

Is 26

Is 27

Is 28

b1 , b0

304

LAD768 est un CNA 16 bits ralis en technologie BICMOS architecture segmente base sur des sources de courant commutes. Son diagramme de blocs est le suivant :

Il est aliment en 5 V avec une consommation typique de 465 mW. La sortie se fait en courant avec possibilit de multiplication. Sa tension de rfrence interne est gale 2.5 V et il est disponible en botier SOIC 28 broches. Le chronogramme dcriture est le suivant :

Ses caractristiques principales (typique) sont:

paramtre rsolution erreur de dcalage erreur de gain Temps dtablissement THD SFDR

valeur 16 bits 0.2 % FSR 1 % FSR 25 ns -66 dB 73 dB

305

6.5

Exercices

Exercice 6.1 On utilise dans cet exercice le CAN 3 bits vu au 7.1.3. La tension de rfrence est gale 1 V. On cherche convertir le signal triangulaire suivant :
amplitude A

0 0 T

La priode T est gale 14 fois la priode dchantillonnage. 1. Quelle est la frquence dchantillonnage minimale ? 2. Calculer le pas de quantification . 3. A = 7 Vref. Dessiner le signal quantifi ainsi que lerreur de quantification. 8

4. Calculer le rapport signal sur bruit de quantification (SNR). 5. A = 2.Vref. Dessiner le signal quantifi. Conclusion ? 6. A = 1 Vref. Dessiner le signal quantifi ainsi que lerreur de quantification. 8

7. Calculer le SNR. Quel est le nombre de bits effectif de la conversion dans ce cas ?

Exercice 6.2 Pour des convertisseurs de rsolution 6, 8, 12, 16 et 24 bits, rappeler la dfinition et calculer : 1. Le rapport signal sur bruit de quantification. 2. La dynamique. 3. La rsolution en pourcentage de la pleine chelle.

Exercice 6.3 On souhaite raliser un systme permettant de retarder un signal analogique laide dun CNA, dun CAN et de registres dcalage. 1. Proposer un montage permettant de raliser cette fonction. 2. Ce montage est-il synchrone ? 3. Comment peut-on rgler la valeur du retard ?

306

Exercice 6.4 On se propose de raliser un gnrateur de rampes (y=a.t pour 0 t T) de priode T, de frquence et damplitude variables, laide dun CNA et dun compteur. 1. Proposer un montage permettant de raliser cette fonction. 2. Quelles modifications faudrait-il apporter au montage prcdent pour gnrer un signal sinusodal ?

Exercice 6.5 La figure suivante reprsente un CAN redistribution de charges ayant 5 bits de rsolution.

S2 Vx C 16
+

comparateur

C b4 b4 b3

C 2 b3 b2

C 4 b2 b1

C 8 b1 b0

C 16 b0 S3

Vs

S3

S1 Ex Vref

Quand le bit de commande vaut 1, linterrupteur correspondant est ferm. Tous les lments sont supposs parfaits (notamment le courant dentre du comparateur est nul). On travaille avec Vref = 1 V et Ex = 0.8 V. 1. On dsire charger tous les condensateurs Ex. Donner la position des interrupteurs du montage. 2. Quelle est alors la valeur de la charge totale stocke dans les condensateurs ? 3. On inverse tous les interrupteurs. Quelle est la nouvelle valeur de la charge totale stocke ? Combien vaut Vx ? 4. b4 passe 1. Calculer la charge totale du systme et en dduire Vx. 5. Si Vx > 0, alors b4 = 0, sinon b4 = 1. Que vaut b4 dans cet exemple ?

307

6. b4 reste dans la position dtermine prcdemment et b3 passe 1. Calculer la charge totale du systme et en dduire Vx. 7. Si Vx > 0, alors b3 = 0, sinon b3 = 1. Que vaut b3 dans cet exemple ? 8. Dduire du fonctionnement prcdent la valeur des bits b2, b1, b0.

Exercice 6.6 La figure suivante reprsente un CNA rseau R-2R ayant 4 bits de rsolution.

CNA Vref Itot A R B R C R D 2R

2R IA b3 b3 IB b2

2R IC b2 b1

2R ID b1 b0

2R

b0

RFB IOUT1

IS

IOUT2 +

AOP

Vs

Quand le bit de commande vaut 1, linterrupteur correspondant est ferm. Tous les lments sont supposs parfaits (notamment le courant dentre de lAOP est nul). On travaille avec Vref = 10 V et B = 1011. 1. Calculer la rsistance quivalente droite du point D par rapport la masse. Mme question pour les points C, B et A. 2. Calculer Itot et IA. En dduire le potentiel au point B. 3. Calculer IB. En dduire le potentiel au point C.
B

4. Calculer IC. En dduire le potentiel au point D et ID. 5. Donner la formule reliant Is et Vref, b3, b2, b1 et b0. En dduire Vs. 6. On passe Vref -10 V. Quelle est la nouvelle valeur de Vs. 7. On applique sur Vref un signal sinusodal damplitude crte 5 V. Quobtient-on alors sur Vs. Mme question avec B = 0001 et B = 1111.

308

8. On applique sur Vref une tension continue gale - 5 V, on inverse les bit b3 et b 3 et on

modifie lamplificateur de sortie de la manire suivante :

R R Is

-Vref 2 RFB IOUT1 IOUT2 +


AOP

Vs

Calculer la nouvelle formule de Vs. Combien vaut Vs pour B = 0000, 0001, 0111, 1111, 1001 et 1000. Conclusion ?

Exercice 6.7 Soit le circuit AD676 donc la documentation se trouve en annexe page A-47. 1. Quelles sont les caractristiques gnrales de ce circuit ? 2. Quelles sont ses caractristiques statiques ? 3. Quelles sont ses caractristiques dynamiques ? 4. Y-a-t-il dautres informations intressantes dans la documentation ?

Exercice 6.8 Soit le circuit DAC8562 donc la documentation se trouve en annexe page A-63. 1. Quelles sont les caractristiques gnrales de ce circuit ? 2. Quelles sont ses caractristiques statiques ? 3. Quelles sont ses caractristiques dynamiques ? 4. Y-a-t-il dautres informations intressantes dans la documentation ?

309

310

7 Corrigs succincts
7.1 Corrigs chapitre 1

Exercice 1.1 1. Voir cours. 2. Y = A.B.C.D,


Y = A + B + C + D , Y = A+B+C+D, Y = A.B.C.D , Y = A.B.C. D .

3. F1 = A + B , F2 = A.C + B.C , F3 = A.B + A.B , F4 = 1 . 4. voir cours. 5. voir cours. 6. A.B + A.B , A.B.C + B.C.D + A.C.D , A B C . 7. S = A.B . 8. A B C D F

Exercice 1.2 1. F = S1 .A.B + S1 .S 0 .A . B + C.S1 .A.B.A . B .S 0 . 2. C 0 0 0 0 1 1 1 1 S1 S0 F 0 0 0 0 1 0 1 0 A.B 1 1 A.B+ A.B 0 0 A.B 0 1 A.B + A.B 1 0 A.B 1 1 A.B+ A.B

3. F=A.B si S1S0 = 10, F= A.B si CS1S0 = 100, F= A B si CS1S0 = 101, F= A B si S1S0 = 11.

311

Exercice 1.3 1. D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2. C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1

D C B A Exercice 1.4 1. Y1 = A , Y2 = A + B , Y3 = 1 . Exercice 1.5


Y1 = B.C.A. B , implantation avec 5 NAND 2 entres. Y1 = A + B + C + B , implantation avec 5 NOR 2 entres.

Y2 = A.B.C , implantation avec 3 NAND 2 entres.


Y2 = A + B + C , implantation avec 5 NOR 2 entres.

Y3 = B.D. B.D , implantation avec 5 NAND 2 entres.


Y3 = B + D + B + D , implantation avec 6 NOR 2 entres.

312

Y4 = B.A.D , implantation avec 3 NAND 2 entres.


Y4 = B + A + D , implantation avec 5 NOR 2 entres.

Y5 = A.C.B.C , implantation avec 6 NAND 2 entres.


Y5 = A + C + B + C , implantation avec 5 NOR 2 entres.

Y6 = B.C , implantation avec 4 NAND 2 entres.


Y6 = B + C , implantation avec 1 NOR 2 entres.

Y7 = B.A.C , implantation avec 5 NAND 2 entres.


Y7 = B + A + C , implantation avec 3 NOR 2 entres.

Exercice 1.6 1. 4 bits : 0 15, -8 7 ; 8 bits : 0 255, -128 127 ; 16 bits : 0 65535, -32768 32767 ; 32 bits : 0 4294967295, -2147483648 2147483647 ; N bits : 0 2N-1, -2N-1
2N-1-1.

2. (1101101)2=(109)10. 3. (19)10 = (10011)2, (45)10 = (101101)2, (63)10 = (111111)2. 4. (1CA57)16. 5. (10A4)16 = (4260)10 = (1000010100100)2, (CF8E)16 = (53134)10 = (1100111110001110)2, (9742)16 = (38722)10 = (1001011101000010)2. Exercice 1.7 1. Dcimal 0 1 2 3 4 5 6 7 C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Y0 0 1 1 1 1 1 1 1 Y1 1 0 1 1 1 1 1 1 Y2 1 1 0 1 1 1 1 1 Y3 1 1 1 0 1 1 1 1 Y4 1 1 1 1 0 1 1 1 Y5 1 1 1 1 1 0 1 1 Y6 1 1 1 1 1 1 0 1 Y7 1 1 1 1 1 1 1 0

313

2.

Y0 = C + B + A = C . B.A ,
Y3 = C + B + A = C .B.A ,

Y1 = C + B + A = C . B .A , Y4 = C + B + A = C. B .A ,

Y2 = C + B + A = C .B. A ,

Y5 = C + B + A = C.B .A ,

Y6 = C + B + A = C.B.A , Y7 = C + B + A = C.B.A .

3. A B C

C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

4.
A A B B C C Y0 Y7

V Exercice 1.8 1.

314

0 1 2 3 4 5 6 7 8 9 2.

b4 0 1 1 0 1 0 0 1 0 0

b3 0 1 0 1 0 1 0 0 1 0

b2 0 0 1 1 0 0 1 0 0 1

b1 1 0 0 0 1 1 1 0 0 0

b0 1 0 0 0 0 0 0 1 1 1

a3 0 0 0 0 0 0 0 0 1 1

a2 0 0 0 0 1 1 1 1 0 0

a1 0 0 1 1 0 0 1 1 0 0

a0 0 1 0 1 0 1 0 1 0 1

3. b0 = a3 + a2.a1.a0 + a2.a1.a0 , b1 = a1.a2 + a3.a1.a0 + a2.a1.a0 ,


b2 = a1.a0 + a3.a0 + a2.a1.a0 , b3 = a3.a0 + a3.a1.a0 + a2.a1.a0 ,

b4 = a3.a2.a1.a0 + a 2.a1.a0 + a2.a1.a0 + a2.a1.a0 .

4. b0 = a3.a2.a1.a0.a2.a1.a0 implantation avec 4 NAND 2 entres et 3 NAND 3 entres. Exercice 1.9 1. S = A B , C=A.B.

A B

S C

2.

S i = C i 1 A i B i , C i = C i 1 .(A i B i ) + A i .B i .

Ci-1 Ai Bi Ci Si

3. D = A B , E = A.B .

315

A B

S E

4. D i = E i 1 A i B i , E i = E i 1 .( A i Bi ) + A i .Bi .

Ei-1 Ai Bi Ei Di

5. K = 0, addition ; K = 1, soustraction.
Ri-1 Ai Bi K SDi

Ri

Exercice 1.10 1. Cest un comparateur dgalit de deux nombres sur 4 bits. S = 1 si a3 = b3 et a2 = b2 et a1 = b1 et a0 = b0.

Exercice 1.11 1. Si = E.a i .b i , E i = E.(Si + I i ) , I i = E.a i .bi . 2.


316

1 b3 a3 E S3 I3 E3 S2 I2 E2 S1 I1 E1 A>B

b2 a2

A<B

b1 a1

A=B

Exercice 1.12 1. S = (A B).(E (C + D)) .

Exercice 1.13 1.
A0 A1 A2 20 2 22
1

E7

E0

A0 A1 A2

20 2 22
1

E7

E0

A0 A1 A2

20 2 22
1

E7

E0

A0 A1 A2

20 2 22
1

E7

E0

A3 A4

20 2
1

E3

E2

E1

E0

Exercice 1.14 1. e 0 0 0 p 0 0 0 m 0 0 1 c 0 1 0 317 E 0 0 0 P 0 0 0 M 0 0 0 C 0 0 0

0 0 0 0 0 1 1 1 1 1 1 1 1

0 1 1 1 1 0 0 0 0 1 1 1 1

1 0 0 1 1 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 1 0 1 0 0 0 1 1 1 0

0 1 0 0 1 0 0 0 0 1 0 0 1

0 0 0 1 0 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 0 0 1 0 0

2. M = p.m.c , C = p.m.c , P = p.m.c + p.m.c , E = e.m.c + C + M . 3. A0 = c, A1 = m, A2 = p. C = 5, M = 6, P = 4 + 7, E = 5 + 6 + e.m.c . 4. A0 = m, A1 = c. M : I0 = 0, I1 = p, I2 = 0, I3 = 0. C : I0 = 0, I1 = 0, I2 = p, I3 = 0. P : I0 = p, I1 = 0, I2 = 0, I3 = p. E : I0 = e, I1 = p, I2 = p, I3 = 0. 5. A0 = c, A1 = m, A2 = p, A3 = e, A4 = 0. D0 = E, D1 = M, D2 = C, D3 = P. Contenu PROM = table de vrit. 6. Ralisation avec des NAND des quations M = p.m. c , C = p.m.c , P = p.m.c + p.m.c ,

E = e.m.c + C + M .
Exercice 1.15 1. nb 0 1 2 3 4 5 6 7 E D C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 S 0 0 0 1 0 0 1 0 T 0 0 0 0 0 1 0 0 U 0 0 0 0 0 0 0 1

318

8 9 10 11 12 13 14 15 16 17 18 19 20

0 0 0 0 0 0 0 0 1 1 1 1 1

1 1 1 1 1 1 1 1 0 0 0 0 0

0 0 0 0 1 1 1 1 0 0 0 0 1

0 0 1 1 0 0 1 1 0 0 1 1 0

0 1 0 1 0 1 0 1 0 1 0 1 0

0 1 0 0 1 0 0 1 0 0 1 0 0

0 0 1 0 0 0 0 1 0 0 0 0 1

0 0 0 0 0 0 1 0 0 0 0 0 0

2. S = A.B.E + A.B.C.D.E + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D ,

T = A.B.C.D + A.B.C.D + A.B.C.D + C.E , U = A.B.C.D + A.B.C.D .


3. Voir : thorme de De Morgan + formules prcdentes. 4. A0 = A, A1 = B, A2 = C, A3 = D.

I0 S T U 0 0 0

I1 0 0 0

I2 E 0 0

I3
E

I4 0 E 0

I5 0
E

I6
E

I7 0 0
E

I8 0 0 0

I9
E

I10 0
E

I11 0 0 0

I12
E

I13 0 0 0

I14 0 0
E

I15
E E

0 0

0 0

0 0

0 0

5. A0 = A, A1 = B, A2 = C, A3 = D, A4 = E. D0 = S, D1 = T, D2 = U. Contenu PROM = table de vrit. Exercice 1.16 1. A 0 0 0 0 B 0 0 0 0 C 0 0 1 1 D 0 1 0 1 EQ 1 0 0 0 319 NE 0 1 1 1 LT GT 0 0 1 0 1 0 1 0

0 0 0 0 1 1 1 1 1 1 1 1

1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 0 0 0 1 0 0 0 0 1

1 0 1 1 1 1 0 1 1 1 1 0

0 0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 1 1 0 0 1 1 1 0

2. EQ = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D ,

NE = A.C + A.C + B.D + B.D ,

LT = A.C + A.B.D + B. C.D , GT = A.C + A.B.D + B.C.D .


3. Voir : thorme de De Morgan + formules prcdentes. 4. A0 = C, A1 = B, A2 = A.

I0 EQ NE LT GT
D

I1 0 1 1 0

I2 D
D

I3 0 1 1 0

I4 0 1 0 1

I5
D

I6 0 1 0 1

I7 D
D

D D 0

D D 0

0
D

0
D

5. A0 = D, A1 = C, A2 = B, A3 = A. EQ = (0,5,10,15), NE = (1,2,3,4,6,7,8,9,11,12,13,14), LT = (1,2,3,6,7,11), GT = (4,8,9,12,13,14). 6. A0 = D, A1 = C, A2 = B, A3 = A, A4 = 0. D0 = EQ, D1 = NE, D2 = LT, D3 = GT. Contenu PROM = table de vrit.

Exercice 1.17 temps de propagation = 15 ns.

320

E1 [V]

1,5 100 E2 [V] t [ns]

1,5 100 S [V] t [ns]

100

t [ns]

Exercice 1.18 1.
Vs 5V

0,8

1,6

5V

Ve

2. hystrsis = VT+ - VT- = 0,8 V.

7.2

Corrigs chapitre 2

Exercice 2.1 1.
S rebond 1

321

2.
S rebond 1

3. On a maintenant une bascule SR. 2 1 : pendant le rebond, on passe de mise 0 mmoire S reste 0. 1 2 : pendant le rebond, on passe de mise 1 mmoire S reste 1. Exercice 2.2 1. H A 1 D
D

R S Q+ 0 0 Q

D D

D D D
0 0 Q

0 D D ou 0 si D change D D Q
D

2. bascule D synchrone sur front descendant. Exercice 2.3 1.

CP

D=Q

2. Nand : tP = 15 ns. Bascule : tPHLmax = 40 ns, tsmin = 20 ns, thmin = 5 ns. 3. fmax = 11,1 MHz. Exercice 2.4

322

1. si tPDQA < T/2, alors pas derreur. si T/2 < tPDQA < T, alors erreur (mtastabilit).
CP entre asynchrone QA QB
pas derreur

QC QD

erreur erreur pas derreur

2. t [ns] MTBF Exercice 2.5 1.


H

0 0.001 s

0,5 16,3 s

1 74 h

1,5 138 ans

2 2,25.106 ans

Q0 Q1 Q2 Q3

2. Cest un compteur Johnson. Une seule sortie change chaque coup dhorloge. On peut donc raliser des combinaisons de sorties garanties sans glitches. Autre application, les horloges dcales en phase. Exercice 2.6 1. 323

QC 0 0 0 0 1 1 1 1 2. J = K = T.

QB
B

QA 0 1 0 1 0 1 0 1

QC+ 1 0 0 0 0 X X X

QB+ 0 0 0 1 1 X X X

QA+ 0 0 1 0 1 X X X

0 0 1 1 0 0 1 1

QBQA QC 00 T CT BT A 0 1

01

11

10

100 001 001 011 111 XXX XXX XXX

3. TC = Q B .Q A , TB = Q C + Q B .Q A , TA = Q C + Q B + Q A . 4. Avec des NAND, TC = Q B .Q A , TB = Q C . Q B .Q A , TA = Q C . Q B . Q A . 5.


0 7

6. Seul QB change. TB = Q B .Q A + Q C . Q B + Q A . Q C .
B

Exercice 2.7 1. J A = Q B , KA = QB. JB = KB = QA. JC = KC = QB.


B B B B

324

2.
0 1 7

2 3 6 4 5

3. On connecte 6 sur 0, QB+ change JB = KB = QA+QB.QC.


B B B

Exercice 2.8 1. QC 0 0 0 0 1 1 1 1 QB
B

QA 0 1 0 1 0 1 0 1

QC+ 0 X 0 1 X 1 0 X

QB+ 1 X 1 0 X 1 0 X

QA+ 0 X 1 1 X 0 0 X

0 0 1 1 0 0 1 1

2. J = K = T.

QBQA QC 00 T CT BT A 0

01

11

10

010 XXX 110 001

1 XXX 011 XXX 110

3. Une solution de regroupement possible est : TC = Q A Q C , TB = Q A + Q B + Q C ,

TA = Q C . Q B . Q A + Q B .Q C .
325

4. Ralisation directe avec un XOR, deux OR et deux NAND. 5.


0

3 4 1 7

6. Seul QC change. TC = Q B .Q A + Q A . Q C . Exercice 2.9 1. Registre dcalage droite. 2. Registre dcalage gauche. 3. S0 = 0, dcalage droite. S0 = 1, dcalage gauche.
Qn-1 S0 Dn Qn+1 S0

4. S1 = 0, dcalage. S1 = 1, chargement.
Qn-1 S0 S1 Qn+1 S0 S1 chgt S1 Dn

5. EN = 1, fonctionnement prcdent. EN = 0, Qn = Dn.

326

Qn-1 S0 S1 EN Qn+1 S0 S1 EN chgt S1 EN EN

Dn

Qn

Exercice 2.10 1. fmax = 13,3 MHz.

SD T D

SD

CP CD

CP CD

2. T0 = 1, T1 = Q0, fmax = 13,3 MHz. 3. 3 bits : T0 = 1, T1 = Q0, T2 = Q0.Q1, fmax = 11,1 MHz. 4 bits : T0 = 1, T1 = Q0, T2 = Q0.Q1, T3 = Q0.Q1.Q2, fmax = 9,5 MHz. La taille du AND augmente avec le nombre de bits. On ne peut pas dpasser une taille limite on fait des compteurs 4 bits et on les associe en cascade. 4. On ajoute un signal EN (validation) et un signal RCO (Ripple Carry Output vaut 1 pour Qn = 1111).

327

EN T0 H Q0 T1 H Q1 T2 H Q2 T3 H Q3

RCO

16 bits : fmax = 5,5 MHz, 32 bits : fmax = 4,2 MHz. 5. fmax = 6,1 MHz.
Q0 Q1 Q2 Q3 RCO EN T EN P

EN (vers les bascules)

Exercice 2.11 1.

SD T D Q T D

SD Q

CP CD

CP CD

2. Cest un compteur 4 bits : T0 = 1, T1 = Q0, T2 = Q0.Q1, T3 = Q0.Q1.Q2. La taille du AND augmente avec le nombre de bits. On ne peut pas dpasser une taille limite on fait des compteurs 4 bits et on les associe en cascade. 3. les Dn valent 0 les Qn passent 0 sur le front suivant de lhorloge. 4. D0 = A, D1 = B, D2 = C, D3 = D les Qn changent sur le front suivant de lhorloge. 5. RCO = 0, Tn = 0 Q+n = Qn (effet mmoire). 328

6. On passe du montage 1 au montage 2.


vers les bascules
vers les bascules

1
EN P EN T
EN Qn

RCO

Qn

RCO

16 bits : fmax = 6 MHz, 32 bits : fmax = 4,4 MHz. 7. On distribue paralllement EN P. La fmax est indpendante du nombre de compteurs associs : 6,7 MHz.

7.3

Corrigs chapitre 3

Exercice 3.1 1. IIL et IOH sortant, IIH et IOL rentrant. 2. VOHmin = VIHmin + H VOHmin > VIHmin. VILmax = VOLmax + L VILmax > VOLmax. 3. H = VOHmin - VIHmin = 2,7 - 2 = 0,7 V. L = VILmax - VOLmax = 0,8 - 0,5 = 0,3 V. 4. 20 portes. Exercice 3.2 1. tp (5.25 V, 0 C) = 0,275. tp (4.75 V, 0 C) = 0,315. tp (4.75 V, 0 C) = 0,315. tp (4.75 V, 70 C) = 0,39. t p VCC = -2.5 % par 100 mV.

t p T

= -0.34 % par degr.

tp (4.75 V, 0 C) = 0,315 min. tp (4.75 V, 0 C) = 0,76 max.

t p fabrication

= 145 %.

2. On a : tpmin (5.25 V, 0 C) = 0,275. tptyp (5 V, 25 C) = 0,53. tpmax (4.75 V, 70 C) = 0,985. tpmin x 1,0252,5 x 1,003425 x (1 + 1,45 / 2) = 0,55 tptyp. tpmin x 1,125 x 1,24 x (1 + 1,45) = 0,94 tpmax. Exercice 3.3 1. Imax = 80 mA. 329

2. tT = 20 ns. 3. I = 2,56 A. Exercice 3.4 1.


vM 2V 0 -2 V t

2. voir cours. 3. voir cours. 4. Les potentiels sont rfrencs par rapport la masse. Exercice 3.5 1. V = 1,25 V. 2. C = 50 nF. Exercice 3.6 1. A ou B = 0 : T2, T4 bloqu, T3 passant ou satur. S = 1. A et B = 1 : T2, T4 satur, T3 bloqu. S=0. Le circuit est un NAND totem pole. 2. IA = IB = 525 A. IOHmax = 10,8 mA.
B

Vs [V] 3,6 3,3

6,25

32

IOH [mA]

3. IIA = IIB = 16,9 A. T4 satur jusqu' IOL = 75 mA. VS = 0,2 V. 4. protger le circuit contre les tensions ngatives. 5. IILmax = 0,4 mA, IOHmax = 0,4 mA, IIHmax = 20 A, IOLmax = 8 mA. 330

Exercice 3.7 1. A ou B = 0 : T2, T3 bloqu. S en lair ou au niveau 1 si lon a plac une rsistance entre la sortie et VCC. A et B = 1 : T2, T3 satur. S=0. Le circuit est un NAND collecteur ouvert. 2. IA = IB = 525 A. S est en lair (IC3 0), il faut connecter une rsistance Rc externe.
B

3. IIA = IIB = 16,9 A. T3 satur jusqu' IOL = 75 mA. VS = 0,2 V. 4. RCmax = 7,5 k pour une sortance de 20. RCmin = 112 avec 5 sorties connectes sur RC. 5. IILmax = 0,4 mA, IIHmax = 20 A, IOLmax = 8 mA. 6.

VCC

R = 410

Exercice 3.8 1. C = 0. T2, T3 bloqu, T4 passant. C = 1. A ou B = 0 : T2, T3 bloqu, Darlington passant. S = 1. A et B = 1 : T2, T3 satur, Darlington bloqu. S=0.
C = 1. T2, T3 satur, T4 bloqu. C = 0. T2, T3 et Darlington bloqu. S = haute

impdance. Le circuit est un NAND trois tats. 2. I C = 1 mA. IOHmax = 10,8 mA.
VC [V] 3,6 3,3

6,25

32

IOH [mA]

3. IIA = IIB = 16,9 A. T4 satur jusqu' IOL = 75 mA. VS = 0,2 V. D1 est polarise en inverse. 4. IIA = 1 mA. IOHmax = 16 mA.

331

Vs [V] 3,6

9,3

37

IOH [mA]

5. C = 0, D1 passante. VB1 = 0,9 V T2, T3 bloqu.VB41 = 0,9 V Darlington bloqu. 6. IILmax = 0,4 mA, IOHmax = 0,4 mA, IIHmax = 20 A, IOLmax = 8 mA. Exercice 3.9 1. 2. Input 1 0 X Disable 0 0 1 Output 0 1 Z T1 on on off T2 off on X T3 on off X T4 on on off

Exercice 3.10 1. Pour avoir S = 0, on doit avoir T4 = T5 = T6 = on et T1 = T2 = T3 = off E1 = E2 = E3 = 1. S = 1 pour toutes les autres combinaisons. 2. Cest un NAND. Exercice 3.11 1. Pour avoir T1 passant, on doit avoir G2 = 1 et E = 0. Pour avoir T2 passant, on doit avoir G1 = 0 et E = 1. 2. G1 1 1 0 0 E 0 1 0 1 S Z Z 0 1

3. Input = 0 B = A, Input = 1 C = A. Cest un dmultiplexeur.

332

Exercice 3.12 1. On a un inverseur sur A, B et Output. T et T forment une porte de transmission. 2. On a la table de vrit suivante :

A 0 0 1 1 Exercice 3.13

B 0 1 0 1

Output 0 1 1 0

porte trans on off on off

T1 off on off on

T2 off off off on

T3 off on off off

1. IIL et IOH sortant, IIH et IOL rentrant. 2. VOHmin = VIHmin + H VOHmin > VIHmin. VILmax = VOLmax + L VILmax > VOLmax. 3. H = VOHmin - VIHmin = 4,95 - 3,5 = 1,45 V. L = VILmax - VOLmax = 1,5 - 0,05 = 1,45 V. 4. 10000 portes en ne considrant que les courants. Il faut prendre en compte les capacits dentres et leur influence sur le temps de propagation. 5. temps de propagation = (0,90 ns/pF).CL + 80 ns (89 ns, 125 ns, 170 ns). temps de transition = (1,35 ns/pF).CL + 33 ns (46.5 ns, 100.5 ns, 168 ns).
E1 [V]

2,5

500 E2 [V]

t [ns]

2,5

500 S [V]

t [ns]

500

t [ns]

333

Exercice 3.14 1.

CP
D=Q

2. Nand : tP = (0,90 ns/pF).CL + 115 ns. Bascule : tP = (1,7 ns/pF).CL + 90 ns, tsmin = 40 ns, thmin = 40 ns. Cin = 7,5 pF. 3. fmax = 3,8 MHz. 4. fmax = 12,1 MHz. 5. CL = 50 pF, fmax = 2,9 Mhz. CL = 100 pF, fmax = 2,3 Mhz. Exercice 3.15 1. A 25 C, Pd = 2,4 W.
Pd [W]

3,4

85

TA [C]

2. A 25 C, Pd = 4 W.
Pd [W] 5

125

TA [C]

334

7.4

Corrigs chapitre 4

Exercice 4.1 1. 14 broches dadresses. 2. quand CS = 0, le botier est actif. quand CS = 1, le botier est dselectionn, les donnes sont ltat haute impdance. 3. Mmoires slectionnes M0, M1 M2, M3 adresses De 0 3FFF De 4000 7FFF

4 M0
CS

4 M1
CS

A14 Donnes 8 bits 4 M2


CS

4 M3
CS

Exercice 4.2 1. 13 broches dadresses. 2. quand CS = 0, le botier est actif. quand CS = 1, le botier est dselectionn, les donnes sont ltat haute impdance. 3. Mmoires slectionnes M0, M1 M2, M3 M4, M5 M6, M7 adresses De 0 1FFF De 2000 3FFF De 4000 5FFF De 6000 7FFF

335

8 M0
CS

8 M1
CS

8 M2
CS

8 M3
CS

Donnes 16 bits A14 Dec A15 2/4


CS CS

8 M4

8 M5

8 M6
CS

8 M7
CS

Exercice 4.3 1. Adresses ROM = 1xxx xxxx xxxx xxxx avec x valant 0 ou 1. Donc adresses = 8000 FFFF. 2. Adresses RAM = x110 xxxx xxxx xxxx avec x valant 0 ou 1. Donc adresses = 6000 6FFF et de E000 EFFF. 3. Adresses De 0000 5FFF De 6000 6FFF De 7000 7FFF De 8000 DFFF De E000 EFFF De F000 FFFF Zone Libre1 RAM 4 Ko Libre2 ROM 24 Ko ROM + RAM = impossible ROM 4 Ko

Les zones RAM et ROM + RAM sont des zones dadresses images. 336

4. libre1 = A15.( A14 + A13) = 24 Ko, libre2 = A15.A14.A13.A 12 = 4 Ko. 5. Entre du dcodeur : A11, A10, A9. Sortie du dcodeur, s0 s7. Le dcodeur est valid par libre2. Exercice 4.4 1. Taille dun bloc = 213 = 8 Ko.

Adresses De 0000 1FFF De 2000 3FFF De 4000 5FFF De 6000 7FFF De 8000 9FFF De A000 BFFF De C000 DFFF De E000 FFFF

Bloc n 1 2 3 4 5 6 7 8

2. Pour la RAM, il y a deux possibilits : de 0000 0FFF et de 1000 1FFF. Pour la ROM, il y a 4 possibilits : de E000 E7FF, de E800 EFFF, de F000 F7FF et de F800 FFFF. 0100 et 1100 adressent la mme case mmoire de la RAM. 3. De 8000 9FFF. Exercice 4.5 1.
A1 A1 A0 A0 G

Y3

Y2

Y1

Y0

337

2. dcodeur 2/4 sans G = 12 transistors CMOS, avec G = 16 transistors CMOS. Dcodeur N/2N sans G = (N+1). 2N, avec G = (N+2). 2N. 3. On a un dcodeur 20/220. Il faut 22020096 transistors CMOS. Avec un transistor par bit (DRAM), la matrice ne fait que 1048576 transistors. 4. Le premier dcodeur 4/16 attaque (via lentre G) 16 dcodeur 4/16 qui attaque chacun 16 dcodeur 4/16 et ainsi de suite jusqu obtenir 220 lignes (il faut 5 couches de dcodeurs). Nombre de transistors = 6710784. 5. On a deux dcodeurs 10/210. Nombre de transistors = 22528. La slection tage est possible. 6. 12 bits sur X, 8 bits sur Y. Cellule (3125,169). Exercice 4.6 1. R/W , adresses et VMA sont stables TAD aprs le front descendant de E. R/W , adresses et VMA se maintiennent tAH aprs le front descendant de E. En lecture, les donnes doivent arriver tDSR avant le front descendant de E et doivent rester stables tAH aprs. En criture, les donnes arrivent tDDW aprs le front descendant de E et restent stables tH aprs. 2. Priode E tAD tDSR = 630 ns. 3. Priode E/2 tDDW = 275 ns. 4. Non, les temps de maintien sont respects automatiquement. Exercice 4.7 1. 4 bits en entre, 4 bits en sortie. PROM 16 x 4. 2. I3, I2, I1 et I0 sur les adresses. O3, O2, O1 et O0 sur les donnes. In 0 1 2 3 4 5 6 7 O3 0 0 0 0 0 0 0 0 O2 0 0 0 0 1 1 1 1 O1 0 0 1 1 1 1 0 0 O0 0 1 1 0 0 1 1 0 In 8 9 10 11 12 13 14 15 O3 1 1 1 1 1 1 1 1 O2 1 1 1 1 0 0 0 0 O1 0 0 1 1 1 1 0 0 O0 0 1 1 0 0 1 1 0

338

Exercice 4.8 1. 4 bits en entre, 8 bits en sortie. PROM 16 x 8. 2. I3, I2, I1 et I0 sur les adresses. C13, C12, C11 et C10 et C03, C02, C01 et C00 sur les donnes.

In 0 1 2 3 4 5 6 7 Exercice 4.9

C1 0 0 0 0 0 0 0 0

C0 0 1 2 3 4 5 6 7

In 8 9 10 11 12 13 14 15

C1 0 0 1 1 1 1 1 1

C0 8 9 0 1 2 3 4 5

1. 128 caractres de 8 lignes = PROM 1024 x 5. 2. A0, A1, A2 = slection de la ligne, A3 A9 = code ASCII.

A2 A1 A0 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 Exercice 4.10 1. IB2 = 4,2 mA. IC2 = 4,8 mA. IB2 >> IC2 T2 satur. VBE1 = VCE2 = 0.2 V T1 bloqu. V1 = 0.8 V, V2 = 0.2 V. Ltat est stable. 2. Aucun changement. 3. La tension 0 V fait basculer le montage. Les valeurs de courants et de tension sont identiques la question 1, mais les indices 1 et 2 sont inverss. 4. On dconnecte V1 et V2, ltat reste stable. Cest bien une mmoire. 339 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0

5. Les amplificateurs de lecture dtectent le sens du courant sur chaque sortie. Exercice 4.11 1. Qs = Cs.Vs, Qb = 0. 2. Qs = Vfin.Cs, Qb = Vfin.Cb. 3. Vfin = Vs.Cs/(Cs + Cb). Exercice 4.12 1.
1 2 3 4 5 6 7 8 9 10 11

X X X X

X X X 0

X X 1 0

X 2 1 0

3 2 1 0

3 2 1 4

3 2 1 4

3 2 1 4

3 2 5 4

3 2 5 4

3 2 5 4

3 6 5 4

2. 3,3 Ko/s. Exercice 4.13 1. Voir 5.2.2.2. 2. Voir figure 1 et 2 page A-32. 3. Voir tableau AC CHARACTERISTICS page A-33 et chronogrammes page A-35. 4. Voir paragraphe Erasing the AM27C1024 page A-29. 5. Voir les trois paragraphes Programming the AM27C1024 , Program inhibit et Program verify page A-29 ainsi que le tableau page A-30. Exercice 4.14 1. Voir 5.3.1.2. 340

2. Voir tableau Read cycle page A-41 et chronogramme Read cycle n2 page A-42. 3. Voir tableau Write cycle page A-41 et chronogramme Write cycle n2 page A-43.

7.5

Corrigs chapitre 5

Exercice 5.1 1. On a 4 sorties, chacune delle comportant 4 termes produit des 4 variables dentre. 2.

Exercice 5.2 1. A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D W X 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 1 1 0 341 Y 0 0 1 1 1 1 1 1 0 0 Z 0 1 1 0 0 0 0 1 1 0

1 1 1 1 1 1

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

X X X X X X

X X X X X X

X X X X X X

X X X X X X

2. W = A + B.D + B.C , X = B.C , Y = B + C , Z = A.B.C.D + B.C.D + A.D + B.C.D . 3.

Exercice 5.3 1. A 0 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 D EQ NE 0 1 0 1 0 1 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 0 1 342 LT GT 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 0 0 0 0 1

1 1 0 1 1 1 1 0

0 0 0 1 0 0 0 0

1 1 0 0 1 1 1 0

2. EQ = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D ,

NE = A.C + A.C + B.D + B.D ,

LT = A.C + A.B.D + B.C.D , GT = A.C + A.B.D + B.C.D .


3.

Exercice 5.4 1. nb TA EA D3 D2 D1 D0 C0 C1 C2 C3 C4 C5 C6 0 1 1 0 0 0 0 0 343 0 0 0 0 0 1

1 2 3 4 5 6 7 8 9 b d E F

1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1

0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1

0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1

1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1

1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1

1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1

1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

A 1 C 1

X 0 X 1

1 X X 0 X X

X X X X

2. C0 = D0.D2 + D0.D3 + D1.D2 + D1.D2.D3 + D0.D2.D3 + D1.D2.D3 ,

C1 = D2.D3 + D0.D2 + D0.D1.D3 + + D0.D1.D3 + + D0.D1.D3 , C2 = D0.D1 + D0.D2 + D1.D2 + D2.D3 + D2.D3 , C3 = D1.D3 + D0.D2.D3 + D0.D1.D2 + D0.D1.D2 + D0.D1.D2 , C4 = D0.D2 + D2.D3 + D0.D1 + D1.D3 , C5 = D0.D1 + D2.D3 + D1.D3 + D0.D2 + D1.D2.D3 , C6 = D1.D2 + D0.D3 + D2.D3 + D0.D1 + D1.D2.D3 .
EA commande les buffers de sortie (actif 1, haute impdance 0). TA = 0 toutes les sorties Cn 0. 3. 16L8 : 8 sorties avec 7 termes produit de 16 variables. 10 entres, 2 sorties, 6 entres/sorties en fonction de ltat du buffer. 4.

344

Exercice 5.5 1. S2 S1 S0 O7 O6 O5 345 O4 O3 O2 O1 O0

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0 D7

D5 D4 D3 D2 D1 D0 D7 D6

D4 D3 D2 D1 D0 D7 D6 D5

D3 D2 D1 D0 D7 D6 D5 D4

D2 D1 D0 D7 D6 D5 D4 D3

D1 D0 D7 D6 D5 D4 D3 D2

D0 D7 D6 D5 D4 D3 D2 D1

2.

O 7 = S2 .S1.S0 .D7 + S2 .S1.S0 .D6 + S2 .S1.S0 .D5 + S2 .S1.S0 .D4 + S2 .S1.S0 .D3 + S2 .S1.S0 .D3 + S2 .S1.S0 .D1 + S2 .S1.S0 .D0

O 6 = S2 .S1.S0 .D6 + S2 .S1.S0 .D5 + S2 .S1.S0 .D4 + S2 .S1.S0 .D3 + S2 .S1.S0 .D2 + S2 .S1.S0 .D1 + S2 .S1.S0 .D0 + S2 .S1.S0 .D7 O 5 = S2 .S1.S0 .D5 + S2 .S1.S0 .D4 + S2 .S1.S0 .D3 + S2 .S1.S0 .D2 + S2 .S1.S0 .D1 + S2 .S1.S0 .D0 + S2 .S1.S0 .D7 + S2 .S1.S0 .D6 O 4 = S2 .S1.S0 .D4 + S2 .S1.S0 .D3 + S2 .S1.S0 .D2 + S2 .S1.S0 .D1 + S2 .S1.S0 .D0 + S2 .S1.S0 .D7 + S2 .S1.S0 .D6 + S2 .S1.S0 .D5 O 3 = S2 .S1.S0 .D3 + S2 .S1.S0 .D2 + S2 .S1.S0 .D1 + S2 .S1.S0 .D0 + S2 .S1.S0 .D7 + S2 .S1.S0 .D6 + S2 .S1.S0 .D5 + S2 .S1.S0 .D4

O 2 = S2 .S1.S0 .D2 + S2 .S1.S0 .D1 + S2 .S1.S0 .D0 + S2 .S1.S0 .D7 + S2 .S1.S0 .D6 + S2 .S1.S0 .D5 + S2 .S1.S0 .D4 + S2 .S1.S0 .D3 O1 = S2 .S1.S0 .D1 + S2 .S1.S0 .D0 + S2 .S1.S0 .D7 + S2 .S1.S0 .D6 + S2 .S1.S0 .D5 + S2 .S1.S0 .D4 + S2 .S1.S0 .D3 + S2 .S1.S0 .D2

O 0 = S2 .S1.S0 .D0 + S2 .S1.S0 .D7 + S2 .S1.S0 .D6 + S2 .S1.S0 .D5 + S2 .S1.S0 .D4 + S2 .S1.S0 .D3 + S2 .S1.S0 .D2 + S2 .S1.S0 .D1

3. 20R8 : 8 sorties comportant 8 termes produit de 20 variables. 12 entres, 8 sorties. Actif au niveau bas on entre Dn . 4.

346

7.6

Corrigs chapitre 6

Exercice 6.1 1. Le spectre tant infini, il faut mettre un filtre anti-repliement avec fc = 1/20.T. On prend ensuite fe = 2.fc. 2. = 1/8 = 125 mV.

347

3.
B : Valeur numrique Ex

111 110 101 100 011 010 001 000

7.Vref/8 6.Vref/8 5.Vref/8 4.Vref/8 3.Vref/8 2.Vref/8 Vref/8 t Te 2.Te 3.Te T

Ex - B

4. SNR = 6.N + 1.76 20 dB. 5.


Ex 2.Vref

B : Valeur numrique

111 110 101 100 011 010 001 000

7.Vref/8 6.Vref/8 5.Vref/8 4.Vref/8 3.Vref/8 2.Vref/8 Vref/8 t Te 2.Te 3.Te T

348

6.
B : Valeur numrique 011 010 001 000 3.Vref/8 2.Vref/8 Vref/8 t Te 2.Te 3.Te T Ex

Ex - B

7. SNR 3 dB. ENOB 0,2 bits. Exercice 6.2 1. SNR = 6.N + 2. 2. Dynamique = 20.log10 2 N 1 . 3. Rsolution =
1 x100 %FSR . 2N

6 SNR [dB] Dynamique [dB]

12 74 72

16 98 96

24 146 144

38 50 36 48

Rsolution [%FSR] 1.6 0.4 0.025 0.0015 6.10-6 Exercice 6.3 1.


H b0 Ve b1 Registre dcalage b0 b1 Vs

CAN N bits

Registre dcalage

CNA N bits

bN-1

Registre dcalage

bN-1

349

2. Le montage est synchrone. 3. Le retard est fonction de la priode de H. Exercice 6.4 1. Vref fait varier lamplitude, H fait varier la frquence.
Vcc CNA N bits

Vref

Vs

bN-1

b1

b0 H

Compteur N bits

2. LEPROM contient une priode chantillonne de la sinusode.


Vcc CNA N bits

Vref

Vs

dN-1 EPROM

d1

d0

AM-1

A1

A0 H

Compteur N bits

Exercice 6.5 1. S2 = S3 = b4 = b3 = b2 = b1 = b0 = 1, S1 sur Ex. 2. Qtot = 2CEx. 3. Qtot = -2CVx. Vx = -Ex. 4. Qtot = Cvref 2CVx. Vx = -Ex + Vref/2. 5. b4 = 1. 6. Qtot = 3Cvref/2 2CVx. Vx = -Ex + Vref/2 + Vref/4. 350

7. b3 = 1. 8. b2 = 0, b1 = 0, b0 = 1. Exercice 6.6 1. RD = R, RC = R, RB = R, RA = R.
B

2. Itot = Vref / R. IA = Vref / 2R. VB = Vref / 2.


B

3. IB = Vref / 4R. VC = Vref / 4.


B

4. IC = Vref / 8R. VD = Vref / 8. ID = Vref / 16R. 5. Is = b3.Vref / 2R + b2.Vref / 4R + b1.Vref / 8R + b0.Vref / 16R. Vs = (-Vref / 2)( b3 + b2 / 2 + b1 / 4 + b0 / 8). B = 1011, Vs = -6.875 V. 6. Vref = -10 V, Vs = +6.875 V. 7. On obtient en Vs une sinusode en opposition de phase dont lamplitude crte A vaut :

1011 3.4375 V 0001 0.3125 V 1111 4.6875 V 8. Vs = Vref/2 + (-Vref / 2)( b 3 + b2 / 2 + b1 / 4 + b0 / 8). Le CNA fonctionne en code complment 2.

Vs

0111 2.1875 V 0001 0.3125 V 0000 0.0 V 1111 -0.3125 V 1001 -2.1875 V 1000 Exercice 6.7 1. Voir 7.3.3. 2. Voir 7.3.3. 3. Voir 7.3.3. 351 -2.5 V

4. Les timings page A-50. Lalimentation et les dcouplages page A-56. Les diagrammes page A-61. Exercice 6.8 1. CNA 12 bits R-2R sortie tension Technologie BicMOS Alimentation 5 V Consommation 15 3 mW 1 mV / bit en sortie Rfrence interne Bus microprocesseur Botiers DIP et SOIC 20 broches. 2. rsolution Prcision Linarit 3. Temps dtablissement 16 s ( 1 LSB) 4. Le timing fig.2 page A-65. Le cblage page A-71. Les modes oprations page A-72 A75. Linterface 68HC11 page A-76. 12 bits 1/4 LSB Voir figure 1 page A-63

Non-linarit diffrentielle 3/4 LSB (monotone)

352

8 Annexe

Data sheet SN74LS00 SN74LS74A MC14011B, MC14081B MC14013B AM27C1024 CY7C109 AD676 DAC8562

page A-1 A-3 A-7 A-19 A-25 A-37 A-47 A-63

353

354

SN54/74LS00 QUAD 2-INPUT NAND GATE


ESD > 3500 Volts

QUAD 2-INPUT NAND GATE


VCC 14 13 12 11 10 9 8

LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 GND


14 1

14 1

N SUFFIX PLASTIC CASE 646-06

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC

GUARANTEED OPERATING RANGES


Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

FAST AND LS TTL DATA 5-2

SN54/74LS00
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S b l VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Min 2.0

Typ

Max

Unit U i V

Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

0.7 V 0.8 0.65 2.5 2.7 3.5 3.5 0.25 0.35 0.4 0.5 20 1.5 V V V V V A mA mA mA

IIH IIL IOS ICC

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

0.4 20 100 1.6 4.4

mA

AC CHARACTERISTICS (TA = 25C)


Limits Symbol S b l tPLH tPHL Parameter P Turn-Off Delay, Input to Output Turn-On Delay, Input to Output Min Typ 9.0 10 Max 15 15 Unit U i ns ns Test C di i T Conditions VCC = 5.0 V CL = 15 pF

FAST AND LS TTL DATA 5-3

SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP


The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP


LOW POWER SCHOTTKY

LOGIC DIAGRAM (Each Flip-Flop)


14 1

J SUFFIX CERAMIC CASE 632-08

SET (SD) 4 (10) Q 5 (9) CLEAR (CD) 1 (13) CLOCK 3 (11) D 2 (12)
14

N SUFFIX PLASTIC CASE 646-06


1

Q 6 (8)

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION MODE SELECT TRUTH TABLE


INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load 1 (Set) Load 0 (Reset) L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H OUTPUTS SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC

LOGIC SYMBOL
4 2 3 D SD Q CP CD Q 1 VCC = PIN 14 GND = PIN 7 6 5 12 11 10 D SD Q CP CD Q 13 8 9

* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Dont Care i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time i, h (q) = prior to the HIGH to LOW clock transition.

FAST AND LS TTL DATA 5-1

SN54/74LS74A
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits Symbol S b l VIH VIL VIK VOH Parameter P Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage 74 Input High Current Data, Clock Set, Clear Data, Clock Set, Clear IIL IOS ICC Input LOW Current Data, Clock Set, Clear Output Short Circuit Current (Note 1) Power Supply Current 20 0.35 0.5 20 40 0.1 0.2 0.4 0.8 100 8.0 V A 2.5 2.7 54 74 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 1.5 Typ Max Unit U i V V V V V V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

IIH

mA

VCC = MAX, VIN = 7.0 V

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)


Limits Symbol S b l fMAX tPLH tPHL Parameter P Maximum Clock Frequency Clock, Clear, Clock Clear Set to Output Min 25 Typ 33 13 25 25 40 Max Unit U i MHz ns ns Test C di i T Conditions Figure 1 Figure 1 VCC = 5.0 V 50 CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25C)


Limits Symbol S b l tW (H) tW (L) ts th Clock Clear, Set Data Setup Time HIGH p Data Setup Time LOW Hold Time Parameter P Min 25 25 20 20 5.0 Typ Max Unit U i ns ns ns Figure 1 ns ns Figure 1 Test C di i T Conditions Figure 1 Figure 2 VCC = 5.0 V 50

FAST AND LS TTL DATA 5-2

SN54/74LS74A
AC WAVEFORMS

D*

1.3 V th(L) ts(L) 1.3 V tW(H)

1.3 V th(H) ts(H) tW(L) 1.3 V 1 fMAX

CP tPHL Q 1.3 V tPHL 1.3 V

tPLH 1.3 V

tPLH 1.3 V Q

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays, Data Set-Up and Hold Times, Clock Pulse Width

tW SET 1.3 V 1.3 V tW CLEAR tPLH 1.3 V tPHL Q

1.3 V tPHL 1.3 V tPLH

1.3 V

1.3 V

1.3 V

Figure 2. Set and Clear to Output Delays, Set and Clear Pulse Widths

FAST AND LS TTL DATA 5-3

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

B-Suffix Series CMOS Gates


The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. Supply Voltage Range = 3.0 Vdc to 18 Vdc All Outputs Buffered Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B PinforPin Replacements for Corresponding CD4000 Series B Suffix Devices (Exceptions: MC14068B and MC14078B)

Quad 2-Input NOR Gate Dual 4-Input NOR Gate Quad 2-Input NAND Gate Dual 4-Input NAND Gate Triple 3-Input NAND Gate Triple 3-Input NOR Gate 8-Input NAND Gate Quad 2-Input OR Gate Dual 4-Input OR Gate Triple 3-Input AND Gate Triple 3-Input OR Gate 8-Input NOR Gate Quad 2-Input AND Gate Dual 4-Input AND Gate

MC14001B MC14002B MC14011B MC14012B MC14023B MC14025B MC14068B MC14071B MC14072B MC14073B MC14075B MC14078B MC14081B MC14082B

L SUFFIX CERAMIC CASE 632

P SUFFIX PLASTIC CASE 646

D SUFFIX SOIC CASE 751A

ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC


TA = 55 to 125C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to VSS)


Symbol VDD Parameter DC Supply Voltage

Value

Unit V V

0.5 to + 18.0 10 500

Vin, Vout lin, lout PD

Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature

mA

mW

Tstg

65 to + 150

_C

TL Lead Temperature (8Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C Ceramic L Packages: 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

REV 3 1/94

MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14001B 7

LOGIC DIAGRAMS
NOR MC14001B Quad 2Input NOR Gate
1 2

NAND MC14011B Quad 2Input NAND Gate


1 2 5 6 8 9 12 13

OR MC14071B Quad 2Input OR Gate


1 2 5 6 8 9 12 13

AND MC14081B Quad 2Input AND Gate


1 2 5 6 8 9 12 13

2 INPUT

5 6 8 9 12 13

10

10

10

10

11

11

11

11

MC14025B Triple 3Input NOR Gate


1 2 8 3 4 5 11 12 13 9

MC14023B Triple 3Input NAND Gate


1 2 8 3 4 5 11 12 13 9

MC14075B Triple 3Input OR Gate


1 2 8 3 4 5 11 12 13 9

MC14073B Triple 3Input AND Gate


1 2 8 3 4 5 11 12 13 9

3 INPUT

10

10

10

10

MC14002B Dual 4Input NOR Gate


2 3 4 5 9 10 11 12

MC14012B Dual 4Input NAND Gate


2 3 4 5 9 10 11 12

MC14072B Dual 4Input OR Gate


2 3 4 5 9 10 11 12

MC14082B Dual 4Input AND Gate


2 3 4 5 9 10 11 12

4 INPUT

13 NC = 6, 8

13 NC = 6, 8

13 NC = 6, 8

13 NC = 6, 8

MC14078B 8Input NOR Gate


2 3 4 5 9 10 11 12 2 3 4 5 9 10 11 12

MC14068B 8Input NAND Gate


VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES 13

8 INPUT

13

NC = 6, 8

NC = 6, 8

MC14001B 8

MOTOROLA CMOS LOGIC DATA

PIN ASSIGNMENTS
MC14001B Quad 2Input NOR Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C

MC14002B Dual 4Input NOR Gate


OUTA IN 1A IN 2A IN 3A IN 4A NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUTB IN 4B IN 3B IN 2B IN 1B NC

MC14011B Quad 2Input NAND Gate


IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C

MC14012B Dual 4Input NAND Gate


OUTA IN 1A IN 2A IN 3A IN 4A NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUTB IN 4B IN 3B IN 2B IN 1B NC

MC14023B Triple 3Input NAND Gate


IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A

MC14025B Triple 3Input NOR Gate


IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A

MC14068B 8Input NAND Gate


NC IN 1 IN 2 IN 3 IN 4 NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUT IN 8 IN 7 IN 6 IN 5 NC

MC14071B Quad 2Input OR Gate


IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C

MC14072B Dual 4Input OR Gate


OUTA IN 1A IN 2A IN 3A IN 4A NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUTB IN 4B IN 3B IN 2B IN 1B NC

MC14073B Triple 3Input AND Gate


IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A

MC14075B Triple 3Input OR Gate


IN 1A IN 2A IN 1B IN 2B IN 3B OUTB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 3C IN 2C IN 1C OUTC OUTA IN 3A

MC14078B 8Input NOR Gate


NC IN 1 IN 2 IN 3 IN 4 NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUT IN 8 IN 7 IN 6 IN 5 NC

MC14081B Quad 2Input AND Gate


IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C

MC14082B Dual 4Input AND Gate


OUTA IN 1A IN 2A IN 3A IN 4A NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUTB IN 4B IN 3B IN 2B IN 1B NC NC = NO CONNECTION

MOTOROLA CMOS LOGIC DATA

MC14001B 9


** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: #Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Total Supply Current** (Dynamic plus Quiescent, Per Gate, CL = 50 pF)

Quiescent Current (Per Package)

Input Capacitance (Vin = 0)

Input Current

Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

Input Voltage 0 Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

Output Voltage Vin = VDD or 0

MC14001B 10
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Characteristic 1 Level 1 Level 0 Level Source Sink Symbol VOH VOL IOH IDD VIH IOL Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 3.0 0.64 1.6 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 55_C 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 1.5 3.0 4.0 2.4 0.51 1.3 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 0.00001 0.0005 0.0010 0.0015 4.2 0.88 2.25 8.8 Typ # 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0

IT = (0.3 A/kHz) f + IDD/N IT = (0.6 A/kHz) f + IDD/N IT = (0.9 A/kHz) f + IDD/N

MOTOROLA CMOS LOGIC DATA


0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 7.5 1.5 3.0 4.0 1.7 0.36 0.9 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.5 3.0 4.0 mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF


BSERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc Min Typ # 100 50 40 100 50 40 Max 200 100 80 200 100 80 Unit ns Output Rise Time, All BSeries Gates tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns Output Fall Time, All BSeries Gates tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns 5.0 10 15 5.0 10 15 tTHL ns Propagation Delay Time MC14001B, MC14011B only tPLH, tPHL = (0.90 ns/pF) CL + 80 ns tPLH, tPHL = (0.36 ns/pF) CL + 32 ns tPLH, tPHL = (0.26 ns/pF) CL + 27 ns All Other 2, 3, and 4 Input Gates tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 8Input Gates (MC14068B, MC14078B) tPLH, tPHL = (0.90 ns/pF) CL + 155 ns tPLH, tPHL = (0.36 ns/pF) CL + 62 ns tPLH, tPHL = (0.26 ns/pF) CL + 47 ns tPLH, tPHL ns 5.0 10 15 5.0 10 15 5.0 10 15 125 50 40 160 65 50 200 80 60 250 100 80 300 130 100 350 150 110 * The formulas given are for the typical characteristics only at 25_C. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance. 14 INPUT OUTPUT * CL VDD 20 ns INPUT tPHL OUTPUT INVERTING 90% 50% 10% tTHL tPLH 90% 50% 10% tTLH tPHL 90% 50% 10% tPLH VOH VOL VOH VOL 20 ns VDD 0V PULSE GENERATOR 7 VSS * All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. OUTPUT NONINVERTING tTLH tTHL

Figure 1. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA

MC14001B 11

CIRCUIT SCHEMATIC NOR, OR GATES


MC14001B, MC14071B One of Four Gates Shown
VDD 1, 6, 8, 13 * 2, 5, 9, 12 3, 4, 10, 11 14 VDD

MC14025B, MC14075B One of Three Gates Shown


VSS * Inverter omitted in MC14001B 7 VSS 1, 3, 11 2, 4, 12 14 * VDD VDD

MC14002B, MC14072B One of Two Gates Shown


VDD 3, 9 8, 5, 13 2, 10 14 * VDD

VSS 9, 6, 10 VDD

7 VSS

VSS

* Inverter omitted in MC14025B

VSS

1, 13

5, 11 4, 12

SAME AS ABOVE 7 * Inverter omitted in MC14002B VDD 2 3 VSS

MC14078B Eight Input Gate

14 VSS SAME AS ABOVE SAME AS ABOVE SAME AS ABOVE

VDD

4 5 9 10 11 12

13

VSS

MC14001B 12

MOTOROLA CMOS LOGIC DATA

CIRCUIT SCHEMATIC NAND, AND GATES


MC14011B, MC14081B One of Four Gates Shown
14 * VDD

MC14023B, MC14073B One of Three Gates Shown


VDD 2, 5, 9, 12 1, 6, 8, 13

3, 4, 10, 11

7 VSS * Inverter omitted in MC14011B 2, 4, 12 1, 3, 11

14

VDD

VSS VDD

* 9, 6, 10

8, 5, 13 7 VSS * Inverter omitted in MC14023B VSS

MC14012B, MC14082B One of Two Gates Shown


VDD

14 VDD

MC14068B Eight Input Gate

VDD

2, 10 * 3, 9 VSS 4, 12 5, 11 SAME AS ABOVE * Inverter omitted in MC14012B 7 1, 13

VDD 2 3 VSS 5 4 SAME AS ABOVE

VSS

14 VSS 9 10 11 12 SAME AS ABOVE SAME AS ABOVE VDD

VDD

13

7 VSS VSS

MOTOROLA CMOS LOGIC DATA

MC14001B 13

TYPICAL BSERIES GATE CHARACTERISTICS


NCHANNEL DRAIN CURRENT (SINK)
5.0 10 9.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 4.0 TA = 55C 40C + 85C + 25C 2.0 1.0 + 125C 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAINTOSOURCE VOLTAGE (Vdc) 5.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAINTOSOURCE VOLTAGE (Vdc) 5.0 + 85C 40C + 25C TA = 55C

PCHANNEL DRAIN CURRENT (SOURCE)

3.0

+ 125C

Figure 2. VGS = 5.0 Vdc


20 18 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAINTOSOURCE VOLTAGE (Vdc) 9.0 10 TA = 55C 40C + 25C + 85C + 125C 50 45 40 35 30 25 20 15 10 5.0 0 0

Figure 3. VGS = 5.0 Vdc

TA = 55C 40C + 25C + 85C + 125C

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 VDS, DRAINTOSOURCE VOLTAGE (Vdc)

Figure 4. VGS = 10 Vdc


50 45 40 ID , DRAIN CURRENT (mA) 35 30 25 20 15 10 5.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAINTOSOURCE VOLTAGE (Vdc) 18 20 + 125C TA = 55C 40C + 25C + 85C ID , DRAIN CURRENT (mA) 100 90 80 70 60 50 40 30 20 10 0 0

Figure 5. VGS = 10 Vdc

TA = 55C 40C + 25C + 85C + 125C

2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAINTOSOURCE VOLTAGE (Vdc)

18 20

Figure 6. VGS = 15 Vdc

Figure 7. VGS = 15 Vdc

These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin.

MC14001B 14

MOTOROLA CMOS LOGIC DATA

TYPICAL BSERIES GATE CHARACTERISTICS (contd)


VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

5.0 4.0 3.0 2.0 1.0 0 0 1.0 2.0

SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR

V out , OUTPUT VOLTAGE (Vdc)

10 8.0 6.0 4.0 2.0 0 0 2.0 4.0

SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND

SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND

3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc)

6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc

Figure 9. VDD = 10 Vdc

16 V out , OUTPUT VOLTAGE (Vdc) 14 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR

DC NOISE MARGIN The DC noise margin is defined as the input voltage range from an ideal 1 or 0 input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the 1 and 0 levels = 1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply

Figure 10. VDD = 15 Vdc

Vout VO

VDD

Vout VO

VDD

VO VDD 0 VIL VIH Vin

VO VDD 0 VIL VSS = 0 VOLTS DC VIH Vin

(a) Inverting Function

(b) NonInverting Function

Figure 11. DC Noise Immunity

MOTOROLA CMOS LOGIC DATA

MC14001B 15

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 63208 ISSUE Y
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01

A
14 9

B
1 7

T
SEATING PLANE

K F D
14 PL

G 0.25 (0.010)
M

N J T A
S 14 PL

M 0.25 (0.010)
M

T B

DIM A B C D F G J K L M N

P SUFFIX PLASTIC DIP PACKAGE CASE 64606 ISSUE L


14 8

B
1 7

NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01

A F C N H G D
SEATING PLANE

J K M

MC14001B 16

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A03 ISSUE F
A
14 8

B
1 7

P 7 PL 0.25 (0.010)
M

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

G C

R X 45 _

T
SEATING PLANE

D 14 PL 0.25 (0.010)
M

K T B
S

M A
S

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 18004412447 or 6023035454 MFAX: RMFAX0@email.sps.mot.com TOUCHTONE 6022446609 INTERNET: http://DesignNET.com

JAPAN: Nippon Motorola Ltd.; TatsumiSPDJLDC, 6F SeibuButsuryuCenter, 3142 Tatsumi KotoKu, Tokyo 135, Japan. 038135218315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

MOTOROLA CMOS LOGIC DATA

*MC14001B/D*

MC14001B MC14001B/D 17

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14011B/12B (see pg 6-5) MC14011UB/12UB (see pg 6-14)

MC14013B Dual Type D Flip-Flop


The MC14013B dual type D flipflop is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each flipflop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flipflops for counter and toggle applications. Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic EdgeClocked FlipFlop Design Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positivegoing edge of the clock pulse Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range PinforPin Replacement for CD4013B MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 632

P SUFFIX PLASTIC CASE 646

D SUFFIX SOIC CASE 751A

ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC


Value Unit V V 0.5 to + 18.0 Vin, Vout lin, lout PD Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 10 500 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg TL 65 to + 150 260

TA = 55 to 125C for all packages.

BLOCK DIAGRAM
6 5 D S Q 1

_C _C

Lead Temperature (8Second Soldering)

3 4 8 9

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C Ceramic L Packages: 12 mW/_C From 100_C To 125_C

TRUTH TABLE
Inputs Clock Data 0 1 X X X X X X X Reset 0 0 0 1 0 1 Set 0 0 0 0 1 1 Outputs Q 0 1 Q 0 1 1 Q 1 0 Q 1 0 1 No Change

13

11 10

12

VDD = PIN 14 VSS = PIN 7

X = Dont Care = Level Change

REV 3 1/94

MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14013B 45


** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: #Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

Quiescent Current (Per Package)

Input Capacitance (Vin = 0)

Input Current

Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

Input Voltage 0 Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

Output Voltage Vin = VDD or 0

MC14013B 46
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) 1 Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Characteristic 1 Level 0 Level Source Sink Symbol VOH VOL IOH IDD VIH IOL Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 3.0 0.64 1.6 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 55_C 0.1 0.05 0.05 0.05 Max 1.0 2.0 4.0 1.5 3.0 4.0 2.4 0.51 1.3 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 0.00001 4.2 0.88 2.25 8.8 Typ # 0.002 0.004 0.006 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0

IT = (0.75 A/kHz) f + IDD IT = (1.5 A/kHz) f + IDD IT = (2.3 A/kHz) f + IDD

MOTOROLA CMOS LOGIC DATA


0.1 0.05 0.05 0.05 Max 1.0 2.0 4.0 7.5 1.5 3.0 4.0 VSS QA QA CA RA DA SA

PIN ASSIGNMENT

1.7 0.36 0.9 2.4

7 6 5 4 3 2 1 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11

125_C

10

12

13

14

11

1.0

8 9 1.5 3.0 4.0

0.05 0.05 0.05

Max

30 60 120

SB DB QB VDD RB CB QB mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF


* The formulas given are for the typical characteristics only at 25_C. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance. ** Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Removal Times Set

Set and Reset Pulse Width

Clock Pulse Rise and Fall Time

Clock Pulse Frequency

Clock Pulse Width

Hold Times**

Setup Times**

Propagation Delay Time Clock to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 90 ns tPLH, tPHL = (0.66 ns/pF) CL + 42 ns tPLH, tPHL = (0.5 ns/pF) CL + 25 ns

Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

MOTOROLA CMOS LOGIC DATA


Reset to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 265 ns tPLH, tPHL = (0.66 ns/pF) CL + 67 ns tPLH, tPHL = (0.5 ns/pF) CL + 50 ns Set to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 90 ns tPLH, tPHL = (0.66 ns/pF) CL + 42 ns tPLH, tPHL = (0.5 ns/pF) CL + 25 ns Reset Characteristic R C D S C C C C C C

LOGIC DIAGRAM (1/2 of Device Shown)

tWL, tWH

tWL, tWH

Symbol

tTLH, tTHL

tPLH tPHL

tTLH tTHL

trem

tsu

fcl

th

VDD

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

5 10 15

5 10 15

Min

250 100 70

250 100 70

50 30 25

80 45 35

40 20 15

40 20 15

Typ #

35 10 5

125 50 35

125 50 35

225 100 75

175 75 50

175 75 50

100 50 40

4.0 10 14

20 10 7.5

20 10 7.5

0 5 5

Max

450 200 150

350 150 100

350 150 100

200 100 80

2.0 5.0 7.0

15 5.0 4.0

MC14013B 47
MHz Unit s ns ns ns ns ns ns ns

20 ns D tsu (H) C tWH 1 fcl 90% 50% 10% tTLH Inputs R and S low. 90% 50% 10%

20 ns

VDD VSS 20 ns VDD VSS CLOCK tPHL tPLH tPHL Q OR Q 50% VOL 20 ns SET OR RESET 90% 50% tw 20 ns 90% 50% tw 10% 10% trem 20 ns 20 ns VDD VSS VDD VSS VOH

tsu (L) th

90% 50% 10% tWL

tPLH Q

VOH VOL

tTHL

Figure 1. Dynamic Signal Waveforms (Data, Clock, and Output)

Figure 2. Dynamic Signal Waveforms (Set, Reset, Clock, and Output)

TYPICAL APPLICATIONS
nSTAGE SHIFT REGISTER
1 D D C CLOCK Q Q D C 2 Q Q D C nth Q Q Q

BINARY RIPPLE UPCOUNTER (Divideby2n)


1 D CLOCK C Q Q D C 2 Q Q D C nth Q Q Q

T FLIPFLOP

MODIFIED RING COUNTER (Divideby(n+1))


1 D C CLOCK Q Q D C 2 Q Q D C nth Q Q Q

MC14013B 48

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 63208 ISSUE Y
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01

A
14 9

B
1 7

T
SEATING PLANE

K F D
14 PL

G 0.25 (0.010)
M

N J T A
S 14 PL

M 0.25 (0.010)
M

T B

DIM A B C D F G J K L M N

P SUFFIX PLASTIC DIP PACKAGE CASE 64606 ISSUE L


14 8

B
1 7

NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01

A F C N H G D
SEATING PLANE

J K M

MOTOROLA CMOS LOGIC DATA

MC14013B 49

OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A03 ISSUE F
A
14 8

B
1 7

P 7 PL 0.25 (0.010)
M

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

G C

R X 45 _

T
SEATING PLANE

D 14 PL 0.25 (0.010)
M

K T B
S

M A
S

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 18004412447 or 6023035454 MFAX: RMFAX0@email.sps.mot.com TOUCHTONE 6022446609 INTERNET: http://DesignNET.com

JAPAN: Nippon Motorola Ltd.; TatsumiSPDJLDC, 6F SeibuButsuryuCenter, 3142 Tatsumi KotoKu, Tokyo 135, Japan. 038135218315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

MC14013B 50

*MC14013B/D*

MOTOROLA CMOS LOGIC DATA MC14013B/D

FINAL

Am27C1024
1 Megabit (65 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time Speed options as fast as 55 ns s Low power consumption 20 A typical CMOS standby current s JEDEC-approved pinout 40-Pin DIP/PDIP 44-Pin PLCC s Single +5 V power supply s 10% power supply tolerance standard s 100% Flashrite programming Typical programming time of 8 seconds s Latch-up protected to 100 mA from 1 V to VCC + 1 V s High noise immunity s Versatile features for simple interfacing Both CMOS and TTL input/output compatibility Two line control functions

GENERAL DESCRIPTION
The Am27C1024 is a 1 Megabit, ultraviolet erasable programmable read-only memory. It is organized as 64 Kwords by 16 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP packages, as well as plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMDs CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 100 W in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMDs Flashrite programming algorithm (100 s pulses), resulting in a typical programming time of 8 seconds.

BLOCK DIAGRAM
VCC VSS VPP OE# CE# PGM# Output Enable Chip Enable and Prog Logic Y Decoder A0A15 Address Inputs Data Outputs DQ0DQ15

Output Buffers

Y Gating

X Decoder

1,048,576 Bit Cell Matrix


06780J-1
Publication# 06780 Rev: J Amendment/0 Issue Date: May 1998

PRODUCT SELECTOR GUIDE


Family Part Number Speed Options VCC = 5.0 V 5% VCC = 5.0 V 10% -55 -55 55 55 40 -70 70 70 40 -90 90 90 45 -120 120 120 50 -150 150 150 65 -200 200 200 75 250 250 75 Am27C1024 -255

Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)

CONNECTION DIAGRAMS
DIP
VPP CE# (E#) DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 VSS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE# (G#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC DQ13 DQ14 DQ15 PGM# (P#) NC A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0
06780J-2

PLCC
DU (Note 2) PGM# (P#)

CE (E)

VCC

A15

6 DQ12 DQ11 DQ10 DQ9 DQ8 VSS NC DQ7 DQ6 DQ5 DQ4 7 8 9 10 11 12 13 14 15 16

1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5

29 17 18 19 20 21 22 23 24 25 26 27 28 DQ3 DQ2 DQ1 DQ0 OE# (G#) A0 A1 A2 A3 DU (Note 2) A4

A14
06780J-3

VPP

Notes: 1. JEDEC nomenclature is in parenthesis. 2. Dont use (DU) for PLCC.

PIN DESIGNATIONS
A0A15 CE# (E#) = Address Inputs = Chip Enable Input

LOGIC SYMBOL

16 A0A15 DQ0DQ15 CE# (E#) PGM# (P#) OE# (G#)


06780J-4

DQ0DQ15 = Data Input/Outputs OE# (G#) PGM# (P#) VCC VPP VSS NC 2 = Output Enable Input = Program Enable Input = VCC Supply Voltage = Program Voltage Input = Ground = No Internal Connection Am27C1024

NC

16

ORDERING INFORMATION UV EPROM Products


AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

AM27C1024

-55

B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In VOLTAGE TOLERANCE 5 = VCC 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (40C to +85C) E = Extended (55C to +125C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION Am27C1024 1 Megabit (64 K x 16-Bit) CMOS UV EPROM

Valid Combinations Valid Combinations AM27C1024-55 VCC = 5.0 V 5% AM27C1024-55 VCC = 5.0 V 10% AM27C1024-70 AM27C1024-90 AM27C1024-120 AM27C1024-150 AM27C1024-200 AM27C1024-255 VCC = 5.0 V 5% DC, DCB, DI, DIB DC, DCB, DI, DIB, DE, DEB DC, DCB, DI, DIB DC5, DC5B, DI5, DI5B Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am27C1024

ORDERING INFORMATION OTP EPROM Products


AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

AM27C1024

-55

5 OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE 5 = VCC 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (40C to +85C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION Am27C1024 1 Megabit (64 K x 16-Bit) CMOS OTP EPROM

Valid Combinations Valid Combinations AM27C1024-55 VCC = 5.0 V 5% AM27C1024-55 VCC = 5.0 V 10% AM27C1024-70 AM27C1024-90 AM27C1024-120 AM27C1024-150 AM27C1024-200 AM27C1024-255 VCC = 5.0 V 5% JC, PC, JI, PI PC5, PI5, JC5, JI5 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am27C1024

FUNCTIONAL DESCRIPTION Device Erasure


In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lampwavelength of 2537 with intensity of 12,000 W/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 , such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance.

VPP = 12.75 V 0.25 V and PGM# LOW will program that particular device. A high-level CE# input inhibits the other devices from being programmed.

Program Verify
A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# and CE# at VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.

Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0 DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit.

Device Programming
Upon delivery, or after each erasure, the device has all of its bits in the ONE, or HIGH state. ZEROs are loaded into the device through the programming procedure. The device enters the programming mode when 12.75 V 0.25 V is applied to the VPP pin, and CE# and PGM# are at VIL. For programming, the data to be programmed is applied 16 bits in parallel to the data pins. The flowchar t in the Programming section of the EPROM Products Data Book (Section 5, Figure 5-1) shows AMDs Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 s programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 5 of the EPROM Products Data Book for additional programming information and specifications.

Read Mode
To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACC tOE. Refer to the Switching Waveforms section for the timing diagram.

Standby Mode
The device enters the CMOS standby mode when CE# is at VCC 0.3 V. Maximum VCC current is reduced to 100 A. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.

Output OR-Tieing
To accommodate multiple memory connections, a two-line control function provides: s Low memory power dissipation, and s Assurance that output bus contention will not occur. CE# should be decoded and used as the primary device-selecting function, while OE# be made a common

Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#, all like inputs of the devices may be common. A TTL low-level program pulse applied to one devices CE# input with

Am27C1024

connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.

System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.

MODE SELECT TABLE


Mode Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Autoselect (Note 3) Manufacturer Code Device Code CE# VIL X VIH VCC 0.3 V VIL VIL VIH VIL VIL OE# VIL VIH X X X VIL X VIL VIL PGM# X X X X VIL VIH X VIH VIH A0 X X X X X X X VIL VIH A9 X X X X X X X VH VH VPP X X X X VPP VPP VPP X X Outputs DOUT High Z High Z High Z DIN DOUT High Z 01h 8Ch

Notes: 1. VH = 12.0 V 0.5 V. 2. X = Either VIH or VIL. 3. A1A8 and A1015 = VIL 4. See DC Programming Characteristics for VPP voltage during programming.

Am27C1024

ABSOLUTE MAXIMUM RATINGS


Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . 65C to +125C All Other Products . . . . . . . . . . . . . . 65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . 55C to +125C Voltage with Respect to VSS All pins except A9, VPP, VCC . . 0.6 V to VCC + 0.6 V A9 and VPP (Note 2) . . . . . . . . . . . . . 0.6 V to 13.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . 0.6 V to 7.0 V

OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . .55C to +125C Supply Read Voltages VCC for 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.

Notes:
1. Minimum DC voltage on input or I/O pins 0.5 V. During voltage transitions, the input may overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on A9 is 0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to 2.0 V for periods of up to 20 ns. A9 and VPP must not exceed +13.5 V at any time. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability.

Am27C1024

DC CHARACTERISTICS over operating range (unless otherwise specified)


Parameter Symbol VOH VOL VIH VIL ILI ILO ICC1 Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage C/I Devices Input Load Current Output Leakage Current VCC Active Current (Note 2) VIN = 0 V to VCC VOUT = 0 V to VCC CE# = VIL, f = 10 MHz, IOUT = 0 mA CE# = VIH CE# = VCC 0.3 V CE# = OE# = VIL, VPP = VCC C/I Devices E Devices E Devices Test Conditions IOH = 400 A IOL = 2.1 mA 2.0 0.5 Min 2.4 0.45 VCC + 0.5 +0.8 1.0 A 5.0 5.0 50 mA 60 1.0 100 100 mA A A A Max Unit V V V V

ICC2 ICC3 IPP1

VCC TTL Standby Current VCC CMOS Standby Current VPP Supply Current (Read)

Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied. Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Minimum DC Input Voltage is 0.5 V. During transitions, the inputs may overshoot to 2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

40 35 30 25 20 1 2 3 4 5 6 7 Frequency in MHz 8 9 10

40 35 30 25 20 75 50 55

Supply Current in mA

Supply Current in mA

0 25 50 75 100 125 150 Temperature in C


06780J-6

06780J-5

Figure 1.

Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25C

Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz

Am27C1024

TEST CONDITIONS
5.0 V

Table 1.
Test Condition Output Load

Test Specifications
-55 All others 1 TTL gate 30 20 0.03.0 0.452.4 1.5 1.5 0.8, 2.0 0.8, 2.0 100 pF ns V V V Unit

Device Under Test CL 6.2 k

2.7 k

Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels

Note: Diodes are IN3064 or equivalents.


06780J-7

Input timing measurement reference levels Output timing measurement reference levels

Figure 3.

Test Setup

SWITCHING TEST WAVEFORM


3V 1.5 V 0V Input Output Test Points 1.5 V 0.8 V 0.45 V Input Output 2.4 V 2.0 V Test Points 0.8 V 2.0 V

Note: For CL = 30 pF.

Note: For CL = 100 pF.

06780J-8

KEY TO SWITCHING WAVEFORMS


WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Dont Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS

KS000010-PAL

Am27C1024

AC CHARACTERISTICS
Parameter Symbols JEDEC tAVQV tELQV tGLQV tEHQZ tGHQZ Standard tACC tCE tOE tDF (Note 2) Description Address to Output Delay Chip Enable to Output Delay Test Setup CE#, OE# = VIL OE# = VIL Max Max Max Max -55 55 55 40 30 -70 70 70 40 30 Am27C1024 -90 90 90 45 40 -120 -150 -200 -255 120 120 50 50 150 150 65 50 200 200 75 50 250 250 75 50 Unit ns ns ns ns

Output Enable to Output Delay CE# = VIL Chip Enable High or Output Enable High to Output High Z, Whichever Occurs First Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First

tAXQX

tOH

Min

ns

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:

1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is sampled and not 100% tested. 3. Switching characteristics are over operating range, unless otherwise specified. 4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS
2.4 Addresses 0.45 CE# tCE OE# tOE High Z tACC (Note 1) tOH Valid Output High Z
06780J-9

2.0 0.8

Addresses Valid

2.0 0.8

tDF (Note 2)

Output

Notes: 1. OE# may be delayed up to tACC tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE
Parameter Description Input Capacitance Output Capacitance CDV040 Test Conditions VIN = 0 VOUT = 0 Typ 9 12 Max 12 14 PD 040 Typ 7 11 Max 12 14 PL 044 Typ 8 11 Max 10 14 Unit pF pF

Parameter Symbol CIN COUT

Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f = 1 MHz.

10

Am27C1024

PHYSICAL DIMENSIONS* CDV04040-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D CENTER PLANE
1

UV Lens .565 .605

INDEX AND TERMINAL NO. 1 I.D. AREA

TOP VIEW DATUM D CENTER PLANE 2.035 2.080 BASE PLANE SEATING PLANE .160 .220 .015 .060 .125 .200 .300 BSC .045 .065 .014 .026 .600 BSC .100 BSC .008 .018 .700 MAX

94 105

.005 MIN

SIDE VIEW

END VIEW
16-000038H-3 CDV040 DF11 3-30-95 ae

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 04040-Pin Plastic Dual In-Line Package (measured in inches)


2.040 2.080 40 21 .530 .580 20 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .008 .015 .600 .625

Pin 1 I.D.

SEATING PLANE .120 .160 .090 .110 .014 .022 .015 .060

16-038-SC_AF PD 040 DG76 2-28-95 ae

Am27C1024

11

PHYSICAL DIMENSIONS PL 04444-Pin Plastic Leaded Chip Carrier (measured in inches)


.685 .695 .042 .056 .062 .083

.650 .656

Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630

.013 .021

.026 .032

.050 REF

.009 .015

.090 .120 .165 .180

SEATING PLANE

TOP VIEW

SIDE VIEW

16-038-SQ PL 044 EC80 11.3.97 lv

REVISION SUMMARY FOR AM27C1024 Revision J


Global Changed formatting to match current data sheets. Distinctive Characteristics

Low power consumption: Changed 100 A to 20 A.

Trademarks Copyright 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

12

Am27C1024

fax id: 1047

CY7C109 CY7C1009

128K x 8 Static RAM


Features
High speed tAA = 10 ns Low active power 1017 mW (max., 12 ns) Low CMOS standby power 55 mW (max.), 4 mW (Low power version) 2.0V Data Retention (Low power version) Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1, CE2, and OE options active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A 0 through A16). Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE 2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE 2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C109 is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009 is available in a 300-mil-wide SOJ package. The CY7C1009 and CY7C109 are functionally equivalent in all other respects.

Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE 1), an

Logic Block Diagram

Pin Configurations
SOJ Top View
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3

I/O0
INPUT BUFFER

A0 A1 A2 A3 A4 A5 A6 A7 A8

I/O1
ROW DECODER

I/O2
SENSE AMPS 512 x 256 x 8 ARRAY

1092 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 1093

I/O3 I/O4 I/O5

CE1 CE2 WE OE

COLUMN DECODER

POWER DOWN

I/O6 I/O7

TSOP I Top View (not to scale)

A9 A 10 A 11 A 12 A 13 A14 A15 A16

1091

Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Maximum CMOS Standby Current (mA) Low Power Version
Shaded areas contain preliminary information.

7C109-10 7C1009-10 10 195 10 2

7C109-12 7C1009-12 12 185 10 2

7C109-15 7C1009-15 15 155 10 2

7C109-20 7C1009-20 20 140 10

7C109-25 7C1009-25 25 135 10

7C109-35 7C1009-35 35 125 10

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600 June 30, 1998

CY7C109 CY7C1009
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. 65C to +150C Ambient Temperature with Power Applied ............................................. 55C to +125C Supply Voltage on VCC to Relative GND[1] .... 0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................0.5V to VCC + 0.5V DC Input Voltage[1].................................0.5V to VCC + 0.5V Current into Outputs (LOW) ......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA

Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C 40C to +85C VCC 5V 10% 5V 10%

Electrical Characteristics Over the Operating Range[3]


7C109-10 7C1009-10 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current TTL Inputs Automatic CE Power-Down Current CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC 0.3V, or CE 2 < 0.3V, VIN > VCC 0.3V, or VIN < 0.3V, f=0 L Test Conditions VCC = Min., IOH = 4.0 mA VCC = Min., IOL = 8.0 mA 2.2 0.3 1 5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 300 195 2.2 0.3 1 5 Max. 7C109-12 7C1009-12 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 300 185 2.2 0.3 1 5 Max. 7C109-15 7C100915 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 300 155 Max. Unit V V V V A A mA mA

ISB1

45

45

40

mA

ISB2

10 2

10 2

10 2

mA

Shaded areas contain preliminary information.

CY7C109 CY7C1009
Electrical Characteristics Over the Operating Range (continued)
7C109-20 7C1009-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current TTL Inputs Automatic CE Power-Down Current CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < V IL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC 0.3V, or CE2 < 0.3V, VIN > VCC 0.3V, or VIN < 0.3V, f=0 Test Conditions VCC = Min., IOH = 4.0 mA VCC = Min., IOL = 8.0 mA 2.2 0.3 1 5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 300 140 2.2 0.3 1 5 Max. 7C109-25 7C1009-25 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 300 135 2.2 0.3 1 5 Max. 7C109-35 7C1009-35 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 300 125 Max. Unit V V V V A A mA mA

ISB1

30

30

25

mA

ISB2

10

10

10

mA

Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 8 Unit pF pF

Notes: 1. VIL (min.) = 2.0V for pulse durations of less than 20 ns. 2. TA is the instant on case temperature. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms


5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 R1 480 R1 480 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3ns 3.0V 90% 10% 90% 10% 3 ns ALL INPUT PULSES

1093 1094

Equivalent to:

THVENIN EQUIVALENT 167 1.73V OUTPUT

CY7C109 CY7C1009
Switching Characteristics[3, 5] Over the Operating Range
7C109-10 7C1009-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE1 LOW to Low Z, CE2 HIGH to Low Z CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[7] [6, 7] [7] [6, 7]

7C109-12 7C1009-12 Min. 12 Max.

7C109-15 7C1009-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 ns ns ns ns ns ns ns ns ns 15 ns

Description

Min. 10

Max.

10 3 10 5 0 5 3 5 0 10 0 3 0 3

12 12 6 6 6

CE1 HIGH to High Z, CE2 LOW to High Z

12

WRITE CYCLE[8,9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE 10 8 8 0 0 8 6 0 3 5 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 7 ns ns ns ns ns ns ns ns ns ns

Shaded areas contain preliminary information. Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and TSD.

CY7C109 CY7C1009
Switching Characteristics[3, 5] Over the Operating Range
7C109-20 7C1009-20 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE1 LOW to Low Z, CE2 HIGH to Low Z CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z
[6, 7] [7] [6, 7]

7C109-25 7C1009-25 Min. 25 Max.

7C109-35 7C1009-35 Min. 35 Min. Unit ns 35 5 35 15 0 15 5 15 0 ns ns ns ns ns ns ns ns ns 35 ns

Description

Min. 20

Max.

20 3 20 8 0 8 3 8 0 20 0 5 0 5

25 25 10 10 10

CE1 HIGH to High Z, CE2 LOW to High Z

25

WRITE CYCLE[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE 20 15 15 0 0 12 10 0 3 8 25 20 20 0 0 15 15 0 5 10 35 25 25 0 0 20 20 0 5 15 ns ns ns ns ns ns ns ns ns ns

Data Retention Characteristics Over the Operating Range (L Version Only)


Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed V CC + 0.5V VCC = V DR = 2.0V, CE1 > VCC 0.3V or CE2 < 0.3V, VIN > VCC 0.3V or VIN < 0.3V Min. 2.0 50 0 tRC Max Unit V A ns ns

Shaded areas contain preliminary information.

CY7C109 CY7C1009
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR CE
109-5

VDR > 2V

4.5V tR

Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1096

Read Cycle No. 2 (OE Controlled)[11, 12]

ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB
1097

HIGH IMPEDANCE

ICC

Notes: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

CY7C109 CY7C1009
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID
1098

tHA

tHD

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]


tWC ADDRESS tSCE CE1

CE2 tSCE tAW tSA WE tPWE tHA

OE tSD DATA I/O NOTE 15 tHZOE


Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.

tHD

DATAIN VALID
1099

CY7C109 CY7C1009
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
tWC ADDRESS tSCE CE1

CE2 tSCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tLZWE
1099

tHA tPWE

tHD

Note: 15. During this period the I/Os are in the output state and input signals should not be applied.

Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)

CY7C109 CY7C1009
Ordering Information
Speed (ns) 10 Ordering Code CY7C109-10VC CY7C1009-10VC CY7C1009L-10VC 12 CY7C109-12VC CY7C1009-12VC CY7C1009L-12VC CY7C109-12ZC 15 CY7C10915VC CY7C1009-15VC CY7C1009L-15VC CY7C10915ZC 20 CY7C10920VC CY7C1009-20VC CY7C10920VI CY7C10920ZC CY7C109-20ZI 25 CY7C10925VC CY7C1009-25VC CY7C10925VI CY7C10925ZC CY7C109-25ZI 35 CY7C10935VC CY7C1009-35VC CY7C10935VI
Shaded areas contain preliminary information.

Package Name V33 V32 V32 V33 V32 V32 Z32 V33 V32 V32 Z32 V33 V32 V33 Z32 Z32 V33 V32 V33 Z32 Z32 V33 V32 V33

Package Type 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ

Operating Range Commercial

Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial

Document #: 3800140J

CY7C109 CY7C1009
Package Diagrams
32-Lead (300-Mil) Molded SOJ V32

51-85041-A

32-Lead (400-Mil) Molded SOJ V33

51-85033-A

10

CY7C109 CY7C1009
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32

51-85056-B

Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

a
FEATURES Autocalibrating On-Chip Sample-Hold Function Parallel Output Format 16 Bits No Missing Codes 1 LSB INL 97 dB THD 90 dB S/(N+D) 1 MHz Full Power Bandwidth
VIN 15 AGND SENSE 14 VREF 16 AGND 13 INPUT BUFFERS

16-Bit 100 kSPS Sampling ADC AD676


FUNCTIONAL BLOCK DIAGRAM
ANALOG CHIP 16-BIT DAC COMP

CAL DAC LOGIC & TIMING LEVEL TRANSLATORS

DIGITAL CHIP SAR CAL 8 SAMPLE 9 MICRO-CODED CONTROLLER PAT GEN ALU RAM L A T C H

7 BUSY 1 6 19 28 BIT 1 BIT 16

PRODUCT DESCRIPTION

CLK 10

The AD676 is a multipurpose 16-bit parallel output analog-todigital converter which utilizes a switched-capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 s total conversion time). Overall performance is optimized by digitally correcting internal nonlinearities through on-chip autocalibration. The AD676 circuitry is segmented onto two monolithic chips a digital control chip fabricated on Analog Devices DSP CMOS process and an analog ADC chip fabricated on our BiMOS II process. Both chips are contained in a single package. The AD676 is specified for ac (or dynamic) parameters such as S/(N+D) Ratio, THD and IMD which are important in signal processing applications. In addition, dc parameters are specified which are important in measurement applications.

AD676

The AD676 operates from +5 V and 12 V supplies and typically consumes 360 mW during conversion. The digital supply (VDD) is separated from the analog supplies (VCC, VEE) for reduced digital crosstalk. An analog ground sense is provided for the analog input. Separate analog and digital grounds are also provided. The AD676 is available in a 28-pin plastic DIP or 28-pin sidebrazed ceramic package. A serial-output version, the AD677, is available in a 16-pin 300 mil wide ceramic or plastic package.

REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

AD676SPECIFICATIONS
AC SPECIFICATIONS (T
Parameter Total Harmonic Distortion (THD) @ 83 kSPS, TMIN to TMAX @ 100 kSPS, +25C @ 100 kSPS, TMIN to TMAX Signal-to-Noise and Distortion Ratio (S/(N+D))2, 3 @ 83 kSPS, TMIN to TMAX @ 100 kSPS, +25C @ 100 kSPS, TMIN to TMAX Peak Spurious or Peak Harmonic Component Intermodulation Distortion (IMD)4 2nd Order Products 3rd Order Products Full Power Bandwidth Noise 85
2

MIN

to TMAX, VCC = +12 V

5%, VEE = 12 V
Min

5%, VDD = +5 V
Max 88 0.004

10%)1
Min AD676K/B Typ 97 0.0014 97 0.0014 92 0.0025 87 90 90 86 98 102 98 1 160 Max 90 0.003 Units dB % dB % dB % dB dB dB dB dB dB MHz V rms

AD676J/A Typ 96 0.0016 96 0.0016 92 0.0025 89 89 86 98 102 98 1 160

DIGITAL SPECIFICATIONS (for all grades T


Parameter LOGIC INPUTS VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current IIL Low Level Input Current CIN Input Capacitance LOGIC OUTPUTS VOH High Level Output Voltage VOL Low Level Output Voltage

MIN

to TMAX, VCC = +12 V

5%, VEE = 12 V
Min 2.4 0.3 10 10 10 Typ

5%, VDD = +5 V
Max VDD + 0.3 0.8 +10 +10

10%)
Units V V A A pF V V V

Test Conditions

VIH = VDD VIL = 0 V

IOH = 0.1 mA IOH = 0.5 mA IOL = 1.6 mA

VDD 1 V 2.4 0.4

NOTES 1 VREF = 10.0 V, (Conversion Rate (fs) = 83 kSPS, f IN = 1.0 kHz, VIN = 0.05 dB, Bandwidth = fs/2 unless otherwise indicated. All measurements referred to a 0 dB (20 V p-p) input signal. Values are post-calibration. 2 For other input amplitudes, refer to Figure 13. 3 For other input ranges/voltages reference values see Figure 12. 4 fa = 1008 Hz. fb = 1055 Hz. See Definition of Specifications section and Figure 15. Specifications subject to change without notice.

REV. A

AD676 DC SPECIFICATIONS (T
Parameter TEMPERATURE RANGE J, K Grades A, B Grades ACCURACY Resolution Integral Nonlinearity (INL) @ 83 kSPS, TMIN to TMAX @ 100 kSPS, +25C @ 100 kSPS, TMIN to TMAX Differential Nonlinearity (DNL)No Missing Codes Bipolar Zero Error2 (at Nominal Supplies) Gain Error (at Nominal Supplies) @ 83 kSPS2 @ 100 kSPS, +25C @ 100 kSPS2 Temperature Drift, Bipolar Zero3 J, K Grades A, B Grades Temperature Drift, Gain3 J, K Grades A, B Grades VOLTAGE REFERENCE INPUT RANGE4 (VREF) ANALOG INPUT5 Input Range (VIN) Input Impedance Input Settling Time Input Capacitance During Sample Aperture Delay Aperture Jitter POWER SUPPLIES Power Supply Rejection VCC = +12 V 5% VEE = 12 V 5% VDD = +5 V 10% Operating Current ICC IEE IDD Power Consumption
MIN

to TMAX, VCC = +12 V

5%, VEE = 12 V
Min 0 40 16 1 1 2 16 0.005 0.005 0.005 0.01

5%, VDD = +5 V
Max +70 +85

1O%)1
Min 0 40 16 1 1 2 16 0.005 0.005 0.005 0.01 0.0015 0.003 0.0015 0.003 1.5 AD676K/B Typ Max +70 +85 Units C C Bits LSB LSB LSB Bits % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR 10 VREF * 2 50* 6 100 V V s pF ns ps

AD676J/A Typ

0.0015 0.003 0.0015 0.003 5 10 VREF * 2 50* 6 100 5

1 1 1 14.5 14.5 2 360 18 18 5 480

1 1 1 14.5 14.5 2 360 18 18 5 480

LSB LSB LSB mA mA mA mW

NOTES 1 VREF = 5.0 V, Conversion Rate = 83 kSPS unless otherwise noted. Values are post-calibration. 2 Values shown apply to any temperature from TMIN to TMAX after calibration at that temperature. 3 Values shown are based upon calibration at +25C with no additional calibration at temperature. Values shown are the worst case variation from the value at +25 C. 4 See APPLICATIONS section for recommended voltage reference circuit, and Figure 12 for dynamic performance with other reference voltage values. 5 See APPLICATIONS section for recommended input buffer circuit. *For explanation of input characteristics, see ANALOG INPUT section. Specifications subject to change without notice.

REV. A

AD676 TIMING SPECIFICATIONS(T


Parameter Conversion Time CLK Period3 Calibration Time Sampling Time (Included in tC) CAL to BUSY Delay BUSY to SAMPLE Delay SAMPLE to BUSY Delay CLK HIGH4 CLK LOW4 SAMPLE LOW to 1st CLK Delay SAMPLE LOW Output Delay Status Delay CAL HIGH Time
2

MIN

to TMAX VCC = +12 V


Symbol tC tCLK tCT tS tCALB tBS tSB tCH tCL tSC tSL tOD tSD tCALH

5%, VEE = 12 V
Min 10 480 2

5%, VDD = +5 V
Typ

10%, VREF = 10.0 V)1


Max 1000 85,530 Units s ns tCLK s ns s ns ns ns ns ns ns ns ns

75 2 15 50 50 50 100 125 50 50

150 100

200

NOTES 1 See the CONVERSION CONTROL and AUTOCALIBRATION sections for detailed explanations of the above timing. 2 Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion time is specified to account for the droop of the internal sample/hold function. Longer conversion times may degrade performance. See General Conversion Guidelines for additional explanation of maximum conversion time. 3 580 ns is recommended for optimal accuracy over temperature. 4 tCH + t CL = tCLK and must be greater than 480 ns.
t CALH
CAL

t CALB
BUSY

t CT t CLK

t CH

t OD

CLK

t CL

Figure 1. Calibration Timing

tS
SAMPLE (INPUT) CLK (INPUT) BIT 1 BIT 16 (OUTPUTS)

tSL

tC
SAMPLE (INPUT)
13 14 15 16 17

tS

tSL

tC

tS

tSC
1 2 3 4 5

t CL t CLK
(PREVIOUS CONVERSION)

tSC
1 2 3 4 5

t CL
13 14 15 16 17

t CH
(NEW DATA)

CLK (INPUT) BIT 1 BIT 16 (OUTPUTS)

t CLK
(PREVIOUS CONVERSION)

t CH
(NEW DATA)

t OD
BUSY (OUTPUT)

t OD tSD
BUSY (OUTPUT)

tBS

t BS

tSD

tSB

tSB

Figure 2a. General Conversion Timing

Figure 2b. Continuous Conversion Timing

REV. A

AD676
ORDERING GUIDE

Model AD676JD AD676KD AD676AD AD676BD

Temperature Range1 0C to +70C 0C to +70C 40C to +85C 40C to +85C

S/(N+D) 85 dB 87 dB 85 dB 87 dB

Max INL 1.5 LSB 1.5 LSB

Package Description Ceramic 28-Pin DIP Ceramic 28-Pin DIP Ceramic 28-Pin DIP Ceramic 28-Pin DIP

Package Option2 D-28 D-28 D-28 D-28

NOTES 1 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the AD676/883 data sheet. 2 D = Ceramic DIP.

ABSOLUTE MAXIMUM RATINGS*

VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +26.4 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +18 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . 18 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V Digital Inputs to DGND . . . . . . . . . . . . . . . . . . 0 V to +5.5 V Analog Inputs, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . (VCC + 0.3 V) to (VEE 0.3 V) Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C, 10 sec Storage Temperature . . . . . . . . . . . . . . . . . . 65C to +150C
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

The AD676 features input protection circuitry consisting of large distributed diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD676 has been classified as a Category 1 Device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment, and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam discharged to the destination socket before devices are removed. For further information on ESD Precaution. Refer to Analog Devices ESD Prevention Manual.

WARNING!
ESD SENSITIVE DEVICE

REV. A

AD676
PIN DESCRIPTION

Pin 16 7 8 9

Name BIT 11-BIT 16 BUSY CAL SAMPLE

Type DO DO DI DI

Description BIT 11BIT 16 represent the six LSBs of data. Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress. BUSY should be buffered when capacitively loaded. Calibration Control Pin (Asynchronous). VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE controls the state of the internal sample-hold amplifier and the falling edge initiates conversion (see Conversion Control paragraph). During calibration, SAMPLE should be held LOW. If HIGH during calibration, diagnostic information will appear on the two LSBs (Pins 5 and 6). Master Clock Input. The AD676 requires 17 clock cycles to execute a conversion. Digital Ground. +12 V Analog Supply Voltage. Analog Ground. Analog Ground Sense. Analog Input Voltage. External Voltage Reference Input. 12 V Analog Supply Voltage. Note: the lid of the ceramic package is internally connected to VEE. +5 V Logic Supply Voltage. BIT 1BIT 10 represent the ten MSB of data.

10 11 12 13 14 15 16 17 18 1928

CLK DGND VCC AGND AGND SENSE VIN VREF VEE VDD BIT 1BIT 10

DI P P P/AI AI AI AI P P DO

Type: AI = Analog Input DI = Digital Input DO = Digital Output P = Power

BIT 11 1 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 (LSB) BUSY CAL SAMPLE 2 3 4 5 6 7 8 9

28 BIT 10 27 BIT 9 26 BIT 8 25 BIT 7 24 BIT 6

VIN 15 AGND SENSE 14 VREF 16 AGND 13 INPUT BUFFERS 16-BIT DAC

ANALOG CHIP COMP

CAL DAC LOGIC & TIMING

AD676
TOP VIEW (Not to Scale)

23 BIT 5 22 BIT 4 21 BIT 3 20 BIT 2 19 BIT 1 (MSB) 18 VDD 17 VEE 16 VREF 15 VIN
CAL 8 SAMPLE 9 CLK 10 MICRO-CODED CONTROLLER LEVEL TRANSLATORS

DIGITAL CHIP SAR PAT GEN ALU RAM L A T C H

7 BUSY 1 6 19 28 BIT 1 BIT 16

CLK 10 DGND 11 VCC 12 AGND 13 AGND SENSE 14

AD676

Package Pinout

Functional Block Diagram

REV. A

Definition of SpecificationsAD676
NYQUIST FREQUENCY BANDWIDTH

An implication of the Nyquist sampling theorem, the Nyquist frequency of a converter is that input frequency which is one half the sampling frequency of the converter.
TOTAL HARMONIC DISTORTION

The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.
INTERMODULATION DISTORTION (IMD)

Total harmonic distortion (THD) is the ratio of the rms sum of the harmonic components to the rms value of a full-scale input signal and is expressed in percent (%) or decibels (dB). For input signals or harmonics that are above the Nyquist frequency, the aliased components are used.
SIGNAL-TO-NOISE PLUS DISTORTION RATIO

Signal-to-noise plus distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.
GAIN ERROR

With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa fb), and the third order terms are (2 fa + fb), (2 fa fb), (fa + 2 fb) and (fa 2 fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals applied to the converter are of equal amplitude, and the peak value of their sum is 0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal.
APERTURE DELAY

The last transition should occur at an analog value 1.5 LSB below the nominal full scale (4.99977 volts for a 5 V range). The gain error is the deviation of the actual difference between the first and last code transition from the ideal difference between the first and last code transition.
BIPOLAR ZERO ERROR

Aperture delay is the time required after SAMPLE pin is taken LOW for the internal sample-hold of the AD676 to open, thus holding the value of VlN.
APERTURE JITTER

Bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.
DIFFERENTIAL NONLINEARITY (DNL)

Aperture jitter is the variation in the aperture delay from sample to sample.
POWER SUPPLY REJECTION

In an ideal ADC, code transitions are one LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
INTEGRAL NONLINEARITY (INL)

DC variations in the power supply voltage will affect the overall transfer function of the ADC, resulting in zero error and gain error changes. Power supply rejection is the maximum change in either the bipolar zero error or gain error value. Additionally, there is another power supply variation to consider. AC ripple on the power supplies can couple noise into the ADC, resulting in degradation of dynamic performance. This is displayed in Figure 16.
INPUT SETTLING TIME

The ideal transfer function for an ADC is a straight line bisecting the center of each code drawn between zero and full scale. The point used as zero occurs 1/2 LSB before the most negative code transition. Full scale is defined as a level 1.5 LSB beyond the most positive code transition. Integral nonlinearity is the worst-case deviation of a code center average from the straight line.

Settling time is a function of the SHAs ability to track fast slewing signals. This is specified as the maximum time required in track mode after a full-scale step input to guarantee rated conversion accuracy.

REV. A

AD676
FUNCTIONAL DESCRIPTION

The AD676 is a multipurpose 16-bit analog-to-digital converter and includes circuitry which performs an input sample/hold function, ground sense, and autocalibration. These functions are segmented onto two monolithic chipsan analog signal processor and a digital controller. Both chips are contained within the AD676 package. The AD676 employs a successive-approximation technique to determine the value of the analog input voltage. However, instead of the traditional laser-trimmed resistor-ladder approach, this device uses a capacitor-array, charge redistribution technique. Binary-weighted capacitors subdivide the input sample to perform the actual analog-to-digital conversion. The capacitor array eliminates variation in the linearity of the device due to temperature-induced mismatches of resistor values. Since a capacitor array is used to perform the data conversions, the sample/hold function is included without the need for additional external circuitry. Initial errors in capacitor matching are eliminated by an autocalibration circuit within the AD676. This circuit employs an on-chip microcontroller and a calibration DAC to measure and compensate capacitor mismatch errors. As each error is determined, its value is stored in on-chip memory (RAM). Subsequent conversions use these RAM values to improve conversion accuracy. The autocalibration routine may be invoked at any time. Autocalibration insures high performance while eliminating the need for any user adjustments and is described in detail below. The microcontroller controls all of the various functions within the AD676. These include the actual successive approximation algorithm, the autocalibration routine, the sample/hold operation, and the internal output data latch.
AUTOCALIBRATION

LOW and completes in 85,530 clock cycles, indicated by BUSY going LOW. During calibration, it is preferable for SAMPLE to be held LOW. If SAMPLE is HIGH, diagnostic data will appear on Pins 5 and 6. This data is of no value to the user. The AD676 requires one clock cycle after BUSY goes LOW to complete the calibration cycle. If this clock cycle is not provided, it will be taken from the first conversion, likely resulting in first conversion error. In most applications, it is sufficient to calibrate the AD676 only upon power-up, in which case care should be taken that the power supplies and voltage reference have stabilized first. If not calibrated, the AD676 accuracy may be as low as 10 bits.
CONVERSION CONTROL

The AD676 is controlled by two signals: SAMPLE and CLK, as shown in Figures 2a and 2b. It is assumed that the part has been calibrated and the digital I/O pins have the levels shown at the start of the timing diagram. A conversion consists of an input acquisition followed by 17 clock pulses which execute the 16-bit internal successive approximation routine. The analog input is acquired by taking the SAMPLE line HIGH for a minimum sampling time of tS. The actual sample taken is the voltage present on VIN one aperture delay after the SAMPLE line is brought LOW, assuming the previous conversion has completed (signified by BUSY going LOW). Care should he taken to ensure that this negative edge is well defined and jitter free in ac applications to reduce the uncertainty (noise) in signal acquisition. With SAMPLE going LOW, the AD676 commits itself to the conversionthe input at VIN is disconnected from the internal capacitor array, BUSY goes HIGH, and the SAMPLE input will be ignored until the conversion is completed (when BUSY goes LOW). SAMPLE must be held LOW for a minimum period of time tSL. A period of time tSC after bringing SAMPLE LOW, the 17 CLK cycles are applied; CLK pulses that start before this period of time are ignored. BUSY goes HIGH tSB after SAMPLE goes LOW, signifying that a conversion is in process, and remains HIGH until the conversion is completed. BUSY goes LOW during the 17th CLK cycle at the point where the data outputs have changed and are valid. The AD676 will ignore CLK after BUSY has gone LOW and the output data will remain constant until a new conversion is completed. The data can, therefore, be read any time after BUSY goes LOW and before the 17th CLK of the next conversion (see Figures 2a and 2b). The section on Microprocessor Interfacing discusses how the AD676 can be interfaced to a 16-bit databus. Typically BUSY would be used to latch the AD676 output data into buffers or to interrupt microprocessors or DSPs. It is recommended that the capacitive load on BUSY be minimized by driving no more than a single logic input. Higher capacitive loads such as cables or multiple gates may degrade conversion quality unless BUSY is buffered.

The AD676 achieves rated performance without the need for user trims or adjustments. This is accomplished through the use of on-chip autocalibration. In the autocalibration sequence, sample/hold offset is nulled by internally connecting the input circuit to the ground sense circuit. The resulting offset voltage is measured and stored in RAM for later use. Next, the capacitor representing the most significant bit (MSB) is charged to the reference voltage. This charge is then transferred to a capacitor of equal size (composed of the sum of the remaining lower weight bits). The difference in the voltage that results and the reference voltage represents the amount of capacitor mismatch. A calibration digital-to-analog converter (DAC) adds an appropriate value of error correction voltage to cancel this mismatch. This correction factor is also stored in RAM. This process is repeated for each of the capacitors representing the remaining top eight bits. The accumulated values in RAM are then used during subsequent conversions to adjust conversion results accordingly. As shown in Figure 1, when CAL is taken HIGH the AD676 internal circuitry is reset, the BUSY pin is driven HIGH, and the ADC prepares for calibration. This is an asynchronous hardware reset and will interrupt any conversion or calibration currently in progress. Actual calibration begins when CAL is taken

REV. A

AD676
CONTINUOUS CONVERSION

For maximum throughput rate, the AD676 can be operated in a continuous convert mode (see Figure 2b). This is accomplished by utilizing the fact that SAMPLE will no longer be ignored after BUSY goes LOW, so an acquisition may be initiated even during the HIGH time of the 17th CLK pulse for maximum throughput rate while enabling full settling of the sample/hold circuitry. If SAMPLE is already HIGH when BUSY goes LOW at the end of a conversion, then an acquisition is immediately initiated and tS and tC start from that time. Data from the previous conversion may be latched up to tSD before BUSY goes LOW or tOD after the rising edge of the 17th clock pulse. However, it is preferred that latching occur on or after the falling edge of BUSY. Care must he taken to adhere to the minimum/maximum timing requirements in order to preserve conversion accuracy.
GENERAL CONVERSION GUIDELINES

Figure 3 also illustrates the use of a counter (74HC393) to derive the AD676 SAMPLE command from the system clock when a continuous convert mode is desirable. Pin 9 (2QC) provides a 96 kHz sample rate for the AD676 when used with a 12.288 MHz system clock. Alternately, Pin 8 (2QD) could be used for a 48 kHz rate. If a continuous clock is used, then the user must avoid CLK edges at the instant of disconnecting VIN which occurs at the falling edge of SAMPLE (see tSC specification). The duty cycle of CLK may vary, but both the HIGH (tCH) and LOW (tCL ) phases must conform to those shown in the timing specifications. The internal comparator makes its decisions on the rising edge of CLK. To avoid a negative edge transition disturbing the comparators settling, tCL should be at least half the value of tCLK. To also avoid transitions disturbing the internal comparators settling, it is not recommended that the SAMPLE pin change state toward the end of a CLK cycle. During a conversion, internal dc error terms such as comparator voltage offset are sampled, stored on internal capacitors and used to correct for their corresponding errors when needed. Because these voltages are stored on capacitors, they are subject to leakage decay and so require refreshing. For this reason there is a maximum conversion time tC (1000 s). From the time SAMPLE goes HIGH to the completion of the 17th CLK pulse, no more than 1000 s should elapse for specified performance. However, there is no restriction to the maximum time between conversions. Output coding for the AD676 is twos complement, as shown in Table I. By inverting the MSB, the coding can be converted to offset binary. The AD676 is designed to limit output coding in the event of out-of-range inputs.
Table I. Output Coding

During signal acquisition and conversion, care should be taken with the logic inputs to avoid digital feedthrough noise. It is possible to run CLK continuously, even during the sample period. However, CLK edges during the sampling period, and especially when SAMPLE goes LOW, may inject noise into the sampling process. The AD676 is tested with no CLK cycles during the sampling period. The BUSY signal can be used to prevent the clock from running during acquisition, as illustrated in Figure 3. In this circuit BUSY is used to reset the circuitry which divides the system clock down to provide the AD676 CLK. This serves to interrupt the clock until after the input signal has been acquired, which has occurred when BUSY goes HIGH. When the conversion is completed and BUSY goes LOW, the circuit in Figure 3 truncates the 17th CLK pulse width which is tolerable because only its rising edge is critical.
11 3Q 4 1D 12.288MHz SYSTEM CLOCK 9 CLK CLR 1 7 BUSY SAMPLE 9 1Q 2 2D 5 10 CLK 2Q 7 3D 12

VIN >Full Scale Full Scale Full Scale 1 LSB Midscale + 1 LSB Midscale Midscale 1 LSB Full Scale + 1 LSB Full Scale <Full Scale

Output Code 011 . . . 11 011 . . . 11 011 . . . 10 000 . . . 01 000 . . . 00 111 . . . 11 100 . . . 01 100 . . . 00 100 . . . 00

74HC175
1 1CLK 13 2CLK 6 1QD 12 2CLR 2 1CLR

AD676

2QC 9 2QD 8

74HC393

Figure 3.

REV. A

AD676
POWER SUPPLIES AND DECOUPLING

The AD676 has three power supply input pins. VCC and VEE provide the supply voltages to operate the analog portions of the AD676 including the ADC and sample-hold amplifier (SHA). VDD provides the supply voltage which operates the digital portions of the AD676 including the data output buffers and the autocalibration controller. As with most high performance linear circuits, changes in the power supplies can produce undesired changes in the performance of the circuit. Optimally, well regulated power supplies with less than 1% ripple should be selected. The ac output impedance of a power supply is a complex function of frequency, and in general will increase with frequency. In other words, high frequency switching such as that encountered with digital circuitry requires fast transient currents which most power supplies cannot adequately provide. This results in voltage spikes on the supplies. If these spikes exceed the 5% tolerance of the 12 V supplies or the 10% limits of the +5 V supply, ADC performance will degrade. Additionally, spikes at frequencies higher than 100 kHz will also degrade performance. To compensate for the finite ac output impedance of the supplies, it is necessary to store reserves of charge in bypass capacitors. These capacitors can effectively lower the ac impedance presented to the AD676 power inputs which in turn will significantly reduce the magnitude of the voltage spikes. For bypassing to be effective, certain guidelines should be followed. Decoupling capacitors, typically 0.1 F, should be placed as closely as possible to each power supply pin of the AD676. It is essential that these capacitors be placed physically close to the IC to minimize the inductance of the PCB trace between the capacitor and the supply pin. The logic supply (VDD) should be decoupled to digital common and the analog supplies (Vcc and VEE) to analog common. The reference input is also considered as a power supply pin in this regard and the same decoupling procedures apply. These points are displayed in Figure 4.

Additionally, it is beneficial to have large capacitors (>47 F) located at the point where the power connects to the PCB with 10 F capacitors located in the vicinity of the ADC to further reduce low frequency ripple. In systems that will be subjected to particularly harsh environmental noise, additional decoupling may be necessary. RC-filtering on each power supply combined with dedicated voltage regulation can substantially decrease power supply ripple effects (this is further detailed in Figure 7).
BOARD LAYOUT

Designing with high resolution data converters requires careful attention to board layout. Trace impedance is a significant issue. A 1.22 mA current through a 0.5 trace will develop a voltage drop of 0.6 mV, which is 4 LSBs at the 16-bit level for a 10 V full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. Analog and digital signals should not share a common return path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog and digital ground planes are also desirable, with a single interconnection point at the AD676 to minimize interference between analog and digital circuitry. Analog signals should be routed as far as possible from digital signals and should cross them, if at all, only at right angles. A solid analog ground plane around the AD676 will isolate it from large switching ground currents. For these reasons, the use of wire wrap circuit construction will not provide adequate performance; careful printed circuit board construction is preferred.
GROUNDING

+5V

18 VDD DGND

AD676
AGND 13 VCC 12 VEE 17 VREF 11

0.1F

11

The AD676 has three grounding pins, designated ANALOG GROUND (AGND), DIGITAL GROUND (DGND) and ANALOG GROUND SENSE (AGND SENSE). The analog ground pin is the high quality ground reference point for the device, and should be connected to the analog common point in the system. AGND SENSE is intended to be connected to the input signal ground reference point. This allows for slight differences in level between the analog ground point in the system and the input signal ground point. However no more than 100 mV is recommended between the AGND and the AGND SENSE pins for specified performance.

0.1F 0.1F

SYSTEM DIGITAL COMMON

0.1F 12V 12V SYSTEM ANALOG COMMON

Figure 4. Grounding and Decoupling the AD676

10

REV. A

AD676
Using AGND SENSE to remotely sense the ground potential of the signal source can be useful if the signal has to be carried some distance to the A/D converter. Since all IC ground currents have to return to the power supply and no ground leads are free from resistance and inductance, there are always some voltage differences from one ground point in a system to another. Over distance this voltage difference can easily amount to several LSBs (in a 10 V input span, 16-bit system each LSB is about 0.15 mV). This would directly corrupt the A/D input signal if the A/D measures its input with respect to power ground (AGND) as shown in Figure 5a. To solve this problem the AD676 offers an AGND SENSE pin. Figure 5b shows how the AGND SENSE can be used to eliminate the problem in Figure 5a. Figure 5b also shows how the signal wires should be shielded in a noisy environment to avoid capacitive coupling. If inductive (magnetic) coupling is expected to be dominant such as where motors are present, twisted-pair wires should be used instead. The digital ground pin is the reference point for all of the digital signals that operate the AD676. This pin should be connected to the digital common point in the system. As Figure 4 illustrated, the analog and digital grounds should be connected together at one point in the system, preferably at the AD676.
AD676
VIN SOURCE VS V AGND TO POWER SUPPLY GND GROUND LEAD I GROUND > 0

VOLTAGE REFERENCE

The AD676 requires the use of an external voltage reference. The input voltage range is determined by the value of the reference voltage; in general, a reference voltage of n volts allows an input range of n volts. The AD676 is specified for both 10 V and 5.0 V references. A 10 V reference will typically require support circuitry operated from 15 V supplies; a 5.0 V reference may be used with 12 V supplies. Signal-to-noise performance is increased proportionately with input signal range. In the presence of a fixed amount of system noise, increasing the LSB size (which results from increasing the reference voltage) will increase the effective S/(N+D) performance. Figure 12 illustrates S/(N+D) as a function of reference voltage. In contrast, INL will be optimal at lower reference voltage values (such as 5 V) due to capacitor nonlinearity at higher voltage values. During a conversion, the switched capacitor array of the AD676 presents a dynamically changing current load at the voltage reference as the successive-approximation algorithm cycles through various choices of capacitor weighting. (See the following section Analog Input for a detailed discussion of the VREF input characteristics.) The output impedance of the reference circuitry must be low so that the output voltage will remain sufficiently constant as the current drive changes. In some applications, this may require that the output of the voltage reference be buffered by an amplifier with low impedance at relatively high frequencies. In choosing a voltage reference, consideration should be made for selecting one with low noise. A capacitor connected between REF IN and AGND will reduce the demands on the reference by decreasing the magnitude of high frequency components required to be sourced by the reference. Figures 6 and 7 represent typical design approaches.
+12V

Figure 5a. Input to the A/D Is Corrupted by IR Drop in Ground Leads: VIN = VS + V
SHIELDED CABLE

2 VIN 8

AD676
VIN AGND SENSE AGND TO POWER SUPPLY GND

CN 1.0F

AD586

6 + 10F

16 VREF

SOURCE VS

4 13 AGND

AD676

GROUND LEAD

I GROUND > 0

Figure 6.

Figure 5b. AGND SENSE Eliminates the Problem in Figure 5a.

Figure 6 shows a voltage reference circuit featuring the 5 V output AD586. The AD586 is a low cost reference which utilizes a buried Zener architecture to provide low noise and drift. Over the 0C to +70C range, the AD586L grade exhibits less than 2.25 mV output change from its initial value at +25C. A noisereduction capacitor, CN, reduces the broadband noise of the

REV. A

11

AD676
AD586 output, thereby optimizing the overall performance of the AD676. It is recommended that a 10 F to 47 F high quality tantalum capacitor be tied between the VREF input of the AD676 and ground to minimize the impedance on the reference.
AD587
10 2 VIN 10F 0.1F GND 4 VO 6

NR 8 1F

10 +15V 100F +5V 100F 0.1F 78L12 0.01F 10F 10

0.1F 12 VCC 18 VDD VEE VREF 16

AD676
VIN 15 0.1F

10F

10 15V 100F VIN 79L12 0.01F 10F

17

The AD676 analog inputs (VIN, VREF and AGND SENSE) exhibit dynamic characteristics. When a conversion cycle begins, each analog input is connected to an internal, discharged 50 pF capacitor which then charges to the voltage present at the corresponding pin. The capacitor is disconnected when SAMPLE is taken LOW, and the stored charge is used in the subsequent conversion. In order to limit the demands placed on the external source by this high initial charging current, an internal buffer amplifier is employed between the input and this capacitance for a few hundred nanoseconds. During this time the input pin exhibits typically 20 k input resistance, 10 pF input capacitance and 40 A bias current. Next, the input is switched directly to the now precharged capacitor and allowed to fully settle. During this time the input sees only a 50 pF capacitor. Once the sample is taken, the input is internally floated so that the external input source sees a very high input resistance and a parasitic input capacitance of typically only 2 pF. As a result, the only dominant input characteristic which must be considered is the high current steps which occur when the internal buffers are switched in and out. In most cases, these characteristics require the use of an external op amp to drive the input of the AD676. Care should he taken with op amp selection; even with modest loading conditions, most available op amps do not meet the low distortion requirements necessary to match the performance capabilities of the AD676. Figure 8 represents a circuit, based upon the AD845, recommended for low noise, low distortion ac applications. For applications optimized more for low bias and low offset than speed or bandwidth, the AD845 of Figure 8 may be replaced by the OP27.
1k +12V 0.1F 1k 2 499 3 7

Figure 7.

Using the AD676 with 10 V input range (VREF = 10 V) typically requires 15 V supplies to drive op amps and the voltage reference. If 12 V is not available in the system, regulators such as 78L12 and 79L12 can be used to provide power for the AD676. This is also the recommended approach (for any input range) when the ADC system is subjected to harsh environments such as where the power supplies are noisy and where voltage spikes are present. Figure 7 shows an example of such a system based upon the 10 V AD587 reference, which provides a 300 V LSB. Circuitry for additional protection against power supply disturbances has been shown. A 100 F capacitor at each regulator prevents very large voltage spikes from entering the regulators. Any power line noise which the regulators cannot eliminate will be further filtered by an RC filter (10 /10 F) having a 3 dB point at 1.6 kHz. For best results the regulators should be within a few centimeters of the AD676.
ANALOG INPUT

5V INPUT

AD676 AD845
4 6 0.1F 13 AGND 12V 14 AGND SENSE 15 VIN

As previously discussed, the analog input voltage range for the AD676 is VREF. For purposes of ground drop and common mode rejection, the VIN and VREF inputs each have their own ground. VREF is referred to the local analog system ground (AGND), and VIN is referred to the analog ground sense pin (AGND SENSE) which allows a remote ground sense for the input signal.

Figure 8.

12

REV. A

AD676
AC PERFORMANCE

AC parameters, which include S/(N+D), THD, etc., reflect the AD676s effect on the spectral content of the analog input signal. Figures 12 through 16 provide information on the AD676s ac performance under a variety of conditions. As a general rule, averaging the results from several conversions reduces the effects of noise, and therefore improves such parameters as S/(N+D). AD676 performance may be optimized by operating the device at its maximum sample rate of 100 kSPS and digitally filtering the resulting bit stream to the desired signal bandwidth. This succeeds in distributing noise over a wider frequency range, thus reducing the noise density in the frequency band of interest. This subject is discussed in the following section.
OVERSAMPLING AND NOISE FILTERING

This limit is described by S/(N+D) = (6.02n + 1.76 + 10 log FS/2FA) dB, where n is the resolution of the converter in bits, FS is the sampling frequency, and Fa is the signal bandwidth of interest. For audio bandwidth applications, the AD676 is capable of operating at a 2 oversample rate (96 kSPS), which typically produces an improvement in S/(N+D) of 3 dB compared with operating at the Nyquist conversion rate of 48 kSPS. Oversampling has another advantage as well; the demands on the antialias filter are lessened. In summary, system performance is optimized by running the AD676 at or near its maximum sampling rate of 100 kHz and digitally filtering the resulting spectrum to eliminate undesired frequencies.
DC CODE UNCERTAINTY

In quantized systems, the informational content of the analog input is represented in the frequency spectrum from dc to the Nyquist rate of the converter. Within this same spectrum are higher frequency noise and signal components. Antialias, or low pass, filters are used at the input to the ADC to reduce these noise and signal components so that their aliased components do not corrupt the baseband spectrum. However, wideband noise contributed by the AD676 will not be reduced by the antialias filter. The AD676 quantization noise is evenly distributed from dc to the Nyquist rate, and this fact can be used to minimize its overall affect. The AD676 quantization noise effects can be reduced by oversamplingsampling at a rate higher than that defined by the Nyquist theorem. This spreads the noise energy over a bandwidth wider than the frequency band of interest. By judicious selection of a digital decimation filter, noise frequencies outside the bandwidth of interest may be eliminated. The process of analog to digital conversion inherently produces noise, known as quantization noise. The magnitude of this noise is a function of the resolution of the converter, and manifests itself as a limit to the theoretical signal-to-noise ratio achievable.

NUMBER OF CODE HITS

The Nyquist rate for a converter is defined as one-half its sampling rate. This is established by the Nyquist theorem, which requires that a signal he sampled at a rate corresponding to at least twice its highest frequency component of interest in order to preserve the informational content. Oversampling is a conversion technique in which the sampling frequency is more than twice the frequency bandwidth of interest. In audio applications, the AD676 can operate at a 2 FS oversampling rate, where FS = 48 kHz.

Ideally, a fixed dc input should result in the same output code for repetitive conversions. However, as a consequence of system noise and circuit noise, for a given input voltage there is a range of output codes which may occur. Figure 9 is a histogram of the codes resulting from 1000 conversions of a typical input voltage by the AD676 used with a 10 V reference.
800

600

400

200

DEVIATION FROM CORRECT CODE LSBs

Figure 9. Distribution of Codes from 1000 Conversions, Relative to the Correct Code

The standard deviation of this distribution is approximately 0.5 LSBs. If less uncertainty is desired, averaging multiple conversions will narrow this distribution by the inverse of the square root of the number of samples; i.e., the average of 4 conversions would have a standard deviation of 0.25 LSBs.

REV. A

13

AD676
MICROPROCESSOR INTERFACE

The AD676 is ideally suited for use in both traditional dc measurement applications supporting a microprocessor, and in ac signal processing applications interfacing to a digital signal processor. The AD676 is designed to interface with a 16-bit data bus, providing all output data bits in a single read cycle. A variety of external buffers, such as 74HC541, can be used with the AD676 to provide 3-state outputs, high driving capability, and to prevent bus noise from coupling into the ADC. The following sections illustrate the use of the AD676 with a representative digital signal processor and microprocessor. These circuits provide general interface practices which are applicable to other processor choices.
ADSP-2101

The AD676 CLK and SAMPLE can be generated by dividing down the system clock as described earlier (Figure 3), or if the ADSP-2101 serial port clocks are not being used, they can be programmed to generate CLK and SAMPLE.
A13 A12 CS A11 DMS

Figure 10b.
80286

Figure 10a shows the AD676 interfaced to the ADSP-2101 DSP processor. The AD676 buffers are mapped in the ADSP-2101s memory space, requiring one wait state when using a 12.5 MHz processor clock. The falling edge of BUSY interrupts the processor, indicating that new data is ready. The ADSP-2101 automatically jumps to the appropriate service routine with minimal overhead. The interrupt routine then instructs the processor to read the new data using a memory read instruction.
IRQ2 A0 ADDRESS BUS A13 RD DMS D8 D23 16 8 A1 A3 BUSY CS DECODER G1 Y1 Y8

The 80286 16-bit microprocessor can be interfaced to a buffered AD676 without any generation of wait states. As seen in Figure 11, BUSY can be used both to control the AD676 clock and to alert the processor when new data is ready. In the system shown, the 80286 should be configured in an edge triggered, direct interrupt mode (integrated controller provides the interrupt vector). Since the 80286 does not latch interrupt signals, the interrupt needs to be internally acknowledged before BUSY goes HIGH again during the next AD676 conversion (BUSY = 0). Depending on whether the AD676 buffers are mapped into memory or 1/0 space, the interrupt service routine will read the data by using either the MOV or the IN instruction. To be able to read all the 16 bits at once, and thereby increase the 80286s efficiency, the buffers should be located at an even address.
G1 AD0 AD15 16 RD PCSO 6 ALE S2 8 CS DECODER G1 Y1 Y8 Y1 Y8 8 A1 A8 8

74HC541
G2

ADSP-2101

74HC541
G2

BIT1 BIT16 16 A1 A8

BIT 1 BIT 16 G1 Y1 Y8 8 A1 A3 8 16

80286

74HC541
G2

AD676

AD676

CLKOUT

DIVIDER 2MHz D Q D Q Q CLR Q CLR

SAMPLE CLK BUSY

74HC541
G2

INT 0

Figure 10a.

74HC04

74HC74

Figure 10b shows circuitry which would be included by a typical address decoder for the output buffers. In this case, a data memory access to any address in the range 3000H to 37FFH will result in the output buffers being enabled.

Figure 11.

14

REV. A

Typical Dynamic Performance AD676


102 100 98 96 94
dB
dB

100

THD

90 THD 80

92 90 88 86 84 82 80 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 S/(N+D)

70 S/(N+D) 60

50 40

30 60

50

40

30

20

10

VREF Volts

INPUT AMPLITUDE dB

Figure 12. S/(N+D) and THD vs. VREF

Figure 13. S/(N+D) and THD vs. Input Amplitude

Figure 14. 4096 Point FFT at 96 kSPS, fIN = 1.06 kHz

Figure 15. IMD Plot for fIN = 1008 Hz (fa), 1055 Hz (fb) at 96 kSPS

+5V 90 80 +12V 70

S/(N+D) dB

12V 60 50 40 30 20 0 100 1k 10k 100k RIPPLE FREQUENCY Hz 1M

Figure 16. AC Power Supply Rejection (fIN = 1.06 kHz) fSAMPLE = 96 kSPS, VRIPPLE = 0.13 V p-p

REV. A

15

AD676
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

28-Pin Ceramic DIP Package (D-28)

28

15

14

1.490 (37.85) MAX 0.225 (5.72) MAX

0.060 (1.52) 0.015 (0.38)

0.610 (15.49) 0.500 (12.70)

0.150 (3.81) MIN 0.070 (1.78) 0.030 (0.76) 0.620 (15.75) 0.590 (14.99)

0.018 (0.46) 0.008 (0.20)

0.200 (5.08) 0.125 (3.18)

0.026 (0.66) 0.014 (0.36)

0.100 (2.54) BSC

16

REV. A

PRINTED IN U.S.A.

C1679247/92

0.005 (0.13) MIN

0.100 (2.54) MAX

a
FEATURES Complete 12-Bit DAC No External Components Single +5 Volt Operation 1 mV/Bit with 4.095 V Full Scale True Voltage Output, 5 mA Drive Very Low Power 3 mW APPLICATIONS Digitally Controlled Calibration Servo Controls Process Control Equipment PC Peripherals
REF

+5 Volt, Parallel Input Complete 12-Bit DAC DAC8562


FUNCTIONAL BLOCK DIAGRAM
REFOUT VDD

DAC-8562
12-BIT DAC 12 AGND DAC REGISTER 12 VOUT

DGND

CE

DATA

CLR

GENERAL DESCRIPTION

The DAC8562 is a complete, parallel input, 12-bit, voltage output DAC designed to operate from a single +5 volt supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost, and ease-of-use in +5 volt only systems. Included on the chip, in addition to the DAC, is a rail-to-rail amplifier, latch and reference. The reference (REFOUT) is trimmed to 2.5 volts, and the on-chip amplifier gains up the DAC output to 4.095 volts full scale. The user needs only supply a +5 volt supply. The DAC8562 is coded straight binary. The op amp output swings from 0 to +4.095 volts for a one millivolt per bit resolution, and is capable of driving 5 mA. Built using low temperature-coefficient silicon-chrome thin-film resistors, excellent linearity error over temperature has been achieved as shown below in the linearity error versus digital input code plot. Digital interface is parallel and high speed to interface to the fastest processors without wait states. The interface is very simple requiring only a single CE signal. An asynchronous CLR input sets the output to zero scale.

The DAC8562 is available in two different 20-pin packages, plastic DIP and SOL-20. Each part is fully specified for operation over 40C to +85C, and the full +5 V 5% power supply range. For MIL-STD-883 applications, contact your local ADI sales office for the DAC8562/883 data sheet which specifies operation over the 55C to +125C temperature range.
1 0.75
LINEARITY ERROR LSB

VDD = +5V TA = 55C, +25C, +125C 55C

0.5 0.25 0 0.25 0.5 +25C & +125C 0.75 1 0 1024 2048 3072 DIGITAL INPUT CODE Decimal 4096

Figure 1. Linearity Error vs. Digital Input Code Plot

REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

DAC8562SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter

(@ VDD = +5.0
Symbol

5%, RS = No Load, 40 C TA +85 C, unless otherwise noted)


Min Typ Max Units

Condition

STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage

N INL DNL VZSE VFS TCVFS IOUT LDREG CL VREF IREF LNREJ LDREG VIL VIH IIL CIL tCEW tDS tDH tCLRW tS

Full-Scale Tempco ANALOG OUTPUT Output Current Load Regulation at Half Scale Capacitive Load REFERENCE OUTPUT Output Voltage Output Source Current Line Rejection Load Regulation LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance INTERFACE TIMING SPECIFICATIONS1, 4 Chip Enable Pulse Width Data Setup Data Hold Clear Pulse Width AC CHARACTERISTICS4 Voltage Output Settling Time6 Digital Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current Power Dissipation Power Supply Sensitivity

Note 2 E Grade F Grade No Missing Codes Data = 000H Data - FFFH3 E Grade F Grade Notes 3, 4 Data = 800H RL = 402 to , Data = 800H No Oscillation4

12 1/2 1 1

1/4 3/4 3/4 +1/2 4.095 4.095 16 7 1 500 2.500 7

+1/2 +1 +1 +3 4.103 4.111

Bits LSB LSB LSB LSB V V ppm/C mA LSB pF V mA %/V %/mA V V A pF ns ns ns ns

4.087 4.079

Note 5 IREF = 0 to 5 mA

2.484 5

2.516 0.08 0.1 0.8

2.4 Note 4 30 30 10 20 To 1 LSB of Final Value 16 35 3 0.6 15 3 0.002 6 1 30 5 0.004 10 10

s nV sec mA mA mW mW %/%

IDD PDISS PSS

VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5V VDD = 5%

NOTES 1 All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 1 LSB = 1 mV for 0 to +4.095 V output range. 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground. 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice.

REV. A

DAC8562 WAFER TEST LIMITS unless otherwise noted)


Parameter Symbol

(@ VDD = +5.0 V

5%, RL = No Load, TA = +25 C, applies to part number DAC8562GBC only,


Condition Min Typ Max Units

STATIC PERFORMANCE Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Reference Output Voltage LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current SUPPLY CHARACTERISTICS Positive Supply Current Power Dissipation Power Supply Sensitivity

INL DNL VZSE VFS VREF VIL VIH IIL IDD PDISS PSS

No Missing Codes Data = 000H Data = FFFH

1 1 4.085 2.490

3/4 3/4 +1/2 4.095 2.500

+1 +1 +3 4.105 2.510 0.8

LSB LSB LSB V V V V A mA mA mW mW %/%

2.4 10 VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V VDD = 5% 3 0.6 15 3 0.002 6 1 30 5 0.004

NOTE 1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS*

tCEW tDS tDH

VDD to DGND and AGND . . . . . . . . . . . . . . . . 0.3 V, +10 V Logic Inputs to DGND . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V VREFOUT to AGND . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . (TJ max TA)/ JA Thermal Resistance JA 20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 74C/W 20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 89C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150C Operating Temperature Range . . . . . . . . . . . . . 40C to +85C Storage Temperature Range . . . . . . . . . . . . . 65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CE
0 1

DB110
0 1

DATA VALID

tCLRW

CLR
0 FS

VOUT
ZS

1 LSB ERROR BAND

tS

tS

Figure 2. Timing Diagram


Table I. Control Logic Truth Table CE CLR DAC Register Function

H L + X H

H H H L +

Latched Transparent Latched with New Data Loaded with All Zeros Latched All Zeros

+ Positive Logic Transition; X Don't Care.

CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted.

WARNING!
ESD SENSITIVE DEVICE

REV. A

DAC8562
PIN CONFIGURATIONS 20-Pin P-DIP (N-20)
DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DGND 1 2 3 4 5 6 7 8 9 10 NC = NO CONNECT 20 VDD 19 DB2

Table II. Nominal Output Voltage vs. Input Code Binary Hex Decimal Output (V)

SOL-20 (R-20)
1

18 DB1 17 DB0 CE CLR

DAC-8562
TOP VIEW (Not to Scale)

DAC-8562
TOP VIEW (Not to Scale)

16 15

14 REFOUT 13 12 11 VOUT AGND NC

0000 0000 0000 0000 0000 0001 0000 0000 0010 0000 0000 1111 0000 0001 0000 0000 1111 1111 0001 0000 0000 0001 1111 1111 0010 0000 0000 0011 1111 1111 0100 0000 0000 0111 1111 1111 1000 0000 0000 1100 0000 0000 1111 1111 1111

000 001 002 00F 010 0FF 100 1FF 200 3FF 400 7FF 800 C00 FFF

0 1 2 15 16 255 256 511 512 1023 1024 2047 2048 3072 4095

0.000 Zero Scale 0.001 0.002 0.015 0.016 0.255 0.256 0.511 0.512 1.023 1.024 2.047 2.048 Half Scale 3.072 4.095 Full Scale

PIN DESCRIPTIONS ORDERING GUIDE Pin Model INL (LSB) Temperature Range Package Option Name Description

20 1-9 17-19 16 15

VDD DB0-DB11 CE CLR

DAC8562EP DAC8562FP DAC8562FS DAC8562GBC

1/2 1 1 1

40C to +85C 40C to +85C 40C to +85C +25C

N-20 N-20 R-20 Dice

DICE CHARACTERISTICS
AGND 12 VOUT REFOUT 13 14 7 DB9 DGND 10 DB11 9 8 DB10

8 12

DGND AGND

13

VOUT

CLR

15

DB8

5 CE DB0 16 17 4

DB7

14

REFOUT

DB6

11
DB1 18 19 DB2 20 VDD 1 DB3 2 DB4 3 DB5

NC

Positive supply. Nominal value +5 volts, 5%. Twelve Binary Data Bit inputs. DB11 is the MSB and DB0 is the LSB. Chip Enable. Active low input. Active low digital input that clears the DAC register to zero, setting the DAC to minimum scale. Digital ground for input logic. Analog Ground. Ground reference for the internal bandgap reference voltage, the DAC, and the output buffer. Voltage output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature and power supply variations. Nominal 2.5 V reference output voltage. This node must be buffered if required to drive external loads. No Connection. Leave pin floating.

SUBSTRATE IS COMMON WITH VDD. TRANSISTOR COUNT: 524 DIE SIZE: 0.70 X 0.105 INCH; 7350 SQ MILS

REV. A

DAC8562
OPERATION

The DAC8562 is a complete ready to use 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for operation. It contains a voltage-switched, 12-bit, laser-trimmed digital-to-analog converter, a curvature-corrected bandgap reference, a rail-to-rail output op amp, and a DAC register. The parallel data interface consists of 12 data bits, DB0DB11, and a active low CE strobe. In addition, an asynchronous CLR pin will set all DAC register bits to zero causing the VOUT to become zero volts. This function is useful for power on reset or system failure recovery to a known state.
D/A CONVERTER SECTION

current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the 5% supply tolerance value of 4.75 volts.
VDD P-CH

VOUT N-CH

The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt internal bandgap voltage. It uses a laser trimmed R-2R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output (not available to the user) is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION

AGND

Figure 4. Equivalent Analog Output Circuit

Figures 5 and 6 in the typical performance characteristics section provide information on output swing performance near ground and full scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability.
REFERENCE SECTION

The internal DACs output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zeroscale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an equivalent circuit schematic of the analog section.
REFOUT 2.5V BANDGAP REFERENCE VOLTAGE SWITCHED 12-BIT R-2R D/A CONVERTER 2R R BUFFER 2R R1 R 2R R2

The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the REFOUT pin. Since REFOUT is not intended to drive external loads, it must be bufferedrefer to the applications section for more information. The equivalent emitter follower output circuit of the REFOUT pin is shown in Figure 3. Bypassing the REFOUT pin is not required for proper operation. Figure 7 shows broadband noise performance.
POWER SUPPLY

RAIL-TO-RAIL OUTPUT AMPLIFIER

VOUT

The very low power consumption of the DAC8562 is a direct result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved. For power-consumption sensitive applications it is important to note that the internal power consumption of the DAC8562 is strongly dependent on the actual logic-input voltage-levels present on the DB0DB11, CE and CLR pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. The graph in Figure 9 shows the effect on total DAC8562 supply current as a function of the actual value of input logic voltage. Consequently for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the DB0DB11 pins provides the lowest standby dissipation of 600 A with a +5 V power supply.

AV = 4.096/2.5 = 1.636V/V

SPDT N ch FET SWITCHES

2R 2R

Figure 3. Equivalent DAC8562 Schematic of Analog Portion

The op amp has a 16 s typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the Typical Performances section of this data sheet.
OUTPUT SECTION

The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull down FETs that will pull an output load directly to GND. The output sourcing REV. A 5

DAC8562
As with any analog system, it is recommended that the DAC8562 power supply be bypassed on the same PC card that contains the chip. Figure 10 shows the power supply rejection versus frequency performance. This should be taken into account when using higher frequency switched-mode power supplies with ripple frequencies of 100 kHz and higher. One advantage of the rail-to-rail output amplifier used in the DAC8562 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +4.75 V to +5.25 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the DAC8562 is possible down to +4.3 volts. The minimum operating supply voltage versus load current plot, in Figure 11, provides information for operation below VDD = +4.75 V.
TIMING AND CONTROL

The DAC8562 has a 12-bit DAC register that simplifies interface to a 12-bit (or wider) data bus. The latch is controlled by the Chip Enable (CE) input. If the application does not involve a data bus, wiring CE low allows direct operation of the DAC. The data latch is level triggered and acquires data from the data bus during the time period when CE is low. When CE goes high, the data is latched into the register and held until CE returns low. The minimum time required for the data to be present on the bus before CE returns high is called the data setup time (tDS) as seen in Figure 2. The data hold time (tDH) is the amount of time that the data has to remain on the bus after CE goes high. The high speed timing offered by the DAC8562 provides for direct interface with no wait states in all but the fastest microprocessors.

Typical Performance Characteristics


5

OUTPUT PULLDOWN VOLTAGE mV

VDD = +5V TA = +25C

100 VDD = +5V DATA = 000H 10


OUTPUT CURRENT mA

80 60 40 20 0 20 40 60 80 1 10 100 OUTPUT SINK CURRENT A 1000 100 1 NEG CURRENT LIMIT 2 3 OUTPUT VOLTAGE Volts DATA = 800H RL TIED TO +2V POS0 CURRENT0 LIMIT0

OUTPUT VOLTAGE Volts

4 RL TIED TO AGND RL TIED TO AGND DATA = FFFH D = FFFH 3

TA = +85C

TA = +25C 0.1 TA = 40C

RL TIED TO +5V DATA = 000H

0 10 100 1k 10k LOAD RESISTANCE 100k

0.01

Figure 5. Output Swing vs. Load

Figure 6. Pull-Down Voltage vs. Output Sink Current Capability


5 VDD = +5V TA = +25C
POWER SUPPLY REJECTION dB

Figure 7. IOUT vs. VOUT

OUTPUT NOISE VOLTAGE 500V/DIV

100 VDD = +5V 200mV AC 80 TA = +25C DATA = FFFH

50mV
100 90

1ms

SUPPLY CURRENT mA

60

40

10 0%

TA = 25C NBW = 630kHz TIME = 1ms/DIV

20

1 2 3 4 LOGIC VOLTAGE VALUE Volts

0 10 100 1k 10k FREQUENCY Hz 100k

Figure 8. Broadband Noise

Figure 9. Supply Current vs. Logic Input Voltage

Figure 10. Power Supply Rejection vs. Frequency

REV. A

DAC8562
5.0

INPUT

5
4.8
VDD MIN Volts

5V

VFS 1 LSB DATA = FFFH TA = +25C

CE

5
100

0 4

90

VDD = +5V TA = +25C

4.6

DATA = 204810 TO 204710 2.048


OUTPUT
PROPER OPERATION WHEN VDD SUPPLY VOLTAGE ABOVE CURVE
VOUT Volts

3 2 1 0
10 0%

4.4

2.038 2.028 2.018

4.2

1V

20s

TIME = 20s/DIV 4.0 0.01 0.04 0.1 1.0 0.4 4.0 OUTPUT LOAD CURRENT mA 10

TIME 200ns/DIV

Figure 11. Minimum Supply Voltage vs. Load

Figure 12. Midscale Transition Performance

Figure 13. Large Signal Settling Time

2.0

DATA

DATA

5 0 16s

5 0

VDD = +5V TA = +25C


LINEARITY ERROR LSB

VDD = +5V 1.5 1.0 0.5 0.0 0.5 +25C & +85C 1.0 1.5 2.0 40C TA = 40C, 25C, +85C

OUTPUT VOLTAGE 1mV/DIV

VDD = +5V TA = +25C

OUTPUT VOLTAGE 1mV/DIV

16s

TIME 10s/DIV

TIME 10s/DIV

512 1024 1536 2048 2560 3072 3584 4096 DIGITAL INPUT CODE Decimal

Figure 14. Output Voltage Rise Time Detail

Figure 15. Output Voltage Fall Time Detail

Figure 16. Linearity Error vs. Digital Code

50

4.125

FULL-SCALE OUTPUT Volts

40

TUE = INL+ZS+FS SS = 300 UNITS TA = +25C

4.115

NUMBER OF UNITS

30

4.105

AVG +1 AVG

ZERO-SCALE mV

VDD = +5V NO LOAD SS = 300 PCS

DATA = 000H NO LOAD VDD = +5.0V

20

4.095 AVG 1 4.085

10

8 6 4 2 0 2 4 6 8 10 12 14 16 TOTAL UNADJUSTED ERROR LSB

4.075 50

25

25

50

75

100

125

1 50

25

TEMPERATURE C

0 25 50 75 TEMPERATURE C

100

125

Figure 17. Total Unadjusted Error Histogram

Figure 18. Full-Scale Voltage vs. Temperature

Figure 19. Zero-Scale Voltage vs. Temperature

REV. A

DAC8562Typical Performance Characteristics DAC8562


10
OUTPUT NOISE DENSITY V/ Hz

5
OUTPUT VOLTAGE CHANGE mV

8
VDD = +5V DATA = FFF READINGS NORMALIZED TO ZERO HOUR TIME POINT
H

VDD = +5V TA = 25C DATA = FFFH 1

4 3 2 1 0 1 2 3 4 135 UNITS TESTED 0

7
SUPPLY CURRENT mA

VDATA = +2.4V NO LOAD

6 5 4 3 2 VDD = +4.75V 1 0 50 VDD = +5.0V VDD = +5.25V

RANGE AVG

0.1

0.01 10

1k 10k 100 FREQUENCY Hz

100k

5 200 400 600 800 1000 HOURS OF OPERATION AT +125C 1200

25

0 25 50 75 TEMPERATURE C

100

125

Figure 20. Output Voltage Noise Density vs. Frequency

Figure 21. Long-Term Drift Accelerated by Burn-In

Figure 22. Supply Current vs. Temperature

10

DATA

2V
100 90

A4 0.040 V

DLY

1
100

13.82 s
VREF OUT ERROR mV

8 AVG +1 6 4 2 0 2 4 6 8 10 50 AVG 1 VDD = +5V SAMPLE SIZE = 300 X

CE = HIGH

90

VDD 0V VREF 0V
10 0%

TA = +25C RL =
VOUT 5mV/DIV

10 0%

2V

1s

5V

5mV

Bw L

5s

TIME = 1s/DIV

TIME = 20s/DIV

25

25

50

75

100

125

TEMPERATURE C

Figure 23. Reference Startup vs. Time

Figure 24. Digital Feedthrough vs. Time

Figure 25. Reference Error vs. Temperature

0.005

0.10
REF LINE REGULATION %/Volt

REF LOAD REGULATION %/mA

0.004

AVG + 3

0.08

VDD = +4.75 TO +5.25V SAMPLE SIZE = 302 PCS

0.003

AVG AVG 3

0.06

AVG + 3 AVG

0.002 VDD = +5V IL = 5mA SAMPLE SIZE = 302 PCS 25 25 50 75 0 TEMPERATURE C 100 125

0.04 AVG 3 0.02

0.001

0.000 50

0.00 50

25

25

50

75

100

125

TEMPERATURE C

Figure 26. Reference Load Regulation vs. Temperature

Figure 27. Reference Line Regulation vs. Temperature

REV. A

DAC8562
APPLICATIONS SECTION Power Supplies, Bypassing, and Grounding

All precision converter products require careful application of good grounding practices to maintain full-rated performance. Because the DAC8562 has been designed for +5 V applications, it is ideal for those applications under microprocessor or microcomputer control. In these applications, digital noise is prevalent; therefore, special care must be taken to assure that its inherent precision is maintained. This means that particularly good engineering judgment should be exercised when addressing the power supply, grounding, and bypassing issues using the DAC8562. The power supply used for the DAC8562 should be well filtered and regulated. The device has been completely characterized for a +5 V supply with a tolerance of 5%. Since a +5 V logic supply is almost universally available, it is not recommended to connect the DAC directly to an unfiltered logic supply without careful filtering. Because it is convenient, a designer might be inclined to tap a logic circuit s supply for the DACs supply. Unfortunately, this is not wise because fast logic with nanosecond transition edges induces high current pulses. The high transient current pulses can generate glitches hundreds of millivolts in amplitude due to wiring resistances and inductances. This high frequency noise will corrupt the analog circuits internal to the DAC and cause errors. Even though their spike noise is lower in amplitude, directly tapping the output of a +5 V system supplies can cause errors because these supplies are of the switching regulator type that can and do generate a great deal of high frequency noise. Therefore, the DAC and any associated analog circuitry should be powered directly from the system power supply outputs using appropriate filtering. Figure 28 illustrates how a clean, analog-grade supply can be generated from a +5 V logic supply using a differential LC filter with separate power supply and return lines. With the values shown, this filter can easily handle 100 mA of load current without saturating the ferrite cores. Higher current capacity can be achieved with larger ferrite cores. For lowest noise, all electrolytic capacitors should be low ESR (Equivalent Series Resistance) type.
FERRITE BEADS: 2 TURNS, FAIR-RITE #2677006301 TTL/CMOS LOGIC CIRCUITS

The DAC8562 includes two ground connections in order to minimize system accuracy degradation arising from grounding errors. The two ground pins are designated DGND (Pin 10) and AGND (Pin 12). The DGND pin is the return for the digital circuit sections of the DAC and serves as their input threshold reference point. Thus DGND should be connected to the same ground as the circuitry that drives the digital inputs. Pin 12, AGND, serves as the supply rail for the internal voltage reference and the output amplifier. This pin should also serve as the reference point for all analog circuitry associated with the DAC8562. Therefore, to minimize any errors, it is recommended that the AGND connection of the DAC8562 be connected to a high quality analog ground. If the system contains any analog signal path carrying a significant amount of current, then that path should have its own return connection to Pin 12. It is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common to one place only. If the common tie point is remote and an accidental disconnection of that one common tie point were to occur due to card removal with power on, a large differential voltage between the two commons could develop. To protect devices that interface to both digital and analog parts of the system, such as the DAC8562, it is recommended that the common ground tie points be provided at each such device. If only one system ground can be connected directly to the DAC8562, it recommended that the analog common be used. If the systems AGND has suitably low impedance, then the digital signal currents flowing in it should not seriously affect the ground noise. The amount of digital noise introduced by connecting the two grounds together at the device will not adversely affect system performance due to loss of digital noise immunity. Generous bypassing of the DACs supply goes a long way in reducing supply line-induced errors. Local supply bypassing consisting of a 10 F tantalum electrolytic in parallel with a 0.1 F ceramic is recommended. The decoupling capacitors should be connected between the DACs supply pin (Pin 20) and the analog ground (Pin 12). Figure 29 shows how the DGND, AGND, and bypass connections should be made to the DAC8562.
+5V

+5V

100F ELECT.

10-22F TANT.

0.1F CER. DATA +5V RETURN

20 VDD

10F 13

0.1F VOUT

DAC-8562
CE CLR 16 15 DGND 10

AGND 12

+5V POWER SUPPLY

TO OTHER ANALOG CIRCUITS

Figure 28. Properly Filtering a +5 V Logic Supply Can Yield a High Quality Analog Supply

TO POWER GROUND

Figure 29. Recommended Grounding and Bypassing Scheme for the DAC-8562

REV. A

DAC8562
Unipolar Output Operation

This is the basic mode of operation for the DAC8562. As shown in Figure 30, the DAC8562 has been designed to drive loads as low as 820 in parallel with 500 pF. The code table for this operation is shown in Table III.
+5V 10F 0.1F

+12V OR +15V 0.1F

REF-02
4

0.1F

1 DATA

DAC-8562
20 VDD DATA
CE CLR 16 15 DGND 10 AGND 12 13 VOUT

DAC-8562
CE CLR 16 15 DGND 10 AGND 12 13 820

0V VOUT 4.095V

500pF

Figure 31. Operating the DAC8562 on +12 V or +15 V Supplies Using a REF02 Voltage Reference
Measuring Offset Error

Figure 30. Unipolar Output Operation


Table III. Unipolar Code Table Hexadecimal Number in DAC Register Decimal Number in DAC Register Analog Output Voltage (V)

One of the most commonly specified endpoint errors associated with real-world nonideal DACs is offset error. In most DAC testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 volt. There are some DACs where offset errors may be present but not observable at the zero scale because of other circuit limitations (for example, zero coinciding with single supply ground). In these DACs, nonzero output at zero code cannot be read as the offset error. In the DAC8562, for example, the zero-scale error is specified to be +3 LSBs. Since zero scale coincides with zero volt, it is not possible to measure negative offset error. By adding a pull-down resistor from the output of the DAC8562 to a negative supply as shown in Figure 32, offset errors can now be read at zero code. This configuration forces the output P-channel MOSFET to source current to the negative supply thereby allowing the designer to determine in which direction the offset error appears. The value of the resistor should be such that, at zero code, current through the resistor is 200 A maximum.
+5V 0.1F

FFF 801 800 7FF 000

4095 2049 2048 2047 0

+4.095 +2.049 +2.048 +2.047 0

Operating the DAC8562 on +12 V or +15 V Supplies Only

Although the DAC8562 has been specified to operate on a single, +5 V supply, a single +5 V supply may not be available in many applications. Since the DAC8562 consumes no more than 6 mA, maximum, then an integrated voltage reference, such as the REF02, can be used as the DAC8562 +5 V supply. The configuration of the circuit is shown in Figure 31. Notice that the references output voltage requires no trimming because of the REF02s excellent load regulation and tight initial output voltage tolerance. Although the maximum supply current of the DAC8562 is 6 mA, local bypassing of the REF02s output with at least 0. 1 F at the DACs voltage supply pin is recommended to prevent the DACs internal digital circuits from affecting the DACs internal voltage reference.

20 VDD DATA

DAC-8562
CE CLR 16 15 DGND 10 AGND 12 V 13 200A MAX VOUT

Figure 32. Measuring Zero-Scale or Offset Error

10

REV. A

DAC8562
+5V 0.1F 10F R4 23.7k FULL SCALE ADJUST P2 500

20 VDD DATA VOUT 13 R1 10k 2 R2 12.7k R6 10k R5 10k 6 2.5V P1 10k ZERO SCALE ADJUST 7 R3 247k

+5V 8

DAC-8562
CE CLR 16 REFOUT 14 15 DGND 10 AGND 12

A1
3 4

5V VO +5V

5V

A2
5

A1, A2 = 1/2 OP-295

Figure 33. Bipolar Output Operation


Bipolar Output Operation

Although the DAC8562 has been designed for single supply operation, bipolar operation is achievable using the circuit illustrated in Figure 33. The circuit uses a single supply, rail-to-rail OP295 op amp and the DACs internal +2.5 V reference to generate the 2.5 V reference required to level-shift the DAC output voltage. The circuit has been configured to provide an output voltage in the range 5 V VOUT +5 V and is coded in complementary offset binary. Although each DAC LSB corresponds to 1 mV, each output LSB has been scaled to 2.44 mV. Table IV provides the relationship between the digital codes and output voltage. The transfer function of the circuit is given by:

R4 R2 VO = 1 mV Digital Code 1 + R3 + R4 R1 R2 REFOUT R1

For the 2 5 V output range and the circuit values shown in the table, the transfer equation becomes:

VO = 1.22 mV Digital Code 2.5 V


Similarly, for the 5 V output range, the transfer equation becomes:

R4 R4 VO = 1 mV Digital Code + 2.5 R1 R2


and, for the circuit values shown, becomes:
VO = 2.44 mV Digital Code + 5 V
Table IV. Bipolar Code Table

VO = 2.44 mV Digital Code 5 V


Note that, for 5 V output voltage operation, R5 is required as a pull-down for REFOUT. Or, REFOUT can be buffered by an op amp configured as a follower that can source and sink current.
+5V 0.1F

Hexadecimal Number in DAC Register

Decimal Number in DAC Register

Analog Output Voltage (V)

R2 20 VDD DATA REFOUT 14 R1 R5 4.99k R3 VOUT 13 DGND 10 AGND 12 R4 5V 2 +5V 8

FFF 801 800 7FF 000

4095 2049 2048 2047 0

4 9976 2.44E3 0 +2.44E3 +5

DAC-8562
CE CLR 16 15

A1
3 4

VO

To maintain monotonicity and accuracy, R1, R2, R4, R5, and R6 should be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. Mismatching between R1 and R2 causes offset and gain errors while an R4 to R1 and R2 mismatch yields gain errors. For applications that do not require high accuracy, the circuit illustrated in Figure 34 can also be used to generate a bipolar output voltage. In this circuit, only one op amp is used and no potentiometers are used for offset and gain trim The output voltage is coded in offset binary and is given by: REV. A 11

A1 = 1/2 OP-295
VOUT RANGE 2.5V 5V

R1 10k 10k

R2 10k 20k

R3 10k 10k

R4 15.4k + 274 43.2k + 499

Figure 34. Bipolar Output Operation Without Trim Version 1

DAC8562
Alternatively, the output voltage can be coded in complementary offset binary using the circuit in Figure 35. This configuration eliminates the need for a pull-down resistor or an op amp for REFOUT The transfer equation of the circuit is given by:
R2 VO = 1 mV Digital Code + REFOUT R1 R4 R2 1 + R3 + R4 R1

audio mixing consoles, music synthesizers, and other audio processors, VCAs, such as the SSM2018, adjust audio channel gain and attenuation from front panel potentiometers. The VCA provides a clean gain transition control of the audio level when the slew rate of the analog input control voltage, VC, is properly chosen. The circuit in Figure 37 illustrates a volume control application using the DAC8562 to control the attenuation of the SSM2018.
+15V P1 100k OFFSET TRIM 15V 18k VOUT
16 15 14

10M P2 500k SYMMETRY TRIM 10pF 470k

and, for the values shown, becomes:

VO = 2.44 mV Digital Code + 5 V


R2 R1 VOUT

+15V 0.1F

2 3 4

DAC-8562
R3 REFOUT R4 R1 = R3 = 10k

VO

18k VIN +15V 0.1F 47pF

5 6 7 8

SSM-2018

13 12 11 10 9

30k

+15V

15V 0.1F

VO RANGE 5V

R2 23.7k + 715

R4 13.7k + 169

REF-02
4

+5V

0.1F

Figure 35 Bipolar Output Operation Without Trim Version 2


Generating a Negative Supply Voltage

20 CE CLR 16 15 R6 825 13 DATA DGND 10 AGND 12

DAC-8562

Some applications may require bipolar output configuration, but only have a single power supply rail available. This is very common in data acquisition systems using microprocessor-based systems. In these systems, only +12 V, +15 V, and/or +5 V are available. Shown in Figure 36 is a method of generating a negative supply voltage using one CD4049, a CMOS hex inverter, operating on +12 V or +15 V. The circuit is essentially a charge pump where two of the six are used as an oscillator. For the values shown, the frequency of oscillation is approximately 3.5 kHz and is fairly insensitive to supply voltage because R1 > 2 R2. The remaining four inverters are wired in parallel for higher output current. The square-wave output is level translated by C2 to a negative-going signal, rectified using a pair of 1N4001s, and then filtered by C3. With the values shown, the charge pump will provide an output voltage of 5 V for current loading in the range 0.5 mA IOUT 10 mA with a +15 V supply and 0.5 mA IOUT 7 mA with a +12 V supply.
7 INVERTERS = CD4049 9 3 R1 510k 2 5 R2 5.1k 14 C1 0.02F 15 4 11 12 D1 1N4001 C3 47F 1N5231 5.1V ZENER 10 C2 47F D2 1N4001 R3 470 5V 6

0V VC +2.24V CCON 1F

R7 1k*

* PRECISION RESISTOR PT146 1k COMPENSATOR

Figure 37. Audio Volume Control

Since the supply voltage available in these systems is typically 15 V or 18 V, a REF02 is used to supply the +5 V required to power the DAC. No trimming of the reference is required because of the references tight initial tolerance and low supply current consumption of the DAC8562. The SSM2018 is configured as a unity-gain buffer when its control voltage equals 0 volt. This corresponds to a 000H code from the DAC8562. Since the SSM2018 exhibits a gain constant of 28 mV/dB (typical), the DACs full-scale output voltage has to be scaled down by R6 and R7 to provide 80 dB of attenuation when the digital code equals FFFH. Therefore, every DAC LSB corresponds to 0.02 dB of attenuation. Table V illustrates the attenuation versus digital code of the volume control circuit.
Table V. SSM2018 VCA Attenuation vs. DAC8562 Input Code Hexadecimal Number in DAC Register Control Voltage (V) VCA Attenuation (dB)

Figure 36. Generating a 5 V Supply When Only +12 V or +15 V Are Available
Audio Volume Control

The DAC8562 is well suited to control digitally the gain or attenuation of a voltage controlled amplifiers. In professional

000 400 800 C00 FFF

0 +0.56 +1.12 +1.68 +2.24

0 20 40 60 80

12

REV. A

DAC8562
To compensate for the SSM2018s gain constant temperature coefficient of 3300 ppm/C, a 1 k, temperature-sensitive resistor (R7) manufactured by the Precision Resistor Company with a temperature coefficient of +3500 ppm/C is used. A CCON of 1 F provides a control transition time of 1 ms which yields a click-free change in the audio channel attenuation. Symmetry and offset trimming details of the VCA can be found in the SSM2018 data sheet. Information regarding the PT146 1 k Compensator can be obtained by contacting: Precision Resistor Company, Incorporated 10601 75th Street North Largo, FL 34647 (813) 541-5771
A High-Compliance, Digitally Controlled Precision Current Source
R1 100k 1 11 2 4 P1 100k 5

lower limits for the test are loaded into each DAC individually by controlling HDAC/LDAC. If a signal at the test input is not within the programmed limits, the output will indicate a logic zero which will turn the red LED on.
R2 5k 7 6 18 12 RCS 100 10 8 9 0mA IOUT 10mA 2.4A/ LSB +15V 0.1F

17

AMP-05

The circuit in Figure 38 shows the DAC8562 controlling a high-compliance, precision current source using an AMP05 instrumentation amplifier. The AMP05s reference pin becomes the input, and the old inputs now monitor the voltage across a precision current sense resistor, RCS. Voltage gain is set to unity, so the transfer function is given by the following equation: IOUT = VIN RCS

0.1F

15V +15V

0.1F

REF-02
4

0.1F

If RCS equals 100 , the output current is limited to +10 mA with a 1 V input. Therefore, each DAC LSB corresponds to 2.4 A. If a bipolar output current is required, then the circuit in Figure 33 can be modified to drive the AMP05s reference pin with a 1 V input signal. Potentiometer P1 trims the output current to zero with the input at 0 V. Fine gain adjustment can be accomplished by adjusting R1 or R2.
A Digitally Programmable Window Detector

20 CE CLR 16 15 R3 3k 13 DATA DGND 10 AGND 12 R4 1k

DAC-8562

A digitally programmable, upper/lower limit detector using two DAC8562s is shown in Figure 39. The required upper and
+5V 1k 16 15 +5V VIN

Figure 38. A High-Compliance, Digitally Controlled Precision Current Source


+5V +5V

0.1F

20 +5V

R1 604 0.1F

R2 604

DAC-8562
13 DGND AGND 3 5 C1 4

2 1/6 74HC05 1

10

12

RED LED T1 2 PASS/FAIL

GREEN LED T1

+5V

0.1F

7 C2 1 6 12

4 1/6 74HC05

20 HDAC/LDAC CLR DATA 16 15

DAC-8562
13 DGND AGND 10 12

C1, C2 = 1/4 CMP-404

Figure 39. A Digitally Programmable Window Detector

REV. A

13

DAC8562
Decoding Multiple DAC8562s

The CE function of the DAC8562 can be used in applications to decode a number of DACs. In this application, all DACs receive the same input data; however, only one of the DACs CE input is asserted to transfer its parallel input register contents into the DAC. In this circuit, shown in Figure 40, the CE timing is generated by a 74HC139 decoder and should follow the DAC8562s standard timing requirements. To prevent timing errors, the 74HC139 should not be activated by its ENABLE input while the coded address inputs are changing. A simple timing circuit, R1 and C1, connected to the DACs CLR pins resets all DAC outputs to zero during power-up.
MICROPROCESSOR INTERFACING DAC-8562MC68HC11 INTERFACE

when PC1 is cleared. The DACs CLR input, controlled by the M68HC11s PC2 output line, provides an asynchronous clear function that sets the DACs output to zero. Included in this section is the source code for operating the DAC-8562M68HC11 interface.
+5V C1 0.1F R1 1k 15 16 DATA +5V 15 VOUT2 13 4 5 6 7 12 11 10 9 GND 2Y3 NC NC NC 15 NC 16 13 VOUT4 15 16 VOUT3 13 16 VOUT1 13

DAC-8562 #1

The circuit illustrated in Figure 41 shows a parallel interface between the DAC8562 and a popular 8-bit microcontroller, the M68HC11, which is configured in a single-chip operating mode. The interface circuit consists of a pair of 74ACT11373 transparent latches and an inverter. The data is loaded into the latches in two 8-bit bytes; the first byte contains the four most significant bits, and the lower 8 bits are in the second byte. Data is taken from the microcontrollers port B output lines, and three interface control lines, CLR, CE, and MSB/LSB, are controlled by the M68HC11's PC2, PC1, and PC0 output lines, respectively. To transfer data into the DAC, PC0 is set, enabling U1s outputs. The first data byte is loaded into U1 where the four least significant bits of the byte are connected to MSBDB8. PC0 is then cleared; this latches U1s inputs and enables U2s outputs. U2s outputs now become DB7DB0. The DAC output is updated with the contents of U1 and U2

74HC139
0.1F ENABLE 16 VCC 1 2 CODED ADDRESS +5V 3 15 1k 14 2A 13 8 2B 1G 1A 1B 2G 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2

DAC-8562 #2

DAC-8562 #3

DAC-8562 #4

Figure 40. Decoding Multiple DAC8562s Using the CE Pin

74ACT11373 *M6BHC11
PC2 PC1 PC0 CLR 22 CE 13 23 C 1D 2D 3D 4D 5D 6D 7D 8D OC 1Q 2Q 3Q 1 NC 2 3 4 9 10 6Q 7Q 8Q 11 12 NC NC NC PC2 PC1 9 8 7 6 5 4 C PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 23 22 21 20 1 16 15 14 24 1D 2D 3D 4D 5D 6D 7D 8D OC 1Q 2Q 3Q 4Q 1 2 3 4 9 10 11 7Q 8Q 12 3 2 1 19 18 17 DB2 DB1 LSB DB4 DB3 DB6 DB5 15 16 CLR CE MSB DB10 DB9 DB8 DB7

74HC04
2

21 20 1 16 15 14 24

MSB/ LSB 1

*DAC-8562

U1

4Q 5Q

U3
VOUT 13

74ACT11373
13

U2

5Q 6Q

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 41. DAC8562 to MC68HC11 Interface

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DAC8562
DAC8562 M68HC11 Interface Program Source Code
* * DAC8562 to M68HC11 Interface Assembly Program * Adolfo A. Garcia * September 14, 1992 * * M68HC11 Register definitions * PORTB EQU $1004 PORTC EQU $1003 Port C control register * 0,0,0,0;0,CLR/,CE/,MSB-LSB/ DDRC EQU $1007 Port C data direction * * RAM variables: MSBS are encoded from 0 (Hex) to F (Hex) * LSBS are encoded from 00 (Hex) to F (Hex) * DAC requires two 8-bit loads * MSBS EQU $00 Hi-byte: 0,0,0,0;MSB,DB10,DB9,DB8 LSBS EQU $01 Lo-byte: DB7,DB6,DB5,DB4;DB3,DB2, DB1,DB0 * * Main Program * ORG $C000 Start of users RAM in EVB INIT LDS #$CFFF Top of C page RAM * * Initialize Port C Outputs * LDAA #$07 0,0,0,0;0,1,1,1 STAA DDRC CLR/,CE/, and MSB-LSB/ are now enabled as outputs LDAA #$06 0,0.0,0;0,1,1,0 * CLR/-Hi, CE/-Hi, MSB-LSB/-Lo STAA PORTC Initialize Port C Outputs * * Call update subroutine * BSR UPDATE Xfer 2 8-bit words to DAC8562 JMP $E000 Restart BUFFALO * * Subroutine UPDATE * UPDATE PSHX Save registers X, Y, and A PSHY PSHA * * Enter contents of the Hi-byte input register * LDAA #$0A 0,0,0,0;1,0,1,0 STAA MSBS MSBS are set to 0A (Hex) * * Enter Contents of Lo-byte input register * LDAA #$AA 1,0,1,0;1,0,1,0 STAA LSBS LSBS are set to AA (Hex) * LDX #MSBS Stack pointer at 1st byte to send via Port B LDY #$1000 Stack pointer at on-chip registers * * Clear DAC output to zero * BCLR PORTC,Y $04 Assert CLR/ BSET PORTC,Y $04 De-assert CLR/ * * Loading input buffer latches * BSET PORTC,Y $01 Set hi-byte register load TFRLP LDAA 0,X Get a byte to transfer via Port B STAA PORTB Write data to input register INX Increment counter to next byte for transfer CPX #LSBS+1 Are we done yet ? BEQ DUMP If yes, update DAC output BCLR PORTC,Y $01 Latch hi-byte register and set lo-byte register load BRA TFRLP *

DAC8562M68HC11 Interface Program Source Code (Continued)


* Update DAC output with contents of input registers * DUMP BCLR PORTC,Y $02 Assert CE/ BSET PORTC,Y $02 Latch DAC register * PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program **

REV. A

15

DAC8562
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

20-Pin Plastic DIP (P-Suffix)


20 PIN 1 1 1.07 (27.18) MAX 0.145 (3.683) MIN 0.125 (3.175) MIN 0.021 (0.533) 0.015 (0.381) 0.11 (2.79) 0.09 (2.28) 0.065 (1.66) 0.045 (1.15) SEATING PLANE 0.135 (3.429) 0.125 (3.17) 10 0.32 (8.128) 0.30 (7.62)
0.20 (5.0) 0.14 (3.56) 0.15 (3.8) 0.125 (3.18)

20-Pin Cerdip (R-Suffix)


20 11 0.28 (7.11) 0.24 (6.1) 1 0.97 (24.64) 0.935 (23.75) 0.18 (4.57) 0.125 (3.18) 0.011 (0.28) 0.009 (0.23) 15 0.02 (0.5) 0.016 (0.14) 0.11 (2.79) 0.09 (2.28) 0.07 (1.78) 0.05 (1.27) SEATING PLANE 0 10 0.32 (8.128) 0.29 (7.366)

11 0.255 (6.477) 0.245 (6.223)


PIN 1

15 0

0.011 (0.28) 0.009 (0.23)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42.

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42.

20-Lead SOIC (S-Suffix)

20

11 0.299 (7.60) 0.291 (7.40)

PIN 1 1 10

0.419 (10.65) 0.404 (10.00)

0.512 (13.00) 0.496 (12.60) 0.107 (2.72) 0.089 (2.26) 0.011 (0.275) 0.005 (0.125) 0.050 (1.27) BSC 0.022 (0.56) 0.014 (0.36) 0.015 (0.38) 0.007 (0.18) 0.034 (0.86) 0.018 (0.46)

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REV. A

PRINTED IN U.S.A.

C17132410/92

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