Raquibul Hassan

061310045

M. Tawsif Salam
061069045


Instructor
Dr. K.M.A. Salam
NORTH SOUTH UNIVERSITY
Dhaka, Bangladesh
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ASSERTION



This is to state that this project is entirely our original work. No part of this work has been submitted
elsewhere fully or partially for the award of any other degree or diploma. In addition we assure that
any material reproduced in this project has been properly acknowledged.

Students Name and Signature



__________________________
Raquibul Hassan
ID: 061310045



__________________________
M. Tawsif Salam
ID: 061069045
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APPROVAL



The project tilted Measurement of Interface Trap Density of MOS has been submitted to the
following respected members of the Board of Examiners of the department of Electrical Engineering
& Computer Science in partial fulfillment of the requirements for the degree of Bachelor of Science
in Electronics and Telecommunication Engineering on the December 30, 2009 by the following
students has been accepted satisfactory.

Raquibul Hassan (061310045)
M. Tawsif Salam (061069045)





_____________________________ _____________________________

Dr. K.M.A. Salam Dr. Miftahur Rahman
Assistant Professor Professor and Chairman
Department of Electrical Engineering Department of Electrical Engineering
& Computer Science & Computer Science
North South University North South University
(Advisor)
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ABSTRACT



In our research work we are to make attempt to find out the interface trap density parameters of the
extensively used oxides in semiconductor devices, followed by the effort to show a comparison
between those of the oxides. We are to work on different high-k materials like hafnium dioxide,
aluminium oxide, titanium dioxide, hafnium silicate and compare the properties with silicon dioxide
to reach a conclusion that which of these materials would be the most favorable with respect to the
parameters concerning interface trap density D
it
to perform certain operations i.e. device scaling.
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ACKNOWLEDGEMENT



We are thankful to Almighty Allah SWT at the first place. We would also like to mention the love
and support of our families, that of our parents in particular, without which we could not have been
somewhere near to the completion.

Our deepest gratitude is to our academic and advisor Dr. K.M.A. Salam whose kind thoughts were
always with us. Mentions of our work to all extents would rightfully have to have his name too
without whose help we could not have overcome a number of obstacles we had faced.

We would like to express our deepest gratitude to Professor Dr. Miftahur Rahman, the chairman of
the Department of Electrical Engineering & Computer Science, for his kind guidance over the topic
and areas of our research at the initial stage.

Among the others we would like to thank, there is Syed Nafeesul Islam who was always there when
we needed a help. Many others of our well-wishers were there who are not being named all here for
understandable reasons, but we cannot do without mentioning them to acknowledge their help and
support and we wish every good to them.
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TABLE OF CONTENTS

Assertion ---------------------------------------------------------------------------------------------- 2
Approval ---------------------------------------------------------------------------------------------- 3
Acknowledgement ----------------------------------------------------------------------------------- 4
Abstract ------------------------------------------------------------------------------------------------5
List of Figures ---------------------------------------------------------------------------------------- 6
List of Tables ----------------------------------------------------------------------------------------- 7

Chapter 1
Introduction ---------------------------------------------------------------------------------------------- 9

Chapter 2
Background & Review --------------------------------------------------------------------------------- 10
2.1 MOSFET ----------------------------------------------------------------------------------10
2.1.1 Overview of MOSFET ------------------------------------------------------10
2.1.2 Organization and Operations of MOSFET Substances ------------------10
2.2 MOS Capacitor ---------------------------------------------------------------------------12
2.2.1 Function of MOS Capacitor ------------------------------------------------ 12
2.2.2 Frequency of MOS Capacitor and Effects -------------------------------- 13
2.3 Scaling ------------------------------------------------------------------------------------ 14
2.3.1 Necessities, Rules and Limitations of Scaling --------------------------- 14
2.4 High-K ------------------------------------------------------------------------------------ 16
2.5 Properties of High-K -------------------------------------------------------------------- 17
2.6 Interface Trap Density ------------------------------------------------------------------ 18
2.6.1 Nature of Interface Trap Density in Oxide Stack Gates ---------------- 19
2.6.2 Role of Interface Trap Density behind Degradation of MOSFET----- 19
2.6.3 Correlation between Leakage Current & Interface Trap Density ------ 19

Chapter 3
Methodology -------------------------------------------------------------------------------------------- 19
3.1 Scaling Flat-Band and Threshold Voltage -------------------------------------------- 19
3.2 Reasons for choosing the oxides ------------------------------------------------------- 19
3.3 The oxide type ---------------------------------------------------------------------------- 20
3.3.1 Silicon Dioxide --------------------------------------------------------------- 20
3.2.2 Hafnium Dioxide ------------------------------------------------------------- 20
3.3.3 Hafnium Silicate -------------------------------------------------------------- 21
3.4 Charge of the Oxides --------------------------------------------------------------------- 21
3.5 The Doping Concentration -------------------------------------------------------------- 21

Chapter 4
Implementation ------------------------------------------------------------------------------------------ 22
4.1 Calculation of Flat-band Voltage and Threshold Voltage --------------------------- 22
4.2 Interface Trapped Density Calculation ------------------------------------------------- 23

Chapter 5
Result of Simulation ------------------------------------------------------------------------------------ 24

Chapter 6
Conclusion ----------------------------------------------------------------------------------------------- 28

Bibliography --------------------------------------------------------------------------------------------- 30
Addendum I- Codes -------------------------------------------------------------------------------------32
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LIST OF FIGURES


1. (Fig 2.1) Structure of MOSFET, pg-11
2. (Fig 2.2) MOS capacitor Structure, pg-12
3. (Fig 2.3) The Three Modes of MOS Capacitor, pg-13
4. (Fig 2.4) Gate length vs. Technology Node, pg-14
5. (Fig 5.1) Typical Capacitance-Voltage curve, pg-25
6. (Fig 5.2) curve for high frequency capacitance, pg-25
7. (Fig 5.3) curve for low frequency capacitance, pg-26
8. (Fig 5.4) high frequency and low frequency c-v curve showing impact of
fast interface states, pg-26
9. (Fig 5.5) comparison plot of Dit values, pg-27
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LIST OF TABLES


1. (Table 3.1) Characteristics of the metal oxides, pg-20
2. (Table 3.2) Charge of oxides, pg-21
3. (Table 5.2) Comparison of Dit values for the oxides, pg-26
9 | P a g e

Chapter
1
INTRODUCTION



MOSFETs, standing for metaloxidesemiconductor field-effect transistors, presently are the most
extensively used as integrated chips for random access memories, processors, flash memories and
other application specified integrated circuitries (ASIC). MOSFET was invented in 1959 by Dawon
Kahng and Martin M. Atalla at Bell Laboratories in accordance with a principle proposed by Julius
Edgar Lilienfeld in 1925. A trend existed to form MOSFETs where aluminium was used as the
metal, silicon oxide as the oxide and silicon as the semiconductor substrate in MOSFETs until mid
the 1970s, when polycrystalline silicon or simply polysilicon started being used prevalently.

Polysilicon is used mostly because of its formation of a diamond cubic crystal structure that appears
to be mechanically a more stable structure than other known forms. Thus, the name metal at the
augmentation of MOSFET may be recognized as a misnomer as the previously used metal gate
material has been replaced by polysilicon.

MOSFETs have frequently been scaled down in size over the past decade, since the inception to be
specific. For example, Intel Corporation in late 2009 has had a process through production
introducing MOSFETs with 32 nanometer channel length, whereas this length once was several
micrometers long. This process of scaling down the MOSFET size is called MOSFET scaling, or
simply scaling.

George Earle Moore, a co-founder of Intel Corporation, theorized the process of scaling stating that
the number of transistors on an integrated circuit doubles every two years. Widely known as
Moores Law, it was introduced in a paper he published in April 1965. However in 2005 Moore
eventually concluded the law saying about a miniaturization limit, i.e. no further scaling will be
possible in next two or three generations as the transistors would reach the atomic level by size.

The thickness of the silicon dioxide gate dielectric in MOSFETS has steadily decreased, which
increased the gate capacitance and thereby device performances, as the transistors have decreased in
size. As the thickness scales below 2nm, leakage currents due to tunneling increase drastically,
leading to power consumption and reduced device reliability. Replacing the silicon dioxide gate
dielectric with a high-K material allows increased gate capacitance without the leakage effects.
When this dielectric constant K is too high, the charge also increases, meaning accumulation of too
much charge between the insulator and the substrate. This particular phenomenon of charge
accumulation is known as interface trapped density (D
it
).

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Chapter
2
BACKGROUND & REVIEW



In this chapter, brief descriptions on MOSFETs structure, operation and the scaling process are
presented eventually continuing to the discussion on interface trap density.


2.1 MOSFET

MOSFET is the field effect transistor meant to switch or amplify electronic signals.

Based on the principle proposed in 1925 by the Austrian-Hungarian (Ukraine in present days)
physicist Julius E. Lilienfeld, Bell Laboratories scientists Dawon Kahng and Martin Atalla, from
Korea and Egypt respectively, invented MOSFET in 1959. Though the initial formation of a
MOSFET comprised aluminium, silicon oxide and silicon respectively as metal, oxide and
semiconductor, polysilicon was introduced to replace aluminium in mid 1970s, mostly because of its
uniquely stable diamond cubic crystal structure.


2.1.1 Overview of MOSFET

MOSFETs structure thus the basic operation consists of an insulated gate electrode and two contacts
having a conducting channel between them. A voltage on the oxide-insulated gate electrode induces
the channel between the contacts, known as source and drain. Pragmatically, MOSFET works by
electronically varying the width of a channel along which charge-carriers (electrons and holes) flow.
The width of the channel, a criterion for the performance of MOSFET, is controlled by the gate
voltage. As the voltage is applied between the two terminals, the generated electric field permeates
the oxide to create the inversion layer. This inversion layer is the semiconductor-insulator
interface. The channels can be n-type or p-type, making the MOSFETs to be called nMOS and
pMOS respectively.


2.1.2 Organization and Operations of MOSFET Substances

To explain the MOS structure, a silicon substrate is taken to grow a layer of SiO
2
on its top and then
to deposit a layer of polysilicon in order to obtain the formation of a MOSFET.SiO
2
acts as a planar
11 | P a g e

capacitor in the process because of its ability to store energy (
r
or K= 3.9) over an applied voltage.
One of the electrodes here is replaced by a semiconductor.

A MOS structure adapts the mechanism to distribute charges after a voltage is applied across. For
example- if a positive voltage V
GB
is applied to a p-type semiconductor, a depletion layer is created
between the gate and body resulted by the forcing away of positive holes from the insulator-
semiconductor interface. The process leaves a carrier-free region of negatively charged ions to
exposure which concentrates to form in an inversion layer thinly located next to the insulator-
semiconductor interface. Here we may define the threshold voltage, which is the gate voltage where
volume density of electrons at inversion layer and the volume density of holes at body are the same.

Operations of MOSFET are based on the charge concentration adaption of a MOS capacitance
between the body and gate electrodes, located above the body and insulated from the other regions
of the device by a dielectric layer (an oxide i.e. SiO
2
). In case of nMOS, the source and drain are
n+ regions and the body is p region. Electrons from the source enter the inversion layer or the p-
region-oxide interface if the gate voltage is significantly above the threshold voltage. On other hand
in cases of the gate voltage below the threshold voltage, sub-threshold leakage current able to flow
between source and drain is low as the channel is lightly populated.


(Fig 2.1) Structure of MOSFET

In cases of pMOS, the source and drains are p+ regions and the body is a n region. When a
negative gate-to-source voltage (positive source-to-gate) is applied, it creates a p-channel at the
surface of the n-region, analogous to the n-channel case, but with opposite polarities of charges and
voltages. When a voltage less negative than the threshold value (a negative voltage for p-channel) is
applied between gate and source, the channel disappears and only a very small sub-threshold current
can flow between the source and the drain.


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2.2 MOS Capacitor

MOS capacitor is a voltage dependent capacitor consisting of a metal-oxide-semiconductor layer
structure. Details on threshold voltage of the transistor as well as the quality of oxide-
semiconductor interface may belong to the analysis of MOS capacitors.

Structure of a metal oxide semiconductor often comprises silicon, silicon dioxide and aluminium
as the semiconductor, oxide and metal respectively. Metal in most of the cases may be replaced
by extensively doped polysilicon layers as gate electrode. Contacts are made to the metal and to
the semiconductor. A voltage is applied to the metal while the semiconductor is grounded.


(Fig 2.2) MOS capacitor Structure


2.2.1 Function of MOS Capacitor

The capacitance of a MOS structure is voltage dependent since the semiconductor region under
the oxide can be either depleted of carriers, can accumulate carriers or an inversion layer can be
formed. For instance,

For a p-type substrate one finds that for a large negative voltage, V
G
, applied to the metal,
holes are attracted to the interface, causing accumulation.
A positive voltage on the other hand repels the holes that are present in the p-type
material and thereby creates a depletion layer.
A larger positive voltage at the gate causes sufficient bending of the energy bands in the
semiconductor at the interface so that inversion occurs, i.e. a change from holes being
the majority carrier type to electrons.
An even larger positive voltage causes strong inversion where the carrier density at the
oxide-semiconductor interface exceeds that of the opposite carrier type in the substrate.

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(Fig 2.3) The Three Modes of MOS Capacitor


2.2.2 Frequency on MOS Capacitor and Effects

The low frequency capacitance is measured when the semiconductor is in thermal equilibrium at
any time during which the AC voltage is applied. Such measurement is sometimes called the
quasi-static capacitance measurement. On the other hand, high frequency is used for the
concentration of minority carriers to not follow the applied AC voltage so that it maintains its
value as determined by the DC bias voltage. Both capacitance measurements are performed as a
function of the bias voltage, which is slowly swept from accumulation, through depletion into
inversion. High frequency capacitance is same as the oxide capacitance under accumulation
conditions. Since carriers can easily be moved to and from the interface, the charges build up at
both sides of the oxide as in a parallel plate capacitor. This change as the applied bias voltage
becomes positive, creating a depiction layer in the semiconductor. This depletion layer prevents
carriers from moving towards the semiconductor-oxide interface. The variation of the charge
therefore occurs at the edge of the depletion region so that the measured capacitance is the series
connection of the oxide capacitance and the depletion layer capacitance.

Inversion occurs finally at the interface as a larger positive voltage is applied. The presence of
inversion layer makes the depletion layer width almost independent of the applied voltage,
yielding a constant and minimal capacitance. The latter can be obtained from a series connection
of the oxide capacitance and the minimum capacitance of the depletion layer.

As soon the bias voltage is swept rapidly while performing a high capacitance measurement, the
condition of deep depletion appears. As the capacitor is bias from depletion into inversion the
inversion layer needs to be formed. This inversion layer is formed by thermal generation of
minority carriers in absence of light. Since the inversion layer density is much larger than the
thermal equilibrium value of the minority carrier density in the substrate, the time required to
generate the inversion layer is orders of magnitude larger than the minority carrier life time,
typically of the order of seconds in high quality silicon. The absence of the inversion layer
causes the depletion layer to be larger than its thermal equilibrium value, thereby lowering the
capacitance of the MOS structure.
14 | P a g e

The substrate doping is obtained from the MOS capacitance in inversion. The capacitance should
be independent of the applied voltage, but equals to the series connection of the oxide
capacitance and the capacitance of the depletion region. The potential across the depletion region
is 21 Fl so that the doping concentration can be obtained from the depletion layer capacitance..
The oxide capacitance too is obtained from the MOS Capacitance bias in accumulation, but this
time independent of the bias voltage and equals to the oxide capacitance

Flat-band capacitance may be calculated using the result from the exact solution described in the
following section. This enables to identify the flat-band voltage of the MOS for which u
F
= 0
Volt. The difference between the measured flat-band voltage and the expected value based on the
position of the Fermi level in the gate and the substrate is typically attributed to charge located at
the oxide-semiconductor interface or the charge in the oxide.


2.3 Scaling

In microelectronics, scaling refers to the scaling of geometric dimension of the intergraded
circuits, most of the cases being subject to reduction of the lateral geometric dimension of
devices and interconnects. International Technology Roadmap of Semiconductors (ITRS)
comprises the issue of scaling the constantly decreasing size of MOSFETs introduces some
difficulties associated with the fabrication process of semiconductor devices.


(Fig 2.4) Gate length vs. Technology Node


2.3.1 Necessities, Rules and Limitations of Scaling

Scaling appears being a vital issue in microelectronics as it is desired to have smaller size of
MOSFETs, mostly because,

As MOSFETs act like resistors at the ON state, it means that smaller MOSFETs will allow
more current to pass than that of bigger MOSFETs.
15 | P a g e

As smaller MOSFETs have smaller gates, this means the capacitance is lower which
contributes to lower switching times, i.e. higher processing speeds.
The simplest reason is, smaller MOSFETs mean occupation of smaller areas, which leads to
both the reduction of cost and more computing power in the same area.

However, propositions over the issue of scaling comprise some principles of the process, which
we may discuss as the rules of scaling,

Increase packing density and chip functionality.
Increase device current and speed.
Lower cost (increase cost effectiveness).
Constant Voltage gain
Constant-field scaling

Keeping the channel length smaller than a micrometer is a challenge in MOSFET production.
Even a more common limiting factor of scaling is the difficulties in the fabrication process of
semiconductor devices. There also exist operational problems in cases of smaller MOSFETs.

The voltage applied to the gate must be reduced to maintain reliability due to small MOSFET
geometries. To maintain performance, the threshold voltage of the MOSFET has to be reduced as
well As threshold voltage is seduced, the t cannot be completely turned off, resulting in a weak-
inversion layer, which consumes power in the form of sub-threshold leakage.

The switching time is roughly proportional to the gate capacitance of gates. However, with
transistors becoming smaller and more transistors being placed on the chip, interconnect
capacitance is increasing. This leads to increased delay and lower performance. The ever-
increasing density of MOSFETs is causing problems of heat generation that can impair circuit
operation. Circuits operate slower at high temperatures, and have reduced reliability and shorter
lifetimes. Heat sinks and other cooling methods are now required for integrated circuits.

The gate oxide, an insulator between the gate and channel, should be made as thin as possible to
increase the channel conductivity and performance when the transistor is on and to reduce sub-
threshold leakage when the transistor is off. However, with gate oxides of thickness around 1.2
nm tunneling leakage occurs between the gate and channel, leading to increased power
consumption. High-k dielectrics with larger dielectric constant than silicon dioxide, such as
hathium and zirconium silicates and oxides, are now researched to reduce the gate leakage.
Increasing the dielectric constant of the gate oxide material allows a thicker layer while
maintaining a high capacitance. The higher thickness reduces the tunneling current between the
gate and the channel.


2.4 High-K

The term high-K dielectric means the material (used in semiconductor manufacturing processes)
having high dielectric constant K as compared to silicon dioxide.

16 | P a g e

The thickness of the commonly used oxide SiO
2
gate dielectric has steadily decreased to increase
the gate capacitance and thereby device performance, as transistors has decreased in size. As the
thickness scales below 2nm, leakage currents due to tunneling increase drastically, leading to
power consumption and reduced device reliability. Increased gate capacitance without the
leakage effects is allowed by replacing the silicon dioxide gate dielectric with a high-K material.
As transistors shrink, leakage current can increase. Managing that leakage is crucial for reliable
high-speed operation, and is becoming an increasingly important factor in chip design. Intel has
made a significant breakthrough in solving the chip power problem, identifying a new high-k
(Hi-k) material called hafnium to replace the transistors silicon dioxide gate dielectric, and new
metals to replace the polysilicon gate electrode of NMOS and PMOS transistors. These new
materials reduce gate leakage more than 100-fold, while delivering record transistor
performance.


2.5 Properties of High-K Materials

High-k stands for high dielectric constant, a measure of how much charge a material can hold.
Different materials similarly have different abilities to hold charge. High-k materials, such as
hafnium dioxide (HfO2) zirconium dioxide (ZrO
2
) and titanium dioxide (TiO
2
) inherently have a
dielectric constant or k above 3.9. The dielectric constant also relates directly to transistor
performance. The higher k increases the transistor capacitance so that the transistor can switch
properly between and on and off states.

In pursuit of achieving record performance for both NMOS and PMOS technologies, Intel
identified the right high-k material and gate electrode materials. By moving to a new high-k
material, Intel was able to keep the drive current at the same level as with older material.

The exponentially increasing heat of chips with the increase in transistors is seen as a challenge
in semiconductor industry. Leakage control through new high-k materials is one of many steps
toward making transistors run cooler. As high-k gate dielectrics can be several times thicker,
they reduce gate leakage by over 100 times. As a result, these devices run cooler. This shift to a
new material will be one of the most significant in the evolution of the metal- oxide silicon
(MOS) transistor.

There are some disadvantages of high-k materials.

Firstly, if the dielectric constant is too high, then the charge also increases. This means that too
much charge accumulates between the insulator and the substrate. When charge accumulates
between the insulator and the substrate, this phenomenon is known as interface trapped density
(Dit).

17 | P a g e

Secondly, the problem with Hafnium Oxide is that it crystallizes above 700C but Hafnium
Silicate remains amorphous above 1000C.

Thirdly, the problem with Aluminum Oxide is that it accumulates too much negative charge.
When the charge increases, the interface trapped density (D
it
) also increases. This will result in
the shift of the flat-band voltage and as a result the threshold voltage will also increase. Increase
in the threshold voltage means that the leakage current will also increase. This is a disadvantage
with high-k materials since their dielectric constant is too high whereas the dielectric constant of
silicon is perfect to use.

Therefore by analyzing the high-k materials we can say that Hafnium Silicate is the most desired
material among all of them. One reason is because it has silicon in it, which keeps the dielectric
constant from becoming too high. But still we need to analyze the graphical representation of all
the high-k materials using MATLAB simulation to be exactly sure. Therefore although high-k
has some disadvantages, but still it is a good trade-off from silicon dioxide because it gives us
new possibilities to improve the MOS capacitor by scaling.


2.6 Interface Trapped density

The fact that these defects can change their charge state relatively faster in response to changes
of the gate bias refers to the term fast interface states.

The fast interface states or tarps can move above or below the Fermi level in response to the bias
as the surface potential in a MOS device is varied, because their position relative to the band-
edges are fixed. Having it known that the energy level below the Fermi level have a high
probability of occupancy by electrons while levels above Fermi level tend to be empty, it is
observed that a fast interface state moving above the Fermi level would tend to give up its
trapped electron to the semiconductor (or equivalently capture a hole). To explain, the same fast
interface state below the Fermi level captures an electron (or gives up a hole). The fast interface
states give rise to a capacitance which is in parallel with depletion capacitance in the channel
(and hence is additive) since charge storage results in capacitance. This combination is in series
with the insulator capacitance C
i
.

The fast interface states contribute to the low frequency capacitance CLF, but not to the high
frequency capacitance CHF. Because the fast interface states can keep pace with the low
frequency variations of the gate bias (~1-1000 Hz) but not at extremely high frequencies (~1
MHz).



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2.6.1 Nature of Interface Trap Density in Oxide Stack Gates

The classical concept and theory suggest that the degradation of MOS transistors is caused by
interface trap generation resulting from hot carrier injection. Experiments that use the
deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS
transistors in the presence of hot hole and electron injection show that hot carrier injection into
the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the
interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons,
not carriers injected into the gate oxide, are primarily responsible for interface trap generation for
standard hot carrier stressing.

Traps in the high- gate stacks play a crucial role in threshold voltage, channel mobility, and
reliability. We have carried out an extensive experimental investigation of interface traps in the
Si/SiO2/HfO2/TaN structures employing a powerful new admittance spectroscopy technique for
leaky gate dielectrics, to extract the trap parameters - trap density, trap energy, trap capture
cross-section, and trap location. The experiments were carried out on MOS (Metal- Oxide-
Semiconductor) capacitors on wafers with graded SiO2 thickness. The flat-band voltage roll-off
remains a very important phenomenon, explanations for which are not unanimous. We have
carried out extensive measurements of the flat-band voltage as a function of the EOT (Equivalent
Oxide Thickness) on a large number of MOS structures having different thickness of the SiO2
layer and two sets of HfO2 layer thickness. We report the observed correlation between the
flatband voltage variation with EOT with the change in the interface trap density with the EOT.


2.6.2 Role of Interface Trap Density behind Degradation of MOSFET

The classical concept and theory suggest that the degradation of MOS transistors is caused by
interface trap generation resulting from hot carrier injection. Experiments that use the
deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS
transistors in the presence of hot hole and electron injection show that hot carrier injection into
the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the
interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons,
not carriers injected into the gate oxide, are primarily responsible for interface trap generation for
standard hot carrier stressing.


2.6.3 Correlation between Leakage Current & Interface Trap Density

As gate oxide is scaled below the direct tunneling regime, gate leakage current has become the
dominant concern especially for nonvolatile memories and complementary metaloxide
semiconductor CMOS logic circuits for low power and portable applications. In thick oxides,
gate leakage is due primarily to stress-induced leakage current which has both transient and
steady-state components. Another important phenomenon in thin oxide is quasi breakdown. This
is characterized by a localized leakage current of much higher magnitude than conventional
SILC but lower than complete breakdown. The gate leakage current after QB shows steplike
fluctuations, which is due to the occurrences and modulation of multiple QB spots at different
spatial locations.
19 | P a g e

Chapter
3
METHODOLOGY



3.1 Scaling Flat-Band and Threshold voltage

The amount of leakage current increases with the sealing of transistors as the oxide layer
thickness decreases. Thickness of the oxide layer has to be increased to improve this condition,
for the threshold voltage being scaled and the leakage current minimized. But with conventional
devices the oxide thickness cannot be increased, as a result we have to change the structure of the
device. In place of silicon oxide we can use other oxides like Hafnium Dioxide and Lead Oxide.

The C-V curve is a practical way to determine the variation of the Threshold Voltage and the
Flat-band Voltage. This variation mainly occurs due to the change in the dielectric constant k
of the oxide used and the charge of the oxides Compared to silicon dioxide the other oxides that
we are using have a substantial higher dielectric constant.

Our purpose of the research is to compare the different oxides used graphically and to obtain the
best possible outcome for the device. Also to establish the fact that the capacitancevoltage
graph used gives an accurate result. The following parameters are going to be tested during our
comparison like

a) The dielectric constant.
b) The oxide thickness.


3.2 Reasons for choosing the oxides

Silicon dioxide is a good insulator. Replacing the SiO2 with a material having a different
dielectric constant is not as simple as it may seem. The material bulk and interface properties
must be comparable to those of silicone dioxide, which are remarkably good. For instance,
thermodynamic stability with respect to silicon, stability under thermal conditions relevant to
microelectronic fabrication, low diffusion coefficients, and thermal expansion match are quite
critical. With these objectives in mind, recent research on high-k dielectrics has primarily
focused on metal oxides and their silicates, Among these, the group JVb transition metals Zr and
Hf have generated a substantial amount of investigations. Aluminum and Titanium have also
been two other metals, which have been considered. These metals and their oxides are
20 | P a g e

compatible with silicon and that is one of the reasons for considering these. The table 3.1 shows
the characteristics of the metal oxides.

Oxides
Doping
Concentration
(em
3
)
Thickness,
L
ox
(nm)
Dielectric
Constant, K
ox

Band Gap,
Eg (ev)
Silicon dioxide (SiO2)
10
16
1.5 3.9 1.12
Hafnium Dioxide (HfO2)
10
16
.5 25 6
Hafnium Silicate (HfSiO4)
10
16
1.5 15 -

(Table 3.1) Characteristics of the metal oxides

3.3 The oxide type

Here are the brief discussions on different oxides used and their properties. We begin with the
most commonly used oxide in the existing MOSFETs.


3.3.1 Silicon Dioxide

Being an important constituent of a great many minerals and gemstones, Silicon dioxide (silica)
is one of the most commonly encountered substances in both daily life and in electronics
manufacturing. Crystalline silicon dioxide is used both in pure form and mixed with related
oxides. Under exposure to oxygen, a silicon surface oxidizes to form silicon dioxide (SiO
2
).
Native silicon dioxide is a high-quality electrical insulator and can be used as a barrier material
during impurity implants of diffusion, for electrical isolation of semiconductor devices, as a
component in MOS transistors, or as an interlayer dielectric in multilevel metallization structures
such as multichip modules. Silicon has become a prevalent semiconductor material used in
integrated circuits today mostly because of its ability to form a native oxide was one of the
primary processing considerations.


3.2.2 Hafnium Dioxide

Hafnium (IV) oxide is the inorganic compound with the formula Hf0 Also known as hafnia, this
colorless solid is one of the most common arid stable compounds of hafnium. It is an electrical
insulator with a band gap of approximately 6eV.

Hafnia is used as a high-k dielectric in capacitors. Hafnium-based oxides are currently leading
candidates to replace silicon oxide as a gate insulator in field effect transistors the advantage for
21 | P a g e

transistors is its high dielectric constant: The dielectric constant of Ht0 is 25 while the dielectric
constant of HfO2 is 25, while the dielectric constant of SiO2 is only 3.9.

The compound appears to have been chosen by both IBM and Intel as a substrate for future
integrated circuits, where it may help in the continuing effort to increase logic density and clock
speeds, or to lower power consumption, in computer processors.


3.3.3 Hafnium Silicate

Hafnium silicate (HfSiO4) is a chemical compound, a silicate of hafnium. Thin films of hafnium
silicate and zirconium silicate produced by chemical vapor deposition, most often MOCVD, can
be used as a high-k dielectric as a replacement for silicon dioxide in semiconductors. It has an
average dielectric constant of 15 which makes it suitable of the oxide usage.


3.4 Charge of the Oxides

Large charges the used high-k oxides have (compared to SiO
2
) get trapped between the insulator
and oxide giving rise to a phenomenon called the interface trapped density. The higher the
charge, the higher the interface trapped density. There is a shift in the flat-band voltage because
of this interface trapped density and it results in an increased threshold voltage. This also results
in an increase of the leakage current. Therefore high-k oxides with minimum dielectric constant
are to be chosen e.g. Hafnium Silicate, where high-k is not so high since the silicon in the
compound keeps the dielectric constant steady.

Oxides Charge (Coulomb)
SiO2
6.4*10
.
-9
HfO2 1.12*10
.
-7
HfSiO4 1.44*10
.
-8
(Table 3.2) Charge of oxides

3.5 The Doping Concentration

All electronic and optical semiconductor devices incorporate dopants as a crucial ingredient of
their device structure. Almost all of the basic MOSFET parameters are affected by the
distribution of dopants in the device. Doping refers to the process of introducing impurity atoms
into a semiconductor region in a controllable manner in order to define the electrical properties
of this region. The doping with donors and acceptors allows modifying the electron and hole
concentration in silicon in a very large range from 1013 cm3 up to 1021 cm3. The carrier
concentration can also be varied spatially quite accurately which is used to produce pn-junctions
and built-in electric fields.
22 | P a g e

Chapter
4
IMPLEMENTATION


The MOS (Metal Oxide Semiconductor) capacitor consists of a metal-oxide- semiconductor layer
structure, which forms a voltage dependent capacitor. This particular structure has been studied
extensively because it is present in all MOS transistors. The MOS capacitor is voltage dependent and
we have used this varying voltage to determine the Capacitance of the device.

Our purpose is to obtain a graph which represents the Capacitance- Voltage characteristics of a MOS
device, which; we can later manipulate to get our desired outcome.

As the capacitor is voltage dependent, first when a negative voltage is applied holes are attracted to
the interface, causing accumulation. A positive voltage on the other hand repels the holes that are
present in the p-type material and thereby creates a depletion layer. A larger positive voltage at the
gate causes sufficient bending of the energy bands in the semiconductor at the interface so that
inversion occurs, i.e. a change from holes being the majority carrier type to electrons. So the
capacitance has three equations in three cases. We have used these equations to generate the graph.


4.1 Calculation of Flat-band Voltage and Threshold Voltage

We have calculated the Flat-band voltage from the equation below,

V
fb
= u
ms
Q
ss
/ C
ox


Where,
V
fb
= The Flat-band Voltage
u
ms
= The work function difference between the metal and the semiconductor
Q
ss
= The surface charge density
C
ox
= Capacitance of the oxide

Afterwards we have calculated the Threshold Voltage
ox
C
fp
Na e
s
fp fb
V
th
V / * 2 * * * * 2 * 2
|
|
.
|

\
|
|
|
.
|

\
|
u e + u + =




23 | P a g e

4.2 Interface Trapped Density Calculation

We have calculated the interface trapped density from the equation below



Where,

= Insulator capacitance
= Low frequency capacitance
= High frequency capacitance
q = electron charge
24 | P a g e


Chapter
5
RESULT OF SIMULATION



We have taken a conventional way of plotting the Capacitance-Voltage curve. Our instructor
provided us with the testing values of capacitance for both high and low frequency for their
corresponding gate voltage.
0
50
100
150
200
250
300
-10 -8 -6 -4 -2 0 2 4 6 8 10
Gate voltage V
g
(Volts)
C
a
p
a
c
i
t
a
n
c
e

p
F


Figure 5.1 Typical Capacitance-Voltage curve.

From our simulation, for High frequency we got the following figure,

Figure 5.2 curve for high frequency capacitance
25 | P a g e

And for low frequency we got the following figure.

Figure 5.3 curve for low frequency capacitance


Figure 5.4 high frequency and low frequency c-v curve showing impact of fast interface states



26 | P a g e

Oxides D
it

SiO2 -0.2
HfSiO4 0.48
TiO2 0.5
Al2O3 0.55
(Table 5.2) Comparison of D
it
values for the oxides


Figure 5.5 comparison plots of D
it
values

From the above figures we can say our c-v curve plotting is a success. As the fast interface states
can keep pace with the low frequency variations of the gate bias(~1-1000 Hz), but not at
extremely high frequencies(~1 MHz). So the fast interface states contribute to the low frequency
capacitance but not to the high frequency capacitance , we have plotted SiO
2
and HfSiO
4

, TiO
2
, Al
2
O
3
. The difference in the D
it
value is because HfSiO
4
, TiO
2
, Al2O
3
are high k
27 | P a g e

material. So when the dielectric constant is high then the charge also increases. This means that
too much charge accumulates between the insulator and the substrate. When the charge
increases, interface trapped density also increases.

In the above figure we have plotted SiO2 and HfSiO4 that is Hafnium Silicate. It is a special kind of
oxide where a thin film of hafnium dioxide is deposited on a layer of silicon dioxide. The difference
in the Dit value is because HFSiO4 is a high k material. So when the dielectric constant is high then
the charge also increases. This means that too much charge accumulates between the insulator and
the substrate. When the charge increases, interface trapped density also increases.
28 | P a g e

Chapter
6
CONCLUSION



From the observation we did earlier, we can state we can conclude that Hafnium Silicate
(HfSiO
4
) is the most desired among all the high-k materials. The problem with Aluminum Oxide
is that it accumulates too much negative charge. When the charge increases, the interface trapped
density (Dit) also increases. This results in the shift of the flat-band voltage and as a result the
threshold voltage also increases. Increase in the threshold voltage means that the leakage current
also increases. This is a disadvantage with highk materials since their dielectric constant is too
high whereas the dielectric constant of silicon is perfect to use. Therefore by analyzing the high
materials we can say that Hafnium Silicate is the most desired material among the others. The
reason may be that it has silicon in it which keeps the dielectric constant from becoming too high
and keeps it steady. From our simulation we showed Hafnium Silicate has larger interface
trapped density compared to SiO2. Although high-k has some disadvantages, but still it is a good
trade-off from silicon dioxide because it gives us new possibilities to improve the MOS capacitor
by scaling.
29 | P a g e
















ADDENDA
30 | P a g e

Addendum
I
BIBLIOGRAPHY



1. E.F. Schubert,Rensselacr Polytechnic Institute, 2003
2. OMara, William C. (1990). Handbook of Semiconductor Silicon Technology, William
Andrew Inc. p. 349352. ISBN 0815512376. Retrieved 2008-02-24.
3. 1965-Moores Law Predicts the Future of Integrated Circuits. Computer History
Museum.
4. Intel 45nm Hi-k Silicon Technology, Retrived May, 2010.
5. Principles of Electronic Devices, Bart J. Van Zeghbroeck 1996
6. International Technology Roadmap for Sethiconductors,2009
7. Robert H. Dennard, Fritz H. Gaensslen, HwaNien Yu, V Leo Rideout, Ernest Bassours,
and Andre R. LcBlanc, Design of Ion-Implanted MOSEETs with Very Small Physical
Dimensions, IEEEE J. Solid State Circuits, SC-9 (5), 256 (1974)
8. Kaushik Roy, Kiat Seng Yeo (2004). Low Voltage, Low Power VLSI Subsystems.
McGraw-Hill Professional., p. 44. ISBN 007 143786X
9. Moore, Gordon E. (1965). Cramming more components onto integrated circuits .
Electronics Magazine. pp. 4. Press_Releases/Gordon_Moore_1965_Article.pdf. Retrieved
2006-1 1-11.
10. 1965 Moores Law Predicts the Future of Integrated Circuits. Computer History
Museum. 2007. Retrieved 2010-05-19.
11. Disco, Cornelius; van der Meulen, Barend (1998). Getting new technologies together. New
York: Walter de Gruyter. pp. 206207. Retrieved 23 August 2008.
12. IEEE Spectrum: The High-k Solution, Retrieved July, 2010
13. Mark T. Bohr, Robert S. Chau, Tahir Ghani, Kaizad Mistry, I ugh-k Solution, October
2007
14. Lynn Townsend White, Jr. (1961). Eilmer of Malmesbury, an Eleventh Century Aviator:
A Case Study of Technological Innovation, Its Context and
15. Tradition. Technology and Culture 2 (2).
16. Greenwood, Norman N.; Earnshaw, A. (1984), chemistry c the Elements, Oxford:
Pergamon, pp. 1117-19, ISBN 0-08-022057-6.
17. Greenwood, Norman N.; Earnshaw, A. (1984), Chemistry of the Elements, Oxford:
Pergamon. pp. 1117-19, ISBN 0-08-022057-6
18. G.D. Wilk, R.M. Wallace, J.m. Anthony, High-k gate dielectric: Current status and
materials properties consideration. J.Appl. Phys. APPLIED PHYSICS REVIEW, Vol.89,
number 9 (2901) 5243
19. Review article by Wilk et al. in the Journal of Applied Physics, Table I
31 | P a g e

20. Intel Says Chips Will Run Faster, Using L Power. New York Times, 2007-01-27.
21. Prof. Dr. Helmut Foil, University of Kid, Semiconductor Skript, Retrieved August,
2010.
22. S. K. Lei, Interface trap generation in silicon dioxide when electronsare captured by
trapped holes, J. Appl. Phys., vol. 54, pp. 25402546, 1983.
23. B. S. Doyle, M. Bourcerie, J.-C. Marchetaux, and A. Boudou, Interface trap creation and
charge trapping in the medium-to-high gate voltage range during hot carrier stressing of n-
MOS transistors, IEEE Trans. Electron Devices, vol. 37, pp. 744754, 1990.
32 | P a g e

Addendum
II
CODE



%% Dit Calculation

ci=[1.73e-6 8.85e-6 1.42e-4 9.96e-6];
vg=[-0.22 0.48 0.5 0.55];


%%SiO2 data
clf_s=7e-12;
chf_s=4.3e-12;
q_s=1.6e-19;

%%HFSiO4 data
clf_hf=7.72e-11;
chf_hf=4.53e-12;
q_hf=1.6e-19;

%%TiO2 data
clf_t=7.78e-11;
chf_t=4.54e-12;
q_t=1.6e-19;

%%Al2O3 data
clf_a=7.81e-11;
chf_a=4.43e-12;
q_a=1.6e-19;

%%Calculation of Dit
my_dit(1)=((ci(1)*clf_s)/(ci(1)-clf_s)-(ci(1)*chf_s)/(ci(1)-
chf_s))/q_s;
fprintf('Dit for SiO2');
disp(my_dit(1));

my_dit(2)=((ci(2)*clf_hf)/(ci(2)-clf_hf)-(ci(2)*chf_hf)/(ci(2)-
chf_hf))/q_hf;
fprintf('Dit for HF');
disp(my_dit(2));

my_dit(3)=((ci(3)*clf_t)/(ci(3)-clf_t)-(ci(3)*chf_t)/(ci(3)-
chf_t))/q_t;
fprintf('Dit for TiO2');
disp(my_dit(3));

33 | P a g e

my_dit(4)=((ci(4)*clf_a)/(ci(4)-clf_a)-(ci(4)*chf_a)/(ci(4)-
chf_a))/q_a;
fprintf('Dit for Al2O3');
disp(my_dit(4));

%%Point plot
plot(vg,my_dit,'O');
xlabel('Vg---->');
ylabel('Dit---->');
text(0.4,my_dit(2),'Dit For HF');
text(-0.2,my_dit(1),'Dit For SiO2');
text(0.56,my_dit(4)*1.01,'Dit For Al2O3');
text(0.51,my_dit(3)*0.98,'Dit For TiO2');
grid on;
%% Chf values
chf=[4.50E-12
4.49E-12
4.50E-12
4.61E-12
4.48E-12
4.44E-12
4.49E-12
4.47E-12
4.54E-12
4.50E-12
4.47E-12
4.42E-12
4.48E-12
4.37E-12
4.32E-12
4.34E-12
4.47E-12
4.73E-12
5.25E-12
6.06E-12
8.10E-12
1.53E-11
3.18E-11
4.98E-11
6.13E-11
6.76E-11
7.16E-11
7.41E-11
7.59E-11
7.73E-11
7.83E-11
7.90E-11
7.98E-11
8.03E-11
8.07E-11
8.10E-11
8.14E-11
8.17E-11
34 | P a g e

8.19E-11
8.21E-11
8.24E-11
];
%% Vg values
vg=[1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
-2.1
-2.2
-2.3
-2.4
-2.5
-2.6
-2.7
];
%% Clf values
clf=[8.82E-11
8.23E-11
8.20E-11
8.14E-11
8.10E-11
35 | P a g e

8.03E-11
7.97E-11
7.86E-11
7.78E-11
7.62E-11
7.35E-11
6.99E-11
6.36E-11
5.06E-11
2.43E-11
7.89E-12
6.28E-12
7.08E-12
7.69E-12
8.76E-12
1.08E-11
1.67E-11
3.26E-11
5.04E-11
6.19E-11
6.84E-11
7.24E-11
7.48E-11
7.69E-11
7.81E-11
7.90E-11
7.99E-11
8.06E-11
8.10E-11
8.15E-11
8.19E-11
8.25E-11
8.25E-11
8.27E-11
8.29E-11
8.32E-11
];
%% Curve Plot
plot(vg,chf,vg,clf,'--');
legend('Chf vs. Vg','Clf vs. Vg');
xlabel('Voltage (Vg)-------->');
ylabel('Capacitance (Chf) & (Clf)-------->');