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ASIC Verification
Hello Everyone, This is My first blog ever. I have created this blog to discuss about various topics in the field of ASIC. You'll find lot of useful information about verification. Keep visiting this site for more updates.

Showing posts with label State Machine. Show all posts

MO NDA Y , A PR IL 21, 2008

Sequence Detector - Solution

The solution for the problem is given here.

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Posted by Suresh at 12:19:00 PM Labels: Digital, State Machine

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About Me Suresh I did my Master of Engineering in College of Engineering, Guindy Anna University in 2001-2002 and currently working as a ASIC Verification Engineer. View my complete profile

FR IDA Y , A PR IL 18, 2008

Sequence Detector
Design a state machine, that outputs a '1' one and only when two of the last 3 inputs are '1'. For example, if the input sequence is 0110_1110 then the output will be 0011_1101. Assume that the input 'x' is a single bit serial line.

Posted by Suresh at 2:37:00 PM Labels: Digital, State Machine

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T H UR S DA Y , A PR IL 17, 2008

Digital (18) Specman Tutorial (12)

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Counter design using FSM

chipverification.blogspot.in/search/label/State Machine

12/11/12

ASIC Verification: State Machine

Design a 3-bit counter that counts in binary or in Gray code, depending on the values of a mode control input. This synchronous 3-bit counter has a mode control input m. As long as m = 0, the counter steps through the binary sequence 000, 001, 010, 011, 100, 101, 110, 111 and repeats this sequence. As long as m = 1, the counter advances through the Gray code sequence 000, 001, 011, 010, 110, 111, 101, 100 and repeats this sequence. However, it is possible that the mode input changes at any time in any of these sequences. For example, assume that the mode input is 0 for the first two clock cycles but changes to 1 in the third clock cycle and stays at 1 in the fourth clock cycle. (That is, m goes through the sequence 0, 0, 1, 1.) Then, the output will be 000, 001, 010, 110, 111. In this example, 000 is the initial state. The first two state transitions (000->001->010) occurs in the binary counting mode. Then, because m = 1 from the third clock cycle onwards, the state goes from 010->110->->111, as indicated in the Gray code sequence. In addition to the mode control input, there is a reset input. This synchronous counter should go to the 000 state if asserted.

Verification (10) Verilog (8) Learn C (6) Timing (6) Synthesis (5) General (4) SOC (4) Specman (4) State Machine (4) DFT (3) RTL (3) FPGA (2) Gate level simulation (2) Low power (2) VHDL (2) VLSI (2) AMS (1)

Posted by Suresh at 12:46:00 AM Labels: Digital, State Machine

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CMOS (1) Clock divider (1) FIFO (1)

FSM Problem
Construct a synchronous moore state machine with two inputs, A and B, and two outputs, X and Y. The machine accepts data on two input lines synchronously with the clock. The output X is 1 if and only if the data on the two input lines have been identical (i.e. A and B are both 1, or A and B are both 0) for the last three or more consecutive clock cycles. Output Y is 1 if and only if the data on the two input lines have been complements of each other (i.e. A = 1 and B = 0, or A = 0 and B = 1) for the last three or more consecutive clock cycles.

Reset (1) Archives 2011 (2) 2008 (86) Sep (5) Aug (1) Jul (5) Jun (6) May (10) Apr (15) Guidelines for improving the performance of synthe... Older Posts SOC Verification 3 Will we ever get a handle on SoC verification cost... SOC Verification 2 SOC Verification 1 Sequence Detector - Solution Sequence Detector Mod - 10 counter DAG

Posted by Suresh at 12:04:00 AM Labels: Digital, State Machine Home Subscribe to: Posts (Atom)

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12/11/12

ASIC Verification: State Machine

Counter design using FSM FSM Problem Clock Tree Synthesis State Diagram Depth of the Asynchronous FIFO Functional Coverage vs Code Coverage Mar (27) Feb (17) BlogRoll Adventures in ASIC digital design ASIC Planet Cool Verification Digital Electronics Digital Verification Specman Verification Think Verification

Introduction to VLSI design by IIT Professor

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ASIC Verification: State Machine

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