Outline

Introduction Is there a limit? Transistors CMOS building blocks Parasitics I The [un]desirables Parasitics II Building a full MOS model The CMOS inverter A masterpiece Technology scaling Smaller, Faster and Cooler Technology Building an inverter Gates I Just like LEGO The pass gate An useful complement Gates II A portfolio Sequential circuits Time also counts! DLLs and PLLs A brief introduction Storage elements A bit in memory
Parasitics II 1

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Building a full MOS model

MOS process parasitics pn-Junction diodes Depletion capacitance Source/drain resistance MOS Model Parasitic bipolars Device hazards:
Latchup Electrostatic discharge
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MOS Parasitics
In a CMOS process the devices are: PMOS FETs NMOS FETs + unwanted (but ubiquitous): pn-Junction diodes parasitic capacitance parasitic resistance and parasitic bipolars parasitic inductance
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Parasitics or useful?
Resistors Capacitors Inductors Diodes Bipolar transistors Are useful circuit elements for analogue circuit design. Some technologies offer the possibility of manufacture such devices under controlled conditions.
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pn-Junction diodes
pn Junction diodes:
Provide isolation between devices (if reversed biased) Can be used to implement:
band-gap circuits (if forward biased) variable capacitors clamping devices level shifting

Are extremely useful as Electro Static Discharge (ESD) protection devices.

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Parasitics II

CMOS devices
Remember:
Every source and drain creates a pn-junction pn-junctions must be reversed biased to provide isolation between devices Reversed biased pn-junctions display parasitic capacitance
NMOS PMOS

Aluminium contact

(Oxide cut)
Gate W L Al

Polysilicon Gate

SiO

p+

n+ p-substrate

n+

p+ n-well

p+

n+

Substrate contact

Source

Drain

Drain

Source

n-well contact

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Parasitics II

pn-Junctions diodes
Any pn-junction in the IC forms a diode Majority carriers diffuse from regions of high to regions of low concentration The electric field of the depletion region counteracts diffusion In equilibrium there is no net flow of carriers in the diode
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Al

Anode

Cathode

SiO 2

n+ p-substrate Depletion region Diffusion Anode e

+ -

n+
+ + + -

+ -

Drift h

Cathode

Parasitics II

Depletion capacitance
The depletion, the nand the p-type regions form a capacitor This capacitor is bias dependent:
Cj = C j0 V 1 0
m

Junction capacitance (fF/ m2 )

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -5

C j0 = 0.5 fF/m 2 0 = 0.64 V m = 0.33 (linear junction)

Simplification: for V<0

C j = k C j0
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-4

-3

-2

-1

Bias voltage (V)

Source/drain resistance
Scaled down devices higher source/drain resistance: Ls ,d
Rs ,d = W Rsq + Rc

In sub- processes silicidation is used to reduce the source, drain and gate parasitic resistance
Drain contact Source contact

0.24 m process 0.24 m process R (P+) = 4 /sq R (P+) = 4 /sq R (N-) = 4 /sq R (N-) = 4 /sq

Ld
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Ls
Parasitics II 9

MOSFET model
D RD CGD CBD

- VBD + G
Rds

iD - VBS +

CGS CGB

CBS

RS

S
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CMOS parasitic bipolar

Every p-n-p or n-p-n regions form parasitic bipolar transistors. In standard MOS circuits these devices must be turned off. For some applications (like bandgap circuits) these devices can be used. But, better know what you are doing
substrate contact Drain p+ Gate Source p+ n-well contact n+ n-well

p+

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Parasitics II

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CMOS device hazards

CMOS latchup origin Vdd R n-well p+ n+ n+ p+ p+ n+ Rn-well n-well Rp-subs R p-subs

Vdd

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Parasitics II

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CMOS device hazards

Sources of latchup:
Electrical disturbance Transient on power and ground buses Improper power sequencing Radiation ESD

How to avoid it:

Technological methods (beta reduction, substrate resistance reduction, trench isolation) Layout rules:
Spacing rules Contact distribution Guard rings
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CMOS device hazards

ESD protection

VDD

VDD

Input pad

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Parasitics II

14