Applications of PLLs

Frequency synthesis: Generation of a (possibly time-varying) desired frequency (or several

desired frequencies) from an available fixed-frequency reference
-
Skew compensation: required to maintain precise alignment of a clock when driving a large
capacitive load
-
Clock recovery: generation of a clock from a data signal -
Tuning and biasing: Use of a precision time (frequency) reference to aid in tuning or biasing an
analog circuit. Example:
-
Phase locked loops (PLLs)
Thursday, November 12, 2009
12:27 PM
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Basic block diagram
Basic operation is to ensure, thorugh feedback, that the phase difference (as measured by the
"phase detector") remains very small.
Voltage Controlled Oscillator (VCO)
An oscillator with nominal output frequency e
o
:
(The output need not be exactly sinusoidal; all of the analysis that follows works for any periodic
wave-shape.)
The instantaneous frequency of the sinusoid is given by:
We now define the VCOs instantaneous frequency deviation (away from its nominal value):
Hence,
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and
Taking Lapace transforms gives us
This VCO circuit is designed so that its instantaneous frequency is proportional to the control
voltage applied, V
cntrl
,
Hence, we get a s-domain model of the VCO:
Divider
f
out
= f
in
/ N
Example: N = 4
Note also that with respect to any arbitrary reference t=0, the phase in radians of the input and
output are related by:
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Hence, if the phase of V
div
is precisely tracking that of V
in
, so will the phase of the output clock,
V
osc
Phase Detector
Produces an average output that is proportional to the difference in the phase of the output
clocks.
It is usually a digital logic circuit that outputs Early/Late pulses whose width is determined by
the time delay between the arrival of edges on V
in
and V
div
. These logic signals are used to
determine the duration of current pulses using analog current sources and switches.
P
u
is used to "pull-up" the output frequency (because its phase is lagging behind that of the
reference clock).
P
d
is used to "pull-down" the output frequency.
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Loop Filter
An analog filter used to average out the current pulses from the charge pump and obtain their
time-averaged value.
Example:
Usually, C
2
<< C
1
. Hence,
This can be written,
where
Linear Model of the PLL
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Caution - this is a continuous-time model for a discrete-time system. Hence, it is only valid at
frequencies well below the reference clock frequency.
Note, the loop has infinite gain at dc. Hence, in steady-state, the phase difference |
d
must be
zero ensuring that the output phase | and input phase |
in
are equal.
Define the loop constant,
Using the 1st-order loop filter model from above, the (open) loop response is
The closed-loop response is
Notice that if there were no zero in the transfer function (R = 0 in the loop filter above, e
z
= ),
the loop would be unstable.
where
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Q > 0.5 is not usually desirable as it leads to peaking in the loop's frequency response, and lots of
overshoot in the transiet response. This implies that we must take e
z
< e
pll
/ 2 to ensure stability.
So, the zero has an important influence on the system response.
Q = 0.5 provides fast settling and provides reasonable values for the components in the loop
filter. In this case, the closed-loop poles are real and coincident at -e
pll
, and the closed-loop
bandwidth is
The factor of 2.5 is because of the zero at 0.5e
pll
Q << 0.5 provides very little peaking/overshoot in the loop response (which is required in some
applications). In this case, it can be shown that the response is approximately first-order
With a bandwidth of
Note that for Q << 0.5, w
z
<< w
pll
meaning that there are vastly disparate time-constant in the
loop. This is difficult to achieve without having large components (resistors and/or capacitors)
in the loop filter, which can be costly to integrate on-chip.
Effect of C
2
This all neglects C
2
in the loop filter above. (It assumes C
2
= 0.) C
2
is necessary because
otherwise all of the charge-pump current pulses whould be forced to flow through resistor, R,
resulting in a large voltage spike on V
cntrl
which will cause problems in the circuit, and is not
modeled anywhere in the linear model above (which considers only the average current coming
out of the charge pump).
Including C
2
adds another pole to the loop response:
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The 2nd pole reduces the phase margin around the loop. To maintain good stability, we place
the new pole at 2x the loop bandwidth.
For Q=0.5, this translates to C
2
~ 0.1C
1
.
For Q = 0.1, this translates to C
2
= 0.004C
1
(note the huge component value spread which will
mean that C
1
must be quite large).
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LC Oscillator
Simplest form:
As long as
the circuit will oscillate at e
0
2
= 1 / LC
To be integrated, this requires an inductor on-chip:
Ring Oscillator
Voltage Controlled Oscillators
Thursday, November 12, 2009
1:26 PM
Page 10
Note that n=1 will not oscillate because it is a stable feedback system.
Ring vs. LC Oscillator
Generally, ring oscillators consume more power when operating at high frequency than a LC
oscillator, and are also noisier. But, they consume less area - especially at lower oscillator
frequencies where the inductor in an LC oscillator would have to be very large. Hence, LC
oscillators are usually reserved for applications where high-frequency and/or very high spectral
purity are required.
Differential ring oscillators
To ensure the ring does not latch-up, it must have an odd number of stages. (e.g. n=2 stages is
simply a CMOS latch)
Latch-up can be avoided if the "inverters" are differential buffers, usually desirable from a
supply-rejection point-of-view anyway; in this case, a "crossing" the differential signals gives,
effectively, an additional inversion stage (with zero delay).
e.g. n=4
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Example of a differential buffer stage:
Another example:
Above circuit adapted from:
Maneatis, J.G.; Horowitz, M.A., "Precise delay generation using coupled oscillators," Solid-State
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Circuits, IEEE Journal of , vol.28, no.12, pp.1273-1282, Dec 1993
Another possibility is to simple use digital inverters, but with the supply voltage as the frequency
control, V
cntl
.
Sidiropoulos, S.; Dean Liu; Jaeha Kim; Guyeon Wei; Horowitz, M., "Adaptive bandwidth DLLs
and PLLs using regulated supply CMOS buffers," VLSI Circuits, 2000. Digest of Technical
Papers. 2000 Symposium on , vol., no., pp.124-127, 2000
The basic inverter shown above can be replaced by a differential version of it.
For example, the following reference describes in detail a PLL design based on this approach:
Chang, K.-Y.K.; Wei, J.; Huang, C.; Li, S.; Donnelly, K.; Horowitz, M.; Yingxuan Li;
Sidiropoulos, S., "A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop
PLLs," Solid-State Circuits, IEEE Journal of , vol.38, no.5, pp. 747-754, May 2003
Page 13
Absolute jitter:
t
k
is a discrete-time random process in units of time (seconds)
|
k
is the represents the same random process in units of phase (radians)
Phase Noise
Like all random processes, it has a power spectral density.
S
|
(f) = [ the one-sided fourier transform of the autocorrelation of |
k
]
Since t
k
is a discrete-time process, strictly speaking S
|
(f) is defined only over the range 0 to 1/2T
o
The variance of |
k
is integral of S
|
(f) over all frequencies.
Expressed in units of time (seconds), the variance of t
k
is
and its rms alue is

rms absolute jitter
Jitter and Phase Noise
Monday, November 30, 2009
7:37 AM
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Absolute jitter is a useful analytical tool, but difficult to measure since it requires a perfect time
reference. So, it is important to understand how it is related to quantities that we can more easily
observe and which may be of significant practical importance.
Period Jitter or Cycle Jitter:
The deviation of each period from its nominal (ideal) value, T
0
.
It is the time-derivative of absolute jitter. Hence, its power spectrum is the phase noise, passed
through a differentiating (1 - z
-1
) filter:
This filtering is intuitive since only fast variations in the clock phase give rise to period jitter.
P-Cycle Jitter
This can be extended to consider the deviation of the duration of any P consecutive periods from
the nominal (ideal) value, PT
0
:
Adjacent Period Jitter or Cycle-to-cycle Jitter
C
k
= T
k+1
- T
k
= J
k+1
+ J
k
obtained by passing the cycle jitter through another differentiating operation
Clock power spectrum
Note that the clock's power spectrum will be spread around the carrier frequency. The amount of
spreading depends on the amount of jitter.
We can shift this spectrum to dc and normalize it with respect to the total power in the carrier to get
another spectral representation of jitter.
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The relationship between +(Af) and S
|
(f) is complex (involving Bessel functions), but when S
|
(f) is
small,
Jitter Histogram
In the absence of any direct frequency modulation (such as may occur when there is significant
interference from supply noise concentrated at a particular frequency) jitter generally originates
from many superimposed random noise sources. Hence, the PDF of t
k
is typically Gaussian.
Phase Noise of Oscillators
It may be shown that white noise superimposed on an oscillatory waveform (at the output of an
oscillator) gives rise to white phase noise. This arises, for instance, in any clock buffer/amplifier.
e.g. common-source amplifier:
Neglecting the flicker noise, the output sinusoid has superimposed the thermal noise of the
transistor and resistor. This translates into a shift in the zero-crossing time related to the slope of
the clock around the transitions:
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For this reason, fast transition times in clocks generally results in less phase noise.
For sinusoidal signals, this means having high amplitude
----
Noise sources arising within the oscillator itself are shaped by the oscillator's response.
An oscillatory linear system G(s) has poles on the imaginary axis at jf
0
At frequencies near f
0
, its frequency resposnse is dominated by that pole
Hence, white noise introduced within the oscillator is shaped by this frequency response.
--
Finally, some noise sources are mixed with the oscillating signal itself, upconverting it to f
0
. When
this is done within the oscillator circuit, it is also shaped by |G| as shown above. One typical
example of this is the tail current in a differential pair within the oscillator:
In summary, there are 3 important phase noise sources in integrated oscillators:
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Together, they may be modeled as follows:
Jitter and Phase Noise in PLLs
There are several sources of jitter in a PLL:
Jitter on the reference clock: |
in
(k) , S
|,in
(f) -
Jitter generated by the VCO: |
VCO
(k) , S
|,osc
(f) -
Noise in the loop filter (mostly from the resistor, R): v
n
, V
n
(f) -
Noise in the divider circuitry: |
n
(k) , S
|,n
(f) -
e.g. loop filter noise:
Once the PLL has acquired lock, these noise sources represent small disturbances from the steady-
state operating point of the loop; hence, the linear model may be used:
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All noise spectra are filtered by the corresponding closed-loop PLL responses and superimposed at
the output:
Input reference and
divider noise
Lowpass
VCO phase noise Highpass
Loop filter noise Bandpass
Shown above are plots for Q = 1/2
The plot above ignores C
2
, hence |H(f)| has a -20dB/decade slope at high frequencies (2nd order
denominator, 1st order numerator). The addition of C
2
adds another high-frequency pole that
improves the high-frequency rolloff to -40 dB/decade.
A typical plot of the phase noise at the output of a PLL showing the main contributors:
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