FROM: Gekas G DATE: Jun.

19, 2004 10:17 am gmt SUBJECT: Verilog Vga controller problem Hi, I am a new in HDL synthesis and programming of programmable devices. Currently I am working on a mouse project and I have problems with my vga_controller module. Despite the fact that in Modelsim simulation everything works as needed, when I program a Xilinx 4010XL device, nothing works as it should. The module that I test is a simple vga controller that generates 2 pulses h_sync and v_sync so as the display works in 640*400 resolution @60Hz. I also have 6 bits for the colours (rgb). In modelsim everything works perfect but in the real thing, the screen doesn't receive any signal or the signals (h_sync and v_sync) are unsynchronized. Below I provide my Verilog code, so whoever has a bit of free time, please take a look at it. Note that the design must run at 25Mhz. //Here is the module. The job that I want this to do is create a totally //black screen with a //white cursor (32*32 pixels) drawn on the upper left //corner of the screen (co ordinates (0, 0)). module vga_controller(clk, reset, h_sync, v_sync, rgb); input clk, reset; output h_sync, v_sync; output [5:0] rgb; wire [9:0] h_counter; wire [8:0] v_counter; reg h_sync, v_sync; reg [5:0] rgb; reg [9:0] x_pos; reg [8:0] y_pos; parameter h_counter_start_value = 10'd751; parameter v_counter_start_value = 9'd413; parameter zero = 4'b000; parameter low = 1'b0; wire [9:0] up_bound_x; wire [8:0] up_bound_y; wire row_fin, h_sync_low, v_sync_high; wire rgb_wire; //The ports of the below modules are described as this //counter_X(set (synchronous), reset (asynchronous), clock, data_in, chip_enable , output_count) counter_10 inst0(h_counter == 10'd800, reset, clk, h_counter_start_value, !reset , h_counter); counter_9 inst1(v_counter == 9'd449, reset, clk, v_counter_start_value, row_fin, v_counter); assign row_fin = (h_counter == 10'd751); //End of one line of pixels assign h_sync_low = (h_counter > 10'd654 & h_counter < 10'd751) ? 1'b0 : 1'b1; assign v_sync_high = (v_counter > 9'd410 & v_counter < 9'd413) ? 1'b1 : 1'b0; //Upper bounds of coordinations in the screen assign up_bound_x = {x_pos[9:5] + 1, x_pos[4:0]}; assign up_bound_y = {y_pos[8:5] + 1, y_pos[4:0]}; assign rgb_wire = (h_counter < up_bound_x & h_counter >= x_pos & v_counter < up_bound_y & v_counter >= y_pos ) ? 1 : 0; always @(posedge reset or posedge clk) if(reset) begin rgb <= 6'b000000; h_sync <= 0; v_sync <= 1;

x_pos <= 0; y_pos <= 0; end else begin h_sync <= h_sync_low; if(row_fin) v_sync <= v_sync_high; if(rgb_wire) rgb <= 6'b111111; else rgb <= 6'b000000; end endmodule