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Comparison between Diode Clamped and H-Bridge Multilevel Inverter (5 to 15 odd levels)

1

ABSTRACT

Multilevel converters are increasingly being considered for high power applications because of their ability to operate at higher output voltages while producing lower levels of harmonic components in the switched output voltages. Two well known multilevel converter topologies are the Neutral Point Clamped (NPC) Inverter and Cascaded inverter. One of the major problems in electric power quality is the harmonic contents. There are several methods of indicating the quantity of harmonic contents. The most widely used measure is the total harmonic distortion (THD). Various switching techniques have been used in static converters to reduce the output harmonic content. Pulse Width Modulation techniques for multilevel inverters have been developed very intensively in recent years. Many carriers based and sinusoidal PWM (SPWM) techniques for multilevel inverters have been properly deduced from that of two-level inverter. In contrast, Phase Disposition (PD) modulation of a NPC inverter is harmonically superior, because it places harmonic energy directly into the carrier harmonic for each phase leg, and relies on cancellation of this harmonic across phase legs as the line-toline voltage is developed. Many different PWM-strategies for multi-level inverters exist. This paper compares the various multi level circuits (diode clamped and H-Bridge) with SPWM strategies. Operating principles with switching functions are analyzed for Five to Fifteen (odd) levels SPWM inverter. Five-level to fifteen level (odd levels) SPWM inverter is presented to alleviate harmonic components of output voltage. Results are carryout by using Matlab simulink. Keywords : Multilevel Inverter, Diode Clamped, H-Bridge Inverter, SPWM.

1. INTRODUCTION

The schematic of inverter system is as shown in Fig. 1, in which the battery or rectifier provides the dc supply to the inverter. The inverter is used to control the fundamental voltage magnitude and the frequency of the ac output voltage. AC loads may require constant or adjustable voltage at their input terminals, when such loads are

____________________________ 1

Research Scholar ,2Assistant Professor, 1,2Department of Electrical & Electronics Engineering, Data Institute of Information & Technology, Vishakhapatnam, Andhra Pradesh, INDIA. *Correspondence : ddp206@gmail.com

Dhana Prasad Duggapu et al / VSRD International Journal of Electrical, Electronics & Comm. Engg. Vol. 2 (5), 2012

fed by inverters, it is essential that the output voltage of the inverters is so controlled as to fulfill the requirement of the loads. For example if the inverter supplies power to a magnetic circuit, such as a induction motor, the voltage to frequency ratio at the inverter output terminals must be kept constant. This avoids saturation in the magnetic circuit of the device fed by the inverter.

Fig. 1 : Schematic for Inverter System As in the single phase voltage source inverters PWM technique can be used in three-phase inverters, in which three sine waves phase shifted by 120 with the frequency of the desired output voltage is compared with a very high frequency carrier triangle, the two signals are mixed in a comparator whose output is high when the sine wave is greater than the triangle and the comparator output is low when the sine wave or typically called the modulation signal is smaller than the triangle. This phenomenon is shown in Fig. 2. As is explained the output voltage from the inverter is not smooth but is a discrete waveform and so it is more likely than the output wave consists of harmonics, which are not usually desirable since they deteriorate the performance of the load, to which these voltages are applied.

Fig. 2: PWM Illustration by the Sine-Triangle Comparison : (a) Sine-Triangle Comparison (b) Switching Pulses Recent advances in power electronics have made the multilevel concept practical. In fact, the concept is so advantageous that several major drives manufacturers have obtained recent patents on multilevel power converters and associated switching techniques. It is evident that the multilevel concept will be a prominent choice for power electronic systems in future years, especially for medium-voltage operation. Multi-level

Dhana Prasad Duggapu et al / VSRD International Journal of Electrical, Electronics & Comm. Engg. Vol. 2 (5), 2012

inverters are the modification of basic bridge inverters. They are normally connected in series to form stacks of level. The number of levels in an inverter bridge defines the number of direct current (DC) voltage steps that are required by the inverter bridge in order to achieve a certain voltage level at its output. Because power semiconductor switches have limited voltage capability, the total DC bus voltage of an inverter bridge is divided into a number of voltage steps, such that each voltage step can be handled by one power switch. For high power applications, voltages and currents must be pushed up. Hence, maximum ratings of power semiconductors become a real handicap. Paralleling devices, subsystems and systems leads to higher current levels. On the other hand, series connections are the solution for dealing with larger voltages. Nevertheless, given a chain of devices connected in series, achieving static and dynamic voltage sharing among switches become a problem. This will also affect the reliability of the system. An advantage of multilevel inverters compared with the classical twolevel topology, is that the output voltage spectra are significantly improved due to having a greater availability of voltage levels, Hence, the output voltages can be filtered with smaller reactive components, and additionally, the switching frequencies of the devices can be reduced. These two benefits, together with the ability to deal with higher voltage levels, confer on multilevel inverters a very important role in the field of high power applications. The intriguing feature of the multilevel inverter structures is their ability to scale up the kilovoltampere (KVA) rating and also to improve the harmonic performance greatly without having to resort to PWM techniques. The key features of a multilevel structure follow: The output voltage and power increase with number of levels. Adding a voltage level involves adding a main switching device to each phase. The harmonic content decreases as the number of levels increases and filtering requirements are reduced. With additional voltage levels, the voltage waveform has more free-switching angles, which can be reselected for harmonic elimination. In the absence of any PWM techniques, the switching losses can be avoided. Increasing output voltage and power does not require an increase in rating of individual device. Static and dynamic voltage sharing among the switching devices is built into the structure through either clamping diodes or capacitors. The switching devices do not encounter any voltage-sharing problems. For this reason, multilevel inverters can easily be applied for high-power applications such as large motor drives and utility supplies. The fundamental output voltage of the inverter is set by the dc bus voltage Vdc, which can be controlled through a variable dc link. As introduced in the first chapter, the total harmonics distortion (THD) is mathematically given by

Dhana Prasad Duggapu et al / VSRD International Journal of Electrical, Electronics & Comm. Engg. Vol. 2 (5), 2012

Where: H1 is the amplitudes of the fundamental component, whose frequency is w0 and Hn is the amplitudes of the nth harmonics at frequency nw0

Therefore, output voltage THD of the presented waveform can be calculated. Theoretically, to get exact THD, infinite harmonics need to be calculated. However, it is not possible in practice. Therefore, certain number of harmonics will be given. It relies on how precise THD is needed. Usually, n = 63 is reasonably accepted. Several combinational designs have also emerged some involving cascading the fundamental topologies. These designs can create higher power quality for a given number of semiconductor devices than the fundamental topologies alone due to a multiplying effect of the number of levels. The most actively developed of multilevel topologies are listed in Fig. 3.

Fig. 3 : Multilevel Converter Topologies All three multilevel inverters can be used in reactive power compensation without having the voltage unbalance problem. Table 1 compares the power component requirements per phase leg among the three multilevel voltage source inverter mentioned below. It shows that the number of main switches and main diodes, needed by the inverters to achieve the same number of voltage levels. Clamping diodes were not needed in flying-capacitor and cascaded-inverter configuration, while balancing capacitors were not needed in diode clamp and cascadedinverter configuration. Implicitly, the multilevel converter using cascaded-inverters requires the least number of components.

Table 1 : Comparison of Power Component Requirements per Phase Leg among Three Multilevel Inverters Inverter Configuration Main switching devices Main diodes Clamping diodes DC bus capacitors Balancing Capacitors Diode Clamped 2 (m1) 2 (m1) (m1) (m2) (m 1) 0 Flying Capacitors 2(m1) 2(m1) 0 (m 1) (m 1) (m 2)/2 Cascaded inverter 2(m1) 2(m1) 0 (m 1)/2 0

The multilevel topology involves several modulation techniques. Each technique involves different modulation methods. The well-known modulation topologies for multi level inverters as follows: Sinusoidal or Sub harmonic Natural Pulse Width Modulation (SPWM). Selective Harmonic Eliminated Pulse Width Modulation (SHE PWM) or Programmed-Waveform Pulse Width Modulation (PWPWM). Optimized Harmonic Stepped-Waveform Technique (OHSW).

The advent of the transformer less multilevel inverter topology has brought forth various pulse width modulation (PWM) schemes as a means to control the switching of the active devices in each of the multiple voltage levels in the inverter. The most efficient method of controlling the output voltage is to incorporate pulse width modulation control (PWM control) within the inverters. In this method, a fixed d.c. input voltage is supplied to the inverter and a controlled A.C. output voltage is obtained by adjusting the on andoff periods of the inverter devices. Voltage-type PWM inverters have been applied widely to such fields as power supplies and motor drivers. This is because: (1) such inverters are well adapted to high-speed self turn-off switching devices that, as solid-state power converters, are provided with recently developed advanced circuits; and (2) they are operated stably and can be controlled well.

Fig. 4 : Multilevel Modulation Techniques From the above all mentioned PWM control methods, the Sinusoidal pulse width modulation (SPWM) is

applied in the proposed inverter since it has various advantages over other techniques. Sinusoidal PWM inverters provide an easy way to control amplitude, frequency and harmonics contents of the output voltage. Sinusoidal pulse width modulation (SPWM) is one of the primitive techniques, which are used to suppress harmonics presented in the quasi-square wave. In the modulation techniques, there are two important defined parameters: 1) the ratio P = fc/fm known as frequency ratio, and 2) the ratio Ma = Am/Ac known as modulation index, where fc is the reference frequency, fm is the carrier frequency, Am is reference signal amplitude and Ac is carrier signal amplitude. For NPC multilevel inverters, most carrier based modulation strategies derive from disposition techniques developed by Carrara et al, where for an M level inverter, M-1 carriers of identical frequency and amplitude are arranged to occupy contiguous bands between +VDC and -VDC. These carriers can be arranged in: Alternative Phase Opposition Disposition (APOD), where each carrier is phase shifted by 1800 from its adjacent carriers. Phase Opposition Disposition (POD) where the carriers above the reference zero point is out of phase with those below the zero point by 1800. Phase Disposition (PD) where all carriers are in phase.

For Cascaded Inverters, the common modulation strategy is to use continuous three levels PWM within each individual inverter, with phase shifted carriers between the cascaded inverters of each phase leg to achieve optimum harmonic cancellation within the phase leg. Recent work has shown that this modulation strategy achieves the same harmonic performance as the APOD technique for NPC inverters when the switching frequencies are normalized so as to achieve the same overall number of switching transitions per fundamental cycle. From this understanding, an improved modulation strategy for Cascaded inverters has been developed using a discontinuous three level PWM strategy with 1800 phase shifted carriers within each full bridge inverter, which achieves the same harmonic performance on a line- to-line basis as does PD modulation for a NPC inverter. Since the Hybrid inverter topology is derived from the Cascaded structure it is reasonable to expect that a similar situation exists for the Hybrid inverter.

Assuming that all DC side capacitors have the same voltage E, different switching modes provide different output voltages. The voltage Vout in the table is the line-to-neutral voltage. The number of inverter level comes from the voltage levels. In every operating mode, four switches are in on state and the other four are in off state. If the inverter output voltage changes only between two contiguous modes, the main switch voltage and main diode voltage will not exceed E. Some of the clamped diodes, however, do need to have higher rating than E. For example, the DB2 voltage rating should be 2E. From the five modes switching operation, another advantage of multilevel inverter over the series switches 2-level VSI is that there is no possibility of simultaneous operation of the series switches (shoot through).

Fig. 5 : Five Level Diode Bridge Inverter The fundamental requirement for the diode-clamped multilevel inverter switching scheme is to ensure that the switches operate in the contiguous modes listed in Table 2. The most popular and simple methods are step modulation and SPWM. In step modulation, four voltage levels are compared with the sinusoid reference waveform as shown in Fig. 6. The result is used to control all the main switches.

Table 2

For 5-level inverter two three level H-Bridges are connected in series and make this two ceels input voltage is equal. This is also called as symmetrical configuration. 7 level 3-phase H-bridge inverter and phase output voltage are shown in Fig. 7 and Fig. 8 respectively.

Fig. 8 : Switching Strategies for Five Level H-Bridge Inverter The DC source for the first H-bridge (H1) is a DC power source with an output voltage of Vdc, while the DC source for the second H-bridge (H2) is a capacitor voltage to be held at Vdc /2. The output voltage of the first Hbridge is denoted by v1 and the output of the second H-bridge is denoted by v2 so that the output of this two DC source cascade multilevel inverter is v(t)=v1(t)+v2(t) By opening and closing the switches of H1 appropriately, the output voltage v1 can be made equal to - Vdc , 0, or Vdc while the output voltage of H2 can be made equal to - Vdc/2, 0, or Vdc/2 by opening and closing its switches appropriately. Therefore, the output voltage of the inverter can have the values - 3Vdc/2, - Vdc, - Vdc /2, 0, Vdc /2, Vdc, 3Vdc/2, which is seven levels and based on diode clamped and H-bridge is shown in Fig. 9 and Fig. 10 respectively. This fig shows how a waveform can be generated using the topology of Fig. 11.

Fig. 11 : 7-Level Equal Step Output Voltage Waveform The nine-level diode clamped and cascaded inverter shown in Fig. 12 and Fig. 13 respectively.

Fig. 13 : Nine Level H-Bridge Inverter and Switching Strategies Similarly we can design 11, 13 and 15 level of both Diode clamped and H-Bridge inverter.

4. EXPERIMENTAL RESULTS

Diode Clamped:

Fig (a)

Fig (b) Fig. 14 (a) & (b) represent 5 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 5 (n=5, the number of step are n=5) for quarter wave and 10 (n=5, the number of step are 2n =10) for full wave, from this fig. m=1 magnitude is 187.5V and m=0.8 magnitude is 162.5V.

Fig (a)

Fig (b) Fig .15 (a) & (b) represent 5 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 10 (n=5, the number of step are 2n=10) for quarter wave and 20 (n=5, the number of step are 4n=20)

for full wave, from this fig. m=1 magnitude is 325V and m=0.8 magnitude is 275V.

Fig (a)

Fig (b) Fig. 16 (a) & (b) represent 7 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 7 (n=7, the number of step are n=7) for quarter wave and 14 (n=7, the number of step are 2n =14) for full wave from this fig. m=1 magnitude is 295.5V and m=0.8 magnitude is 245.5V

Fig (a)

Fig (b) Fig. 17 (a) & (b) represent 7 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 14 (n=7, the number of step are 2n=14) for quarter wave and 28 (n=7, the number of step are 4n=28) for full wave from this fig. m=1 magnitude is 520V and m=0.8 magnitude is 430V

Fig (a)

Fig (b) Fig .18 (a) & (b) represent 9 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 9 (n=9, the number of step are n=9) for quarter wave and 18 (n=9, the number of step are 2n =18) for

full wave from this fig. m=1 magnitude is 394.5V and m=0.8 magnitude is 324.44V

Fig (a)

Fig (b) Fig. 19 (a) & (b) represent 9 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 18 (n=9, the number of step are 2n=18) for quarter wave and 36 (n=9, the number of step are 4n=36) for full wave from this fig. m=1 magnitude is 680V and m=0.8 magnitude is 563.3V

Fig (a)

Fig (b) Fig. 20 (a) & (b) represent 11 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are (n=11, the number of steps are n=11) for quarter wave and 22 (n=11, the number of steps are 2n=22) for full wave & fig (b) are 9 (n=11, for the number of steps are n-2=9 because hear m=0.8 so, 2 Gtos are in off state in each half wave in every phase) for quarter wave and 18 (n=11, for the number of steps are 2(n-2)=18) for full wave from this fig. m=1 magnitude is 497.15V and m=0.8 magnitude is 392.8V.

Fig (a)

Fig (b) Fig 21 (a) & (b) represent 11 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) & fig (b) are 22 (n=11, the number of steps are 2n=22) for quarter wave and 44 (n=11, for the number of

steps are 4n=44) for full wave & fig (b) are 18 (n=11, for the number of steps are 2(n-2)=18 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 44 (n=11, for the number of steps are 4(n-2)=36) for full wave from this fig. m=1 magnitude is 862.5V and m=0.8 magnitude is 687.5V.

Fig (a)

Fig (b) Fig. 22 (a) & (b) represent 13 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are 13 (n=13, the number of steps are n=13) for quarter wave and 26 (n=13, the number of steps are 2n=26) for full wave & fig (b) are 11 (n=13, for the number of steps are n-2=11 because hear m=0.8 so, 2 Gtos are in off state in each half wave in every phase) for quarter wave and 22 (n=13, for the number of steps are 2(n2)=22) for full wave from this fig. m=1 magnitude is 596.6V and m=0.8 magnitude is 474.5.

Fig (a)

Fig (b) Fig. 23 (a) & (b) represent 13 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) & fig (b) are 26 (n=13, for the number of steps are 2n=26) for quarter wave and 52 (n=13, for the number of steps are 4n=52) for full wave & fig (b) are 22 (n=13, for the number of steps are 2(n-2)=22 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 44 (n=13, for the number of steps are 4(n-2)=44) for full wave from this fig. m=1 magnitude is 1038.46V and m=0.8 magnitude is 834.62V.

Fig (a)

Fig (b) Fig. 24 (a) & (b) represent 15 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are 15 (n=15, for the number of steps are n=15) for quarter wave and 30 (n=15, for the number of steps are 2n=30) for full wave & fig (b) are 13 (n=15, for the number of steps are n-2=13 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 26 (n=15, for the number of steps are 2(n2)=26) for full wave from this fig. m=1 magnitude is 689.6V and m=0.8 magnitude is559.2V

Fig (a)

Fig (b) Fig. 25 (a) & (b) represent 15 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are 30 (n=15, for the number of steps are 2n=30) for quarter wave and 60 (n=15, for the number of steps are 4n=60) for full wave & fig (b) are 26 (n=15, for the number of steps are 2(n-2)=26 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 52 (n=15, for the number of steps are 4(n-2)=52) for full wave from this fig. m=1 magnitude is 1195.3V and m=0.8 magnitude is 961.5V. (a) H-Bridge:

Fig (a)

Fig (b) Fig. 26 (a) & (b) represent 5 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 5 (n=5, the number of step are n=5) for quarter wave and 10 (n=5, the number of step are 2n =10) for full wave, from this fig. m=1 magnitude is 194.44V and m=0.8 magnitude is 168.2V.

Fig (a)

Fig (b) Fig. 27 (a) & (b) represent 5 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 10 (n=5, the number of step are 2n=10) for quarter wave and 20 (n=5, the number of step are 4n=20) for full wave, from this fig. m=1 magnitude is 334.07V and m=0.8 magnitude is 290.91V

Fig (a)

Fig (b) Fig. 28 (a) & (b) represent 7 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 7 (n=7, the number of step are n=7) for quarter wave and 14 (n=7, the number of step are 2n =14) for full wave, from this fig. m=1 magnitude is 292.3V and m=0.8 magnitude is 242.3V.

Fig (a)

Fig (b) Fig. 29 (a) & (b) represent 7 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 14 (n=7, the number of step are 2n=14) for quarter wave and 28 (n=7, the number of step are 4n=28) for full wave, from this fig. m=1 magnitude is 507.7V and m=0.8 magnitude is 423.07V

Fig (a)

Fig (b)

Fig. 30 (a) & (b) represent 9 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 9 (n=9, the number of step are n=9) for quarter wave and 18 (n=9, the number of step are 2n =18) for full wave, from this fig. m=1 magnitude is 392V and m=0.8 magnitude is 323V.

Fig (a)

Fig (b) Fig. 31 (a) & (b) represent 9 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig a & fig b are 18 (n=9, the number of step are 2n=18) for quarter wave and 36 (n=9, the number of step are 4n=36) for full wave, from this fig. m=1 magnitude is 682V and m=0.8 magnitude is 560V

Fig (a)

Fig (b) Fig. 32 (a) & (b) represent 11 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are (n=11, the number of steps are n=11) for quarter wave and 22 (n=11, the number of steps are 2n=22) for full wave & fig (b) are 9 (n=11, for the number of steps are n-2=9 because hear m=0.8 so, 2 Gtos are in off state in each half wave in every phase) for quarter wave and 18 (n=11, for the number of steps are 2(n-2)=18) for full wave, from this fig. m=1 magnitude is 493.75V and m=0.8 magnitude is 393.75V.

Fig (a)

Fig (b)

Fig. 33 (a) & (b) represent 11 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) & fig (b) are 22 (n=11, the number of steps are 2n=22) for quarter wave and 44 (n=11, for the number of steps are 4n=44) for full wave & fig (b) are 18 (n=11, for the number of steps are 2(n-2)=18 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 44 (n=11, for the number of steps are 4(n-2)=36) for full wave, from this fig. m=1 magnitude is 855V and m=0.8 magnitude is 680V.

Fig (a)

Fig (b) Fig. 34 (a) & (b) represent 13 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are 13 (n=13, the number of steps are n=13) for quarter wave and 26 (n=13, the number of steps are 2n=26) for full wave & fig (b) are 11 (n=13, for the number of steps are n-2=11 because hear m=0.8 so, 2 Gtos are in off state in each half wave in every phase) for quarter wave and 22 (n=13, for the number of steps are 2(n2)=22) for full wave, from this fig. m=1 magnitude is 590.8V and m=0.8 magnitude is 476.92V.

Fig (a)

Fig (b) Fig. 35 (a) & (b) represent 13 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) & fig (b) are 26 (n=13, for the number of steps are 2n=26) for quarter wave and 52 (n=13, for the number of steps are 4n=52) for full wave & fig (b) are 22 (n=13, for the number of steps are 2(n-2)=22 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 44 (n=13, for the number of steps are 4(n-2)=44) for full wave, from this fig. m=1 magnitude is 1033.33V and m=0.8 magnitude is 829.12V.

Fig (a)

Fig (b) Fig. 36 (a) & (b) represent 15 level phase voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig (a) are 15 (n=15, for the number of steps are n=15) for quarter wave and 30 (n=15, for the number of steps are 2n=30) for full wave & fig (b) are 13 (n=15, for the number of steps are n-2=13 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 26 (n=15, for the number of steps are 2(n2)=26) for full wave, from this fig. m=1 magnitude is 700V and m=0.8 magnitude is 560V.

Fig (a)

Fig (b) Fig. 37 (a) & (b) represent 15 level line voltages at modulation index (m) is 1 and 0.8 respectively, steps of fig

(a) are 30 (n=15, for the number of steps are 2n=30) for quarter wave and 60 (n=15, for the number of steps are 4n=60) for full wave & fig (b) are 26 (n=15, for the number of steps are 2(n-2)=26 because hear m=0.8 so 2 Gtos are in off state in each half wave in every phase) for quarter wave and 52 (n=15, for the number of steps are 4(n-2)=52) for full wave, from this fig. m=1 magnitude is 1200V and m=0.8 magnitude is 976.92V. Table 3 : Comparison of diode and H-Bridge inverters with different modulation index (m=1 and m=0.8) Level(N) Index(M) 5 7 9 11 13 15 M=1 M=0.8 M=1 M=0.8 M=1 M=0.8 M=1 M=0.8 M=1 M=0.8 M=1 M=0.8 Phase voltages Diode H-Bridge T E T E 200 187.5 200 194.4 160 162.5 160 168.2 300 295.5 300 292.3 240 245.5 240 242.3 400 394.5 400 392 320 324.4 320 323 500 497.2 500 493.8 400 392.8 400 393.8 600 596.6 600 590.8 480 474.5 480 476.9 700 689.6 700 700 560 559.2 560 560 Line voltages Diode H-Bridge T E T E 346.4 325.0 346.4 334.1 277.1 275.0 277.1 290.9 519.6 520.0 519.6 507.7 415.7 430.0 415.7 423.1 692.8 680.0 692.8 682 554.3 563.3 554.3 560 866.0 862.5 866.0 855 692.8 687.5 692.8 680 1039 1038 1039 1033 831.4 834.6 831.4 829.1 1212 1195 1212 1200 969.9 961.5 969.9 976.9 THD (without Filter) Diode 38.75 38.74 21.18 26.68 17.2 18.49 11.65 15.1 12.16 12.93 8.78 10.19 H-Bridge 31.77 37.81 21.27 27.84 15.39 19.96 12.94 17.37 10.84 13.47 9.275 12.05

5. CONCLUSION

This paper has provided a brief summary of multilevel inverter circuit topologies and their switching strategies. Different applications using different inverter circuits were also discussed. Today, more and more commercial products are based on the multilevel inverter structure, and more and more worldwide research and development of multilevel inverter-related technologies is occurring. Multilevel carrier-based PWM offers many more degrees of freedom than traditional two-level PWM. In multilevel PWM, the switching frequency can be less than or greater than the carrier frequency and is a function of the carrier set and the modulation waveform. By adjusting the displacement phase angle in multilevel PWM switching strategies, switching losses can be minimized for a more efficient multilevel inverter. A cascade multilevel inverter topology has been proposed that requires only a single DC power source. Subject to specified constraints, it was shown that the voltage level of the capacitors can be controlled while at the same time choosing the switching angles to achieve a specified modulation index and eliminate harmonics in the output waveform. There are many multilevel inverters developed according to the voltage levels required. This project deals with the design and implementation of single-phase five-level PWM inverter. The sinusoidal PWM technique is involved in the design which has several advantages over other modulation techniques. The operational and the switching functions are analyzed in detail. In addition it is compared with the conventional three-level PWM inverter, smaller filter size, improved output waveform and other advantages. Multilevel inverters have become an effective and practical solution for increasing power and reducing harmonics of ac waveforms. The main advantages of multilevel PWM inverters are 1) The series connection allows higher voltage without increasing voltage stress on switches.2) Multilevel waveforms reduce the dv/dt at the output of an inverter.3) At the same switching frequency, a multilevel inverter can achieve lower harmonic

distortion due to more levels the output waveform in comparison to a single cell inverter. 4) Lower switching losses. 5) Higher voltage capability. 6) Higher power quality. 7) They are useful to drive applications. 8) The efficiency is very high (>98%) because of the minimum switching frequency .9). They can improve the power quality and dynamic stability for utility systems 10). They are suitable for medium to high power applications. Thus the multi-level inverters are used in various fields.

6. FUTURE SCOPE

In this project, do matlab simulation for 5 to 15 (odd levels) level inverter by using SPWM technique, in further implementations are by using SVPWM with fuzzy or neural techniques. We are obtaining good response by using these techniques. Now the most research in electrical vehicles is to develop better controls with multilevel inverters. Another future for multilevel inverters is using DSP controllers an intelligent control approach is possible to reduce the overall system cost and to improve the reliability of the system performance. In future new multilevel technologies are coming. By using this technologies we are reduce to drive costs (mainly in electric vehicles). So in future, maybe it is better research field in power Electronics/Drive applications.

7. REFERENCES

[1] Jose Rodriguez, Jih-Sheng Lai, and Fang Zheng Peng, Multilevel Inverters: A Survey of Topologies, Controls, and Applications, IEEE Transactions on Industrial Electronics, Vol. 49, No. 4, August 2002. pages 724-738. [2] Leon M. Tolbert and Thomas G. Habetler, Novel Multilevel Inverter Carrier-Based PWM Method, IEEE Transactions on industry applications, Vol. 35, No.5, sep/oct 1999. pages 1098 1107. [3] Zhong Du, Leon M. Tolbert, John N. Chiasson, and Burak Ozpineci, A Cascade Multilevel Inverter Using a Single DC Source, 0-7803-9547-6/06/$20.00 2006 IEEE pages 426-430. [4] Remus Teodorescu, Frede Blaabjerg, John. K. Pedersen, Ekrem Cengelci, and Prasad N. Enjeti, Multilevel Inverter by Cascading Industrial VSI, IEEE Transaction on industrial electronics, Vol.49, No.4, August 2002. pages 832-838. [5] Xiaoming Yuan, Lvo Barbi, A New Diode Clamping Multilevel Inverter, 0-7803-5160-6/99/$10.00 1999 IEEE. pages 495-501. [6] Madhav D. Manjrekar, Peter K. Steimer, and Thomas A. Lipo, Hybrid Multilevel Power Conversion System: A Competitive Solution for High-Power Applications IEEE Transaction on Industry Applications, Vol. 36, No. 3, May/June 2000. pages 834-841. [7] Miguel Lopez G, Luis Moran T, Jose Espinoza C and Juan Dixon R, Performance Analysis of a Hybrid Asymmetric Multilevel Inverter for High Voltage Active Power Filter Applications, 0-7803-79063/03/$17.00 2003 IEEE, pages 1050-1055 [8] Jamal Al-Nasseir, Christian Weindl, Gerhard Herold and Joerg Flotthmesch, A Dual-use Snubber Design for Multi-Level Inverter Systems,1-4244-0121-6/06/$20.00.2006 IEEE, pages 683-688 [9] Gui-jia Su and Donald J.Adams, Multilevel DC Link Inverter for Brushless Permanent magnet Motors with Very Low Inductance, IEEE IAS annual Meeting, September 30 October 5, 2001. [10] Ying Cheng Mariesa L. Crow, A Diode Clamped Multi-level Inverter For the StatCom/BESS, 07803-7322-7/02/$17.00 2002 IEEE pages 470-475

[11] L. Li D. Czarkowski, Y.Liu P. Pillay, Multilevel Selective Harmonic Elimination PWM in SeriesConnected Voltage Inverters, 0-7803-4943-1/98/$10.00 (c) 1998 IEEE. [12] Leon M. Tolbert and Thomas G. Habetler, Novel Multilevel Inverter Carrier-Based PWM Methods, IEEE IAS 1998 Annual Meeting, St. Louis, Missouri, October 10-15, 1998, pp. 1424-1431. [13] J. Song-Manguelle and Prof. A. Rufer, Multilevel Inverter for Power System Applications: Highlighting Asymmetric Design Effects From a Supply Network Point of View, 0-7803-77818/03/$17.00 2003 IEEE. [14] S.Mariethoz, A. Rufer, Resolution and efficiency improvements for three-phase cascade multilevel inverters, 35th Annual IEEE Power Electronics Specialists Conference 2004. pages 4441-4446. [15] Nam S. Choi, Jung G. Cho and Gyu H. Cho, A General Circuit Topology Of Multilevel Inverter, 07803-0090-4/91/0700-0096$01.00 1991 IEEE. pages 97-103.

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