System-on-Chip Design Flow

Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems jouni.tomberg@tut.fi

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Jouni Tomberg / TUT

SoC - How and with whom?

SoC Players Markets Flows Bottlenecks IP and platform metrics

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Jouni Tomberg / TUT

Definitions
Frontend design Backend design ASIC flow
Design from system level to cell library level netlist Design from netlist level to Placed & Routed production ready database Netlist handoff to ASIC vendor (takes care of the backend) P&R database handoff to foundry (takes care of the production)
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COT (Customer Owned Tooling) flow

SoC Players
IP provider
Standard function blocks

Customer (end user)

IC's

Requirement specification Production requirements Netlist or P&R database

Design Service provider

Physical backannotation

ASIC vendor or Foundry

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Need for System Level Design

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Market Segments

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Design Productivity Gap

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Typical Design Flow Tasks

Transistor/ Physical
Create physical representation Place & Route Clock-tree synthesis Power Routing Transistor Optimization Verify physical design DRC, LVS Power analysis Rail analysis Static Timing analysis Parasitic Extraction Physical/transistor models Std Cell libraries Gate Array libraries

Behavioral

Implement

Define System Create/select Algorithms Filter design Protocol Development

Create behavioral description Code generation Wordlength optimizatiuon Architectural Tradeoffs Partitioning

Create RTL description Behavioral Synthesis Code generation Design Planning

Create Netlist Optimize Netlist Logic Synthesis Datapath Synthesis Test Synthesis Power Optimization Retiming Verify Netlist (function and performance) Simulation Equivalence Checking Static Timing Analysis Power Analysis Test Analysis/ATPG

Verify

Verify system function Verify Algorithm performance System Simulation HW/SW Coverification

Verify behavioral description (function and performance) Simulation Testbench Generation HW/SW Coverifiication

Verify RTL description (function and performance) Simulation Power Analysis RTL quality analysis Emulation

Models/IP
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System model components System environments Reference Kits

Behavioral models RAM Models Part models Bus Models Cores

RTL models RAM models Part models Bus Models Cores (functional & timing Models)

Gate models Bus Models Synthesis/simulation libraries

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Gate-level

System/ Algorithm

RTL

Design Flows

Source: T. Moxon / EEDesign, 2.1.2002

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ASIC design flow interfaces

DESIGN TEAM Requirement spec Technical info for quotation ASIC quotation Data sheet for acceptance Library & tools Verification for acceptance (modeler/testbench/simul.results) CUSTOMER ASIC VENDOR

Netlist, test vectors, arch.plan Backannotation from P&R Acceptance for prototype production (sign off) Prototype ASICs (/risk production) Prototype acceptance Mass production ASICs 26.03.2003 Jouni Tomberg / TUT 10

Importance of Specification

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Design Bottlenecks
Simulation/Design Verification Design Creation Place & Route Post Layout Optimization Parasitic Extraction System or System-on-Chip Layout Versus Schematic(LVS) Design Rule Check (DRC) Static Timing Analysis Synthesis Delay Calculation
0% 10%

* Source EETIMES EDA 2000 Survey

51% 32% 32% 26% 17% 17% 17%

16% 15% 13%

20% 30% 40%

Base = 545
50% 60%

50 -70 % of project effort devoted to design verification!

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Verification Importance

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Project Scheduling
External constraints

Targeted market entry ASIC vendor
Layout generation (P&R) Mask producing Prototype processing Prototype acceptance Volume production starting delay

Design constraints

Design team experience Design tools / flows, vendor libraries, IP provider quality System specification iterations Design complexity Verification complexity Production test complexity
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 SoPC is a FPGA technology based user programmable

solution
P&R and programming done by the user (vs. backend flow in SoC) No delay on prototype production No delay on mass production start No NRE (production start) costs Production tests done by the IC vendor Design resource and time savings in the design flow Quick and cheap modifications

Differencies between SoC and SoPC design flows

On the other hand certain limitations on performance,

integration capacity and mass production costs exists compared to SoC
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Platform Based Design

A platform should consist of a basic set of
integrated technologies that defines how the system should function. Design platform / Verification platform Generic platform

Application specific platform

CPU, memory and standard peripheral fucntions Generic platform plus pre-integrated IP blocks for the given application

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Platform drivers

Source: B. Altizer, L. Cooke, and G. Martin / EEDesign 7.11.2002

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Platform Advantages
Reduce integration risk by insuring that all IP works
together Reduce licensing and contractual negotiation time per project Reduce cost by allowing efficient reuse in multiple designs It is estimated that in the near future each SoC design will consist of 10 to 15 different IP blocks from 6 to 8 IP vendors
Suppose 6 to 8 weeks per IP vendor for evaluation, negotiation and integration of IP into the system => with 8 different IP vendors this means 64 weeks of hidden cost
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IP Market Dynamics
Design dynamics (Dataquest 2002) Contractual and legal issues Evaluation of IP
30% of a designs are composed of reused circuitry 12% of reused circuit is from outside sources => 3.6% of circuitry is from third parties Legal issues remain a huge bottleneck in the IP purchase process VCX trying to address this bottleneck (with standard Ts &Cs) Deciding if a core is viable is biggest technical challenge in IP acquisition process. Opportunities in IP evaluation services Most IP vendors are small and vulnerable Partnerships and alliance can help to resolve perceived volatility Proliferation of processors in ICs Resulting in more functions being implemented in software SW/HW co-design!
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rights, responsibility, guarantee, business model

Perceived instability of vendors.. Software replacing hardware

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IP Market Metrics
46%CAGR

75% License Revenue

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25% Royalty Revenue

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Conclusions
The main players in the SoC design flow are Design
team, IP provider, IC vendor (or Backend team + Foundry) Efficient SoC design flow is based on IP reuse and platform based design The major bottlenecks are in the test and verification area The system level (specification, HW/SW co-design) and layout level links to RTL design play also an important role in a fluent design flow
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