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PLAINTIFFS EXHIBIT 1

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,034,918 METHOD OF OPERATING A MEMORY HAVING A VARIABLE DATA OUTPUT LENGTH AND PROGRAMMABLE REGISTER 1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request; and issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal.

8. The method of claim 1 further including providing a code which is representative of a delay time to transpire before data is output onto the bus after receipt of a read request, wherein the memory device stores the code in an access time register on the memory device.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,038,195 SYNCHRONOUS MEMORY DEVICE HAVING A DELAY TIME REGISTER AND METHOD OF OPERATING SAME

23. A method of controlling a synchronous memory device having at least one memory section including a plurality of memory cells and a register for storing a value which is representative of a time delay after which the memory device responds to a read request, the method comprising: issuing a read request to the memory device; and receiving data from the memory device, in response to the read request, wherein the memory device outputs the data after the time delay transpires and synchronously with respect to an external clock signal. 24. The method of claim 23 further including issuing a control register access, wherein, in response to the control registers access, the memory device stores the value in the register. 32. The method of claim 23 wherein the value stored in the register is one of a plurality of available delay times.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,260,097 METHOD AND APPARATUS FOR CONTROLLING A SYNCHRONOUS MEMORY DEVICE 1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data; providing a first portion of data to the memory device synchronously with respect to a rising edge transition of an external clock signal; and providing a second portion of data to the memory device synchronously with respect to a falling edge transition of the external clock signal.

5. The method of claim 1 further including: providing block size information to the memory device, wherein the block size information defines a first amount of data to be output by the memory device in response to a read request; issuing a read request to the memory device; and receiving the first amount of data from the memory device. 6. The method of claim 5 further including providing access time information to the memory device, wherein the access time information is representative of a number of clock cycles of the external clock signal to delay before the memory device outputs the first amount of data.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,304,937 METHOD OF OPERATION OF A MEMORY CONTROLLER 1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: issuing a first operation code to the memory device, wherein in response to the first operation code, the memory device outputs first and second portions of data; sampling the first portion of data synchronously with respect to a rising edge transition of an external clock signal; and sampling the second portion of data synchronously with respect to a falling edge transition of the external clock signal. 4. The method of claim 1 further including: providing access time information to the memory device; and issuing a second operation code, wherein in response to the second operation code, the memory device stores the access time information in a register within the memory device. 5. The method of claim 4 wherein the access time information is representative of a number of clock cycles of the external clock signal to transpire before the first portion of data is output by the memory device in response to the first operation code. 18. A controller device for controlling a synchronous memory device, the controller device comprising: output driver circuitry to provide an operation code to the memory device, wherein in response to the operation code, the memory device outputs a first portion of data synchronously with respect to a rising edge transition of an external clock signal and a second portion of data synchronously with respect to a falling edge transition of the external clock signal; and input receiver circuitry to sample the first portion of data and the second portion of data output by the memory device. 23. The controller device of claim 18 wherein the input receiver circuitry samples an amount of data output by the memory device in response to the operation code wherein the amount of data is sampled during a plurality of clock cycles of the external clock signal.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

24. The controller device of claim 23 wherein the output driver circuitry provides block size information to the memory device, wherein the block size information is representative of the amount of data output by the memory device in response to the operation code, and wherein, in response to the operation code, the memory device outputs the amount of data during a plurality of clock cycles of the external clock signal. 29. The controller device of claim 18 wherein the output driver circuitry provides the operation code synchronously with respect to the external clock signal.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,426,916 MEMORY DEVICE HAVING A VARIABLE DATA OUTPUT LENGTH AND A PROGRAMMABLE REGISTER

15. A method of controlling a synchronous memory device by a controller, wherein the memory device includes an array of memory cells, the method of controlling the memory device comprises: providing a value to the memory device, wherein the value is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a first operation code; providing block size information to the memory device, wherein the block size information is representative of an amount of data to be output by the memory device in response to the first operation code; and providing the first operation code to the memory device, wherein the first operation code instructs the memory device to perform a read operation, wherein, in response to the first operation code, the memory device outputs the amount of data after the number of cycles of the external clock signal transpire. 19. The method of claim 15 further including providing a third operation code to the memory device, wherein the third operation code instructs the memory device to store the value in a programmable register. 20. The method of claim 15 further including receiving the amount of data output by the memory device in response to the first operation code. 23. The method of claim 15 wherein the first operation code and the block size information are provided to the memory device via an external bus. 25. The method of claim 15 wherein the block size information is a binary code.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,564,281 SYNCHRONOUS MEMORY DEVICE HAVING AUTOMATIC PRECHARGE 36. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of sense amplifiers coupled to an array of memory cells, wherein the method of controlling the memory device comprises: issuing a first operation code to the memory device, wherein the first operation code indicates that the memory device: output data read from the array of memory cells; and precharge sense amplifiers used in reading the data from the array of memory cells, wherein the sense amplifiers are precharged automatically after the data is read from the array of memory cells; and receiving the data from the memory device, the memory device outputting the data read from the array of memory cells in response to the first operation code. 38. The method of claim 36 wherein the first operation code further includes a first bit wherein: a first state of the first bit indicates that the memory device precharge the sense amplifiers used in reading the data from the array of memory cells; and a second state of the first bit specifies that the memory device retain the data in the sense amplifiers used in reading the data from the array of memory cells. 39. The method of claim 38 wherein the first operation code includes a second bit wherein: a first state of the second bit indicates that the memory device is to output the data read from the array of memory cells; and a second state of the second bit indicates that the memory device is to input data, wherein the input data is to be written to the array of memory cells. 40. The method of claim 36 further including issuing a second operation code to the memory device, wherein the second operation code instructs the memory device to: input data to be written to the array of memory cells; write the input data to the array of memory cells using sense amplifiers of the plurality of sense amplifiers; and precharge the sense amplifiers used in writing the input data to the array of memory cells, wherein the plurality of sense amplifiers are precharged automatically after the input data is written to the array of memory cells.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

42. The method of claim 36 further including providing block size information to the memory device wherein the block size information defines an amount of data read from the array of memory cells to be output from the memory device in response to the first operation code. 43. The method of claim 36 further including: providing a value to the memory device, wherein the value is representative of a number of clock cycles of an external clock signal to transpire before the memory device outputs the data in response to the first operation code; and issuing a second operation code to the memory device, wherein the second operation code initiates storage of the value, in a register internal to the memory device. 45. The method of claim 36 further including issuing address information to the memory device, wherein the address information is issued synchronously with respect to the external clock signal. 46. The method of claim 45 wherein the address information and the first operation code are issued to the memory device via an external bus.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,584,037 MEMORY DEVICE WHICH SAMPLES DATA AFTER AN AMOUNT OF TIME TRANSPIRES 25. A method of controlling a synchronous memory device by an integrated circuit device coupled to the memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: outputting a first operation code to the memory device synchronously with respect to a clock signal, wherein the first operation code specifies a write operation, wherein, in response to the first operation code, the memory device samples data; and outputting the data to the memory device after a delay time transpires. 27. The method of claim 25 wherein the first operation code includes precharge information that specifies that the memory device precharge a plurality of sense amplifiers after the write operation, wherein the plurality of sense amplifiers is used in writing the data to the plurality of memory cells during the write operation. 28. The method of claim 25 further including: outputting a value to the memory device, wherein the value is representative of the delay time; and outputting a second operation code to the memory device, wherein the second operation code instructs the memory device to internally store the value. 33. The method of claim 25 wherein outputting the data to the memory device includes: outputting a first portion of the data synchronously with respect to a rising edge transition of the clock signal; and outputting a second portion of the data synchronously with respect to a falling edge transition of the clock signal.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,715,020 SYNCHRONOUS INTEGRATED CIRCUIT DEVICE 1. A controller device for controlling a synchronous dynamic random access memory device, the controller device comprises: first output driver circuitry to output block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device; and input receiver circuitry to receive the amount of data output by the memory device. 2. The controller device of claim 1 further including second output driver circuitry to output an operation code to the memory device, wherein the operation code specifies a read operation, and wherein, in response to the operation code, the memory device outputs the amount of data. 13. The controller device of claim 1 wherein the block size information is a binary code. 14. The controller device of claim 1 wherein the input receiver circuitry samples: a first portion of the amount of data during a first half of a clock cycle of an external clock signal; and a second portion of the amount of data during a second half of the clock cycle of the external clock signal. 38. An integrated circuit controller device for controlling a synchronous dynamic random access memory device, the controller device comprises: a first plurality of output drivers to output block size information to the memory device, wherein the block size information represents an amount of data to be output by the memory device; a second plurality of output drivers to output an operation code to the memory device, wherein the operation code specifies a read operation, and wherein the memory device outputs the amount of data to the controller device in response to the operation code; and a plurality of input receivers to receive the amount of data output by the memory device. 49. The controller device of claim 38 wherein, during a clock cycle of an external clock signal, the plurality of input receivers samples two bits of data of the amount of data output by the memory device via an external signal line.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 6,751,696 MEMORY DEVICE HAVING A PROGRAMMABLE REGISTER

None.

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

PATENT NO. 7,209,997 CONTROLLER DEVICE AND METHOD FOR OPERATING SAME 1. A method of operating a controller device, comprising: outputting a value to a memory device; outputting a first operation code to the memory device, wherein the first operation code instructs the memory device to store the value in a register of the memory device; outputting a block size value to the memory device, wherein the block size value indicates an amount of read data to be output by the memory device in response to a second operation code; outputting the second operation code to the memory device, wherein the second operation code instructs the memory device to perform a read operation, wherein the second operation code includes precharge information that indicates whether the memory device should precharge sense amplifiers on the memory device after sensing data corresponding to the read operation; and after a read delay following the outputting of the second operation code, sampling a first portion of the read data output by the memory device in response to the second operation code, wherein the read delay is selected to correspond to the value output to the memory device for storage in the register. 2. The method of claim 1, wherein outputting the first and second operation codes further comprises outputting the first and second operation codes synchronously with respect to a clock signal. 3. The method of claim 1, wherein outputting the first operation code further comprises outputting the first operation code using pads on the controller device, the pads to connect to a set of external signal lines, and wherein outputting the second operation code further comprises outputting the second operation code using the pads on the controller device used to output the first operation code. 19. A controller device, comprising: output driver circuitry, the output driver circuitry to: output a value to a memory device; output a first operation code to the memory device, wherein the first operation code instructs the memory device to store the value in a register in the memory device;

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Plaintiffs Exhibit 1: Rambuss Proposed Set of 35 Claims

output a block size value to the memory device, wherein the block size value indicates an amount of read data to be output by the memory device in response to a second operation code; and output the second operation code to the memory device, wherein the second operation code instructs the memory device to perform a read operation, wherein the second operation code includes precharge information that indicates to the memory device whether the memory device should precharge sense amplifiers on the memory device after sensing data corresponding to the read operation; and input receiver circuitry to sample a first portion of the read data output by the memory device in response to the second operation code, the input receiver circuitry to sample the first portion of the read data after a read delay following the outputting of the second operation code, wherein the read delay is selected to correspond to the value output to the memory device for storage in the register. 31. The controller device of claim 19, wherein the output driver circuitry includes: a first set of output drivers to output the first operation code; and a second set of output drivers to output the block size value.

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