Problem-1 Study the variation in threshold voltage of both NMOS and PMOS with respect to change in bulk potential.

Solution: Variation of Threshold voltage(Vtn) of NMOS with the variation in the bulk voltage(Vsb). The substrate voltage is generally connected to the most negative power supply in an NMOS circuit.The resulting reverse bias voltage between source and body will have an effect on device operation.The reverse bias voltage between source and body will widen the depletion region which in turn reduces the channel depth.To return the channel to its former state Vgs has to be increased .Vtn of a mosfet changes with the change in its source to body voltage.

CIRCUIT SCHEMATIC

Plot of Id vs Vgs for different value of Vsb_(NMOS)

From the plot we can see that with the increase in Vsb(from -0.3v to 0.5 v) the value of Vtn increases.Thus Id is indirectly controlled by another gate voltage(Vsb).Vds is kept fixed at 1.0v and Vgs is varied . For PMOS

Circuit Schematic.

Plot of Id vs Vsg for constant Vsd(to check the variation of Vtp with Vbs)

Problem-2 Study the MOSFET (NMOS and PMOS) as a resistor and the variation of the resistance with respect to 1. Terminal voltages 2. Aspect ratio W.

Solution (1):In the following study we have biased the NMOS to operate in the triode region.To operate in the triode region(linear region in which it behaves as a resistor),the value of Vgs should be greater than the threshold voltage Vtn and the value of Vds should be less than Vgs by atleast Vtn.

Circuit Schematic

Plot of Vds vs Id for different Vgs (NMOS)

For each value of Vgs(0.8,0.9 and 1.0) the resistance of each of the following curve has been calculated. Slope of the most linear region has been marked and the inverse of the slope gives the resistance. With the increase in Vgs the resistance value decreases. Below the comparison table is given.

Vgs(in volt)

Vd (in mV) 100 100 100

0.8 0.9 1.0 Solution (2):

Id (in micro amp) 86.2 109.3 131.03

Id/Vd

Resistance

862.30x(10^-6) 1.09x(10^-3) 1.31x(10^-3)

1.51 kilo ohm 917 ohm 763 ohm

The value of resistance of the mosfet is affected by the change in the aspect ratio.The drain current Id depends on the aspect ratio(W/L) of the mosfet.With the increase in the W/L ratio the Id of the NMOS increases which results in a decrease of the resistance of the mosfet in the triode region.Below the table is given. W(micro meter) 15 10 6 3 L(micro meter) 1.25 1 0.75 0.5 W/L 12 10 8 6 Resistance 518 ohm 628 ohm 800 ohm 1.1 kilo ohm

For the 90nm MOS library model the value of W and L can vary from W(5um to 0.1um) and L(0.1um to 100um). With the increase of W/L ratio the drain current Id decreases for an NMOS and viceversa.

Solution(2): For PMOS (1)Variation of resistance with terminal voltages in the triode region

Circuit Schematic

Plot of Vsd vs Id with different Vsg

Vsg 0.4 0.6 0.8 1.0 1.2

Vsd(mV) Id(um) Id/Vsd(x10^-6) Resistance(K) 200 1.17 5.86 170.6 200 19.30 96.48 10.3 200 46.66 233.3 4.2 200 69.83 349.17 2.8 200 88.55 442.74 2.25 Value of resistance for different value of Vsg

Variation of resistance with the change in aspect ratio.

Circuit schematic.
Cell0
iD (M PM O S_1)

-0

-50

Current (uA)

-100

-150

50

100

150

200

250

300

350

400

450

500

550

600

vsdparam (m)

Plot of Id vs Vsd for different W/L ratio.

With the increase in W/L ratio the value of Id increases and value of Vgs decreases.