Digital Systems

Topic 14: Vending Machine Design Problem

Objectives
To design a Vending Machine Controller
Design the state diagram Design the state table Write the VHDL code
Simulate/test each module

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Design Description/Specifications
Vending Machine Controller
1. 2. The machine takes quarters only (Qi) The machine can dispense: 1. Water: 75 cents (W) 2. Cola: 50 cents (C) 3. Beer: 50 cents (B) The machine has a Coin Return button (Cr) Only one input may be active at a time A product can be dispensed in one clock cycle If more than 75 cents is inserted, the money is automatically returned If no inputs are active, the state machine stays in the current state Outputs: 1. CRo: Coin Return Out (all money in the machine) 2. Wo: Water Out 3. Co : Cola Out 4. Bo : Beer Out 5. Qo : Quarter Out

3. 4. 5. 6. 7. 8.

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FSM Design Steps

1. 2. Obtain the specifications of the desired circuit Derive the states of the machine and develop a state diagram
1. 2. Should show all possible states Provide the conditions for which the circuit moves from one state to the next

3. 4. 5.

Develop the state table from the state diagram Decide on the number of state variables needed to represent all states
1. Minimize the number of states if possible

Choose the type of flip-flops that will be used in the implementation

1. 2. Derive the next-state logic expressions to develop the Input Logic Circuit Derive the logic expressions for the Output Logic Circuit

6.

Implement the design

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State Diagram
Reset

1. 2.

A
Qi

C
CRo

B
Qi

Cr Cr

3. 4. 5. 6. 7.
Cr

D E
Co

8.

Qi C B B

K
Qo

G
W Qi

F
Bo

The machine takes quarters only (Qi) The machine can dispense: 1. Water: 75 cents (W) 2. Cola: 50 cents (C) 3. Beer: 50 cents (B) The machine has a Coin Return button (Cr) Only one input may be active at a time A product can be dispensed in one clock cycle If more than 75 cents is inserted, the money is automatically returned If no inputs are active, the state machine stays in the current state Outputs: All produce a pulse that activates the release mechanism: 1. CRo: Coin Return Out (all money in the machine) 2. Wo: Water Out 3. Co : Cola Out 4. Bo : Beer Out 5. Qo : Quarter Out

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

A
Qi

Will this work? If nothing has happened, or if the machine has been reset, the machine is in state A

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi C

K
Qo

G
W Qi

F
Bo

B B

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

If we input a quarter, the machine goes to state B (25 cents)

A
Qi

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi C

K
Qo

G
W Qi

F
Bo

B B

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

If we input a quarter, the machine goes to state B (25 cents) We can now: Do nothing (stay in State B) Hit the Coin Return (Go to state C and return the money) Insert a quarter (Go to state D and wait)

A
Qi

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi C

K
Qo

G
W Qi

F
Bo

B B

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

If the machine is in state D (50 cents) We can: Do nothing (stay in State D) Hit the Coin Return (Go to state C and return the money) Select a cola (go to state E, output a cola, then go to A) Select a beer (go to state F, output a beer, then go to A) Insert a quarter (75 cents - Go to state G and wait)

A
Qi

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi C

K
Qo

G
W Qi

F
Bo

B B

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

If the machine is in state G (75 cents) We can: Do nothing (stay in State G) Hit the Coin Return (Go to state C and return the money) Select a cola (go to state K, return a quarter, and then go to state E, output a cola, then go to A) Select a beer (go to state J, return a quarter, and then go to state F, output a beer, then go to A) Insert a quarter (return the quarter too much money - Go back to state G and wait) Select a water (go to state H, output a water, then go to state A)

A
Qi

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi C

K
Qo

G
W Qi

F
Bo

B B

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

It will work, but we have 3 different states (I, J, and K) that output a quarter. For a Moore machine, this is necessary, because each state then goes to a different state I ->G J->F K->E

A
Qi

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi C

K
Qo

G
W Qi

F
Bo

B B

H
Wo

I
Qo

J
Qo

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State Diagram
Reset

It will work, but we have 3 different states (I, J, and K) that output a quarter. For a Moore machine, this is necessary, because each state then goes to a different state But, if the input (B, C or Qi) is associated with state G as well as the output (Qo), as in Mealy Machines, then we do not need the three states (I, J, and K)
Cr

A
Qi

C
CRo

B
Qi

Cr

This is a simpler design!

Cr

D E
Co

C C/Qo B B/Qo

Qi

G
W Qi/Qo

F
Bo

H
Wo

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FSM Design Steps

1. 2. Obtain the specifications of the desired circuit Derive the states of the machine and develop a state diagram
1. 2. Should show all possible states Provide the conditions for which the circuit moves from one state to the next

3. 4. 5.

Develop the state table from the state diagram Decide on the number of state variables needed to represent all states
1. Minimize the number of states if possible

Choose the type of flip-flops that will be used in the implementation

1. 2. Derive the next-state logic expressions to develop the Input Logic Circuit Derive the logic expressions for the Output Logic Circuit

6.

Implement the design

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State Table
Reset

A
Qi

We have: 8 states (3 state bits) 5 inputs (Cr, Qi, C, B, or W) 5 outputs (CRo, Qo, Wo, Bo, and Co)

C
CRo

B
Qi

Cr Cr

D E
Co

Cr Qi

C C/Qo B B/Qo

G
W Qi/Qo

F
Bo

H
Wo

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FSM Design Steps

1. 2. Obtain the specifications of the desired circuit Derive the states of the machine and develop a state diagram
1. 2. Should show all possible states Provide the conditions for which the circuit moves from one state to the next

3. 4. 5.

Develop the state table from the state diagram Decide on the number of state variables needed to represent all states
1. Minimize the number of states if possible

Choose the type of flip-flops that will be used in the implementation

1. 2. Derive the next-state logic expressions to develop the Input Logic Circuit Derive the logic expressions for the Output Logic Circuit

6.

Implement the design

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VHDL Code: Entity

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Vend is Port ( Clock : in std_logic; Reset : in std_logic; Cr, Qi, Ci, Bi, Wi : in std_logic; CRo, Qo, Co, Bo, Wo : out std_logic; Q: out Std_Logic_Vector (2 DOWNTO 0)); end Vend;

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VHDL Code: Architecture

architecture Behavioral of Vend is TYPE State_type IS (A, B, C, D, E, F, G, H) ; SIGNAL y : State_type ; begin Process Begin If Reset = '0' then y <= A; CRo <= '0'; Qo <= '0'; Co <= '0'; Bo <= '0'; Wo <= '0'; Q <= "000"; end if; Wait Until falling_edge (Clock); CASE y IS WHEN A => Q <= "000"; If Qi = '1' then y <= B; end if; WHEN B => Q <= "001"; If Cr = '1' then y <= C; elsif Qi = '1' then y <= D; end if; WHEN C => Q <= "010"; CRo <= '1' after 0 ns, '0' after 200 ns; y <= A; WHEN D => Q <= "011"; If Cr = '1' then y <= C; elsif Qi = '1' then y <= G; elsif Ci = '1' then y <= E; elsif Bi = '1' then y <= F; end if; WHEN E => Q <= "100"; Co <= '1' after 0 ns, '0' after 200 ns; y <= A; WHEN F => Q <= "101"; Bo <= '1' after 0 ns, '0' after 200 ns; y <= A; WHEN G => Q <= "110"; If Cr = '1' then y <= C; elsif Qi = '1' then y <= G; Qo <= '1' after 0 ns, '0' after 200 ns; elsif Ci = '1' then y <= E; Qo <= '1' after 0 ns, '0' after 200 ns; elsif Bi = '1' then y <= F; Qo <= '1' after 0 ns, '0' after 200 ns; elsif Wi = '1' then y <= H; end if; WHEN H => Q <= "111"; Wo <= '1' after 0 ns, '0' after 200 ns; y <= A; END CASE ; end process; end Behavioral;

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Simulation/Test
This is the 1st Test Bench

2 quarters in, buy a beer 2 quarters in, buy a cola 3 quarters in, buy water 1 quarter in, hit Coin Return

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Simulation/Test: Results
1st set of results

2 quarters in, buy a beer, a beer is dispensed 2 quarters in, buy a cola, a cola is dispensed 3 quarters in, buy water, a water is dispensed 1 quarter in, hit Coin Return, a quarter is returned

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Simulation/Test 2
This is the 2nd Test Bench

5 quarters in, buy a beer 4 quarters in, buy a cola 0 quarters in, buy water 0 quarter in, hit Coin Return

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Simulation/Test: Results 2
2nd set of results

RED: 5 quarters in: after 3, they start being returned

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Simulation/Test: Results 2
2nd set of results

RED: 5 quarters in: after 3, they start being returned BLUE: Buy a beer: another quarter is returned and a beer is dispensed

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Simulation/Test: Results 2
2nd set of results

RED: 4 more quarters in: after 3, they start being returned

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Simulation/Test: Results 2
2nd set of results

RED: 4 more quarters in: after 3, they start being returned YELLOW: Buy a cola, a quarter is returned and a cola is dispensed

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Simulation/Test: Results 2
2nd set of results

Magenta: No quarters in: Buy water, nothing happens Green: Hit Coin Return, nothing happens

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Summary
In this topic we:
Designed a state machine that controls a vending machine
Designed the state diagram Designed the state table Wrote the VHDL code
Looked at two new keywords falling_edge after Xns Simulated and tested each module

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