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Logic-Level Gate Drive l Advanced Process Technology l Surface Mount (IRL1104S) l Low-profile through-hole (IRL1104L) l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description
l
IRL1104SPbF IRL1104LPbF
HEXFET Power MOSFET
D
ID = 104A
S
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL1104L) is available for lowprofile applications.
D 2 Pak
TO-262
Max. 104 74
416 2.4 167 1.1 16 340 62 17 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient(PCB Mounted,steady-state)**
Typ.
Max.
0.9 40
Units
C/W
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1
07/19/04
IRL1104S/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V(BR)DSS RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 40 1.0 53 Max. Units Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID =1mA 0.008 VGS = 10V, ID = 62A W 0.012 VGS = 4.5V, ID = 52A V VDS = VGS, ID = 250A S VDS = 25V, ID = 62A 25 VDS =40V, VGS = 0V A 250 VDS = 32V, VGS = 0V, TJ = 150C 100 VGS = 16V nA -100 VGS = -16V 68 ID =62A 24 nC VDS = 32V 34 VGS = 4.5V, See Fig. 6 and 13 VDD = 20V ID =54A RG = 3.6 , V GS = 4.5V RD = 0.4, See Fig. 10 Between lead, 7.5 nH and center of die contact 3445 VGS = 0V 1065 pF VDS = 25V 270 = 1.0MHz, See Fig. 5 Typ. 0.04 18 257 32 64
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Conditions D MOSFET symbol 104 showing the A G integral reverse 416 p-n junction diode. S 1.3 V TJ = 25C, IS =62A, VGS = 0V 84 126 ns TJ = 25C, IF =62A 223 335 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Pulse width 300s; duty cycle 2%. Uses IRL1104 data and test conditions. Calculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the package refer to Design Tip # 93-4 TJ 175C ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
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IRL1104S/LPbF
1000
VGS 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V TOP
1000
VGS 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V TOP
100
100
10
10
2.7V
2.7V
20s PULSE WIDTH TJ = 25 C
1 10 100
1 0.1
1 0.1
1000
2.5
TJ = 25 C TJ = 175 C
100
ID = 104A
2.0
1.5
1.0
10
0.5
1 2.0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( C)
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IRL1104S/LPbF
6000
5000
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
10
C, Capacitance (pF)
4000
Ciss
3000
2000
Coss
1000
Crss
0 1 10 100
1000
10000
100
TJ = 175 C
10
100us 1ms
TJ = 25 C
1
10
10ms
0.1 0.2
VGS = 0 V
0.8 1.4 2.0 2.6
1 1
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IRL1104S/LPbF
120
LIMITED BY PACKAGE
100
V DS V GS RG
RD
D.U.T.
+
80
V DD -
60
4.5V
Pulse Width 1 s Duty Factor 0.1 %
40
VDS 90%
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
D = 0.50
0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.1
0.01 0.00001
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IRL1104S/LPbF
800
15V
TOP BOTTOM
600
VDS
DRIVER
RG
D.U.T
IAS
+ V - DD
400
5 10V
tp
0.01
200
V(BR)DSS tp
50K
QG
12V
.2F .3F
4.5 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
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IRL1104S/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer
RG dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ V DD
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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OR
INT E R NAT IONAL R E CT IF IE R L OGO PAR T NU MB E R F 530S DAT E CODE P = DE S IGNAT E S L E AD-F R E E PRODU CT (OPT IONAL) YE AR 0 = 2000 WE E K 02 A = AS S E MB LY S IT E CODE AS S E MB L Y LOT CODE
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OR
INT E RNAT IONAL RE CT IF IE R L OGO AS S E MB L Y L OT CODE PART NUMB E R DAT E CODE P = DE S IGNAT E S L EAD-F REE PRODUCT (OPT IONAL ) YE AR 7 = 1997 WE E K 19 A = AS S E MB L Y S IT E CODE
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TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
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