Vous êtes sur la page 1sur 162

DH2T 34 Computer Architecture 1

June 2005 SQA

Computer Architecture 1

DH2T 34

Acknowledgements
No extract from any source held under copyright by any individual or organisation has been included in this publication.

Scottish Qualifications Authority Material developed by West Lothian College and GCNS. This publication is licensed by SQA to COLEG for use in Scotlands colleges as commissioned materials under the terms and conditions of COLEGs Intellectual Property Rights document, September 2004. No part of this publication may be reproduced without the prior written consent of COLEG and SQA.

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

Contents
Acknowledgements Contents Introduction to the unit What this unit is about Outcomes Unit structure How to use these learning materials Symbols used in this unit Other resources required Assessment information How you will be assessed When and where you will be assessed What you have to achieve Opportunities for reassessment Section 1: Data representation working in number bases Introduction to this section Assessment information for this section Introduction The binary number system Number systems Base conventions Converting between base 10, base 2 and base 16 number systems Summary of this section Answers to SAQs 2 3 7 7 7 7 7 8 9 10 10 10 10 10 11 13 14 15 15 16 25 27 40 41

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to activity Section 2: Data representation internal representation of values Introduction to this section Assessment information for this section ASCII characters and their representation Unicode characters and their representation Boolean or logic operators Logic operations on bytes Adding numbers in binary Summary of this section Answers to SAQs Answer to activity Section 3: Memory Introduction to this section Assessment information for this section Memory Interpret graphical information Summary of this section Answers to SAQs Answer to activity Section 4: Communication between the processor and peripherals Introduction to this section Assessment information for this section Introduction Main components of a computer system CPU in operation
SQA Version 1 4

44 45 47 48 49 51 53 64 68 82 83 88 91 93 94 95 99 104 105 106 107 109 110 111 112 115


Developed by COLEG

Computer Architecture 1

DH2T 34

Interconnection methods Input/output devices Peripheral management Speeding up the processor Summary of this section Answers to SAQs Section 5: The fetchexecute cycle Introduction to this section Assessment information for this section Programming languages Assembly language Registers Assembly language instructions Addressing modes The fetchexecute cycle Summary of this section Answers to SAQs Answers to activities

118 122 124 127 133 134 137 139 140 141 141 142 143 144 147 158 159 160

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction to the unit


What this unit is about
This unit is designed to develop broad general knowledge and understanding of the theoretical concepts, principles, boundaries and scope of the mechanisms that underpin the use of digital computers. This includes the way in which the internal representation used within the machine can be translated to give values that people can read. The unit also provides a foundation knowledge of the mechanisms used by a processor to communicate with memory and external devices, how a processor deals with requests from external sources, and the characteristics and requirements of the devices that processors can be regularly expected to deal with.

Outcomes
1 2 3 Demonstrate an ability to manipulate and translate data representations. Demonstrate an understanding of the functions of computer system components. Demonstrate an understanding of the principles of the central processor unit (CPU) operation.

Unit structure
This unit contains the following sections: Approximate. study time 8 hours 8 hours 6 hours 8 hours 6 hours

Section number and title 1 2 3 4 5 Data representation: working in number bases Data representation: internal representation of values Memory Communication between the processor and peripherals The fetchexecute cycle

How to use these learning materials


This pack is designed to provide a complete learning experience. There are theory notes, self assessed questions and tutor assignments to enable you to achieve success when you undertake your assessments for the unit. Work through the pack at a pace you are comfortable with, but please resist the temptation to race through the work. Some of the concepts are fairly tricky and need to be worked through methodically.

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

Symbols used in this unit


These learning materials allow you to work on your own with tutor support. As you work through the course, you will encounter a series of symbols which indicate that something follows that you are expected to do. You will notice that as you work through the sections you will be asked to undertake a series of self assessed questions, activities and tutor assignments. An explanation of the symbols used to identify these is given below. Self assessed question

This symbol is used to indicate a self assessed question (SAQ). Most commonly, SAQs are used to check your understanding of the material that has already been covered in the sections. This type of assessment is self contained; everything is provided within the section to enable you to check your understanding of the materials. The process is simple. You are set SAQs throughout the section. You respond to these by writing either in the space provided in the assessment itself or in your notebook. On completion of the SAQ you turn to the back of the section to compare the model SAQ answers to your own. If youre not satisfied after checking your responses, turn to the appropriate part of the section and go over the topic again.

Remember the answers to SAQs are contained within the study materials. You are not expected to guess at these answers. Activity

This symbol indicates an activity, which is normally a task you will be asked to do that should improve or consolidate your understanding of the subject in general or a particular feature of it. The suggested responses to activities follow directly after each activity. Remember that the SAQs and activities contained within your package are intended to allow you to check your understanding and monitor your own progress throughout the course. It goes without saying that the answers to these should only be checked out after the SAQ or activity has been completed. If you refer to these answers before completing the SAQs or activities, you cannot expect to get maximum benefit from your course.

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

Tutor assignment formative assessment

This symbol means that a tutor assignment is to follow. These are found at the end of each section. The aim of the tutor assignment is to cover and/or incorporate the main topics of the section and prepare you for unit (summative) outcome assessment.

Other resources required


Personal computer. Access to the internet. Computer magazines. Library resources. Scientific calculator.

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

Assessment information
How you will be assessed
Your assessment will comprise several tasks, which will be carried out under supervised conditions.

When and where you will be assessed


You should negotiate a mutually convenient assessment location, date and time with your tutor.

What you have to achieve


You must successfully complete all assessment tasks to achieve this unit.

Opportunities for reassessment


Normally, you will be given one attempt to pass an assessment with one reassessment opportunity. Your centre will also have a policy covering 'exceptional' circumstances, for example if you have been ill for an extended period of time. Each case will be considered on an individual basis and is at your centre's discretion (usually via written application), and they will decide whether or not to allow a third attempt. Please contact your tutor for details regarding how to apply.

SQA Version 1

10

Developed by COLEG

Computer Architecture 1

DH2T 34

Section 1: Data representation working in number bases

SQA Version 1

11

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

12

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction to this section


What this section is about This section will introduce you to different number systems and how data is represented in each. The decimal, binary and hexadecimal number systems will be examined and you will learn how to represent integer numbers in each of these different bases. You will then learn how to convert values between these three bases, i.e. decimal to binary, decimal to hexadecimal and binary to hexadecimal. This section does not require any prior knowledge but basic numeracy skills are essential. It is strongly recommended that you learn the procedures for converting values rather than use a scientific calculator to perform the tasks, but you may use a calculator to check your working. The only practical work in this section is in using the internet and/or computer magazines for one of the activities so you should be able to complete this section at home before sending the tutor assignment to your tutor. Outcomes, aims and objectives The intention of this section is to introduce you to the idea of number bases and their uses within a computer system. Approximate study time 8 hours. Other resources required Use of the internet. Computer magazines.

SQA Version 1

13

Developed by COLEG

Computer Architecture 1

DH2T 34

Assessment information for this section


How you will be assessed This section forms part of Outcome 1. The other part of this outcome is continued in Section 2. There is a tutor assignment at the end of this section for your guidance. The summative assessment comes after you have completed Section 2. Upon successful completion of the summative assessment you will have also completed the using number component of the numeracy core skill which has been embedded in this outcome. When and where you will be assessed The assessment at the end of Section 2 will be in the form of an in-class assessment. The assessment will be closed book and carried out under supervised conditions. This is a formal assessment and it will be held in college but if you are likely to have a problem in attending college then ask your tutor for advice. What you have to achieve The summative assessment for Outcome 1 takes the form of 20 multiple-choice questions that must be completed in an hour. Calculators are not allowed. A candidate must achieve 60% (i.e. 12 correct from the 20 questions) to successfully achieve the required standard. Opportunities for reassessment If you are unsuccessful on your first attempt you will be given an opportunity to be reassessed. The reassessment will be carried out under the same supervised, closed book arrangements as the first attempt. A different selection of questions should appear in the reassessment.

SQA Version 1

14

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction
Computers are electronic devices made up of electronic switches. These electronic switches can have only two states that are understood by the computer: on or 1 or or off 0, referred to as binary digits (bits).

Although digital computers are said to represent information using binary digits, they themselves have to be represented by a physical quantity that can be manipulated by electronic circuits. For example, a particular system may use different voltages to represent the two digits 1 and 0. Typically this may be 5 volts to represent a binary 1 and 0 volts to represent a binary 0. Voltage 5

Time 0 1 0 0 1 0 1 1

Figure 1 Using voltage levels to represent bits Zeros and ones are used to represent the transmission of data. In such a scheme, the numbers 0 and 1 are the language used by computers to communicate. It is this new language that you will learn, to allow you to communicate more accurately with the computer and also provide you with a greater understanding of the underlying operation of digital computers.

The binary number system


The binary number system has two digits, 0 and 1, a binary digit being called a bit. Information inside a computer, data, is represented by a group of bits, and as far as a computer is concerned data is either numeric information or character information. Inside a computer numbers will be held as binary numbers and characters will be held as binary-coded characters, with one character usually being represented by an 8-bit pattern called a byte (with the exception of Unicode, which is covered later in this section). Random access memory (RAM) holds all data numbers, characters, graphical images and audio files in bit patterns. This section covers how numbers are represented and Section 2 includes how a computer represents characters and other symbols.
SQA Version 1 Developed by COLEG

15

Computer Architecture 1

DH2T 34

Number systems
Decimal numbering Decimal numbering is a place system of values because the value of the digit is determined by its place. The most common number system in everyday use is the decimal (sometimes called denary) system. The decimal number system uses 10 symbols, namely: 0123456789 The number of different symbols used in any number system is known as its base or radix. So the base of the decimal number system is 10, i.e. 23410 can be read as two hundred and thirty-four to the base ten. It is only necessary to talk about the base of a number system when you are dealing with different number bases, e.g. 58616, 1628, 1002, 23410. By convention the position of each digit in a number determines its value. For example, the number 824 is pronounced as: eight hundred and twenty-four in other words, 8 100 2 10 41 We can write this in expanded notation as: (8 102) + (2 101) + (4 100) Note: any number raised to the power of 0 is always equal to 1. For example, the number 9999 is pronounced as: nine thousand nine hundred and ninety-nine iIn other words: 9 1000 9 100 9 10 91 We can write this in expanded notation as: (9 x 103) + (9 102) + (9 101) + (9 100) Note: the same digit (9) but representing different values determined by the digits position.

SQA Version 1

16

Developed by COLEG

Computer Architecture 1

DH2T 34

Indices The manner in which we count is based on the number of fingers (digits) that we have. The numbers are put together so that the position of any particular digit in a whole number represents its value multiplied by 10, 100, 1000, etc. These multiples of ten can often be written more conveniently as 10, 102, 103, etc. Ten is called the base and the small number above and to the right is called the index (plural indices). This notation logically extends to include indices of zero and of negative numbers:

100 = 1
Using negative indices allows the position of digits after the decimal point to represent fractions of whole numbers. Reminder indices 61 32 = = = 103 = = 25 = = 31 = = x1 = = 30 10 x0 = = = 61 33 9 10 10 10 1000 22222 32 31 3 x1 x 1 1 1 Remember the rule that any number raised to the power of zero is always equal to 1 The 5 means five 2s multiplied together The 3 means three 10s multiplied together The 1 means 1 multiplied by the number The 2 means two 3s multiplied together

SQA Version 1

17

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a b c d e f

1.1

Complete the following questions and check your answers with those given at the back of the section. Evaluate the following: 34 102 73 26 91 30

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Possible symbols: 0123456789 The power positions for decimal numbers (base 10) are shown in Table 1. Table 1 Base 10 Powers Equal to 107 10 000 000 106 1 000 000 105 100 000 104 10 000 103 1 000 102 100 101 10 100 1

SQA Version 1

18

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a b c d

1.2

Complete the following questions and check your answers with those given at the back of the section. Write in expanded notation: 9 821 11 342 1 102 99 874

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

19

Developed by COLEG

Computer Architecture 1

DH2T 34

Binary systems The number system used by a digital computer is called the binary number system. The binary number system uses two digits, namely: 0 1 Since the binary number system has only two different digits, the base is therefore 2. The power positions for binary numbers are shown in Table 2. Table 2 Base 2 Powers Equal to 27 128 26 64 25 32 24 16 23 8 22 4 21 2 20 1

As discussed previously, the position of each digit in a number determines its value. e.g. 1010 11012 is a binary number and is pronounced as: one, zero, one, zero, one, one, zero, one The subscript of 2 after the number indicates that it is a binary number. Its decimal equivalence can be calculated as follows: Table 3 Binary to decimal equivalence Powers Equal to Binary no. 2
7

26 64 0

25 32 1

24 16 0

23 8 1

22 4 1

21 2 0

20 1 1

128 1

Writing in expanded notation gives: (1 27) + (0 26) + (1 25) + (0 24) + (1 23) + (1 22) + (0 21) + (1 20) 128 + 0 + 32 + 0 + 8 + 4 + 0 + 1 = 17310 The subscript of 10 after the number indicates that it is a decimal number.

SQA Version 1

20

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a d g

1.3

Complete the following questions and check your answers with those given at the back of the section. Find the decimal equivalence to the following binary numbers: 102 1101 01012 1000 11102 b e h 1012 0100 00012 1010 01012 c f i 11012 1110 10012 0001 01102

For the following questions you will have to extend your table to show higher powers the method is the same. j l 1100 1001 10112 1000 0111 0111 01012 k m 0111 1100 00112 1111 1111 0000 11112

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Hexadecimal numbering All data is stored and moved around inside a computer in binary form. However, binary numbers can comprise very long strings of 0s and 1s when they are representing large numbers. For us humans the large binary numbers become difficult to understand and handle and are therefore prone to human error. Thus it is convenient to express the numbers in base 16, known as hexadecimal, instead of base 10 or base 2. That is to say, hexadecimal is a shorthand way of writing binary numbers to aid human understanding. Computers do not work in hexadecimal. The hexadecimal system (shortened to hex) requires 16 symbols to represent the digits from 0 to 15. Since 10 to 15 are outside normal single decimal digits, the letters A to F are used to represent 10 to 15. The hexadecimal number system therefore uses 16 symbols, namely, 0 1 2 3 4 5 6 7 8 9 A B C D E F (10) (11) (12) (13) (14) (15) Since the hexadecimal number system has 16 different symbols, the base is 16. The power positions for hexadecimal numbers (base 16) are shown in Table 4.

SQA Version 1

21

Developed by COLEG

Computer Architecture 1

DH2T 34

Table 4 Base 16 Powers Equal to 16


7

166 1 677 216

165 1 048 576

164 65 536

163 4 096

162 161 160 256 16 1

268 435 456

Note: Remember that the position of each digit in a number determines its value. e.g. 10B216 is a hexadecimal number and is pronounced as: one, zero, B, two The subscript of 16 after the number indicates that it is a hexadecimal number. Its decimal equivalence can be calculated as follows: Table 5 Hexadecimal to decimal equivalence Powers Equal to Hex no. 167 268 435 456 166 1 677 216 165 1 048 576 164 65 536 163 4 096 1 162 161 160 256 0 16 B 1 2

Writing in expanded notation gives: (1 163) 4096 = e.g. A10C4916 + + (0 162) (0) 0 427410 is a hexadecimal number and is pronounced as: + + + (B 161) + (2 160) (11 16) + (2 1) 176 + 2 (1 4096) +

A, one, zero, C, four, nine The subscript of 16, after the number, indicates that it is a hexadecimal number. Powers Equal to Hex no. 167 268 435 456 166 1 677 216 165 1 048 576 A 164 65 536 1 163 4 096 0 162 161 160 256 C 16 4 1 9

SQA Version 1

22

Developed by COLEG

Computer Architecture 1

DH2T 34

Writing in expanded notation gives: (A 165) 10 485 760 = + + (1 164) 65 536 + (0 163) + (C 162) + (4 161) + (0) 0 + (12 256) + (4 16) + + 3 072 + 64 + + (9 160) (9 1) 9 (10 1 048 576) + (1 65 536) + 10 554 44110

?
a b c d e f g h i j

1.4

Complete the following questions and check your answers with those given at the back of the section. Find the decimal equivalence to the following hexadecimal numbers: A62116 F216 3BB166 E41E16 1CC116 213416 ABBA16 D79116 AA16 B18716

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Octal system The octal number system is based on the binary system with a 3-bit boundary. It uses base 8 (i.e. the digits 0 through 7). The weighted values for each position are as follows: 85 32768 84 4096 83 512 82 64 81 8 80 1

SQA Version 1

23

Developed by COLEG

Computer Architecture 1

DH2T 34

Octal to binary conversion Convert the decimal number to its 3-bit binary equivalent. Combine the 3-bit sections by removing the spaces. For example, the octal value 5614 will be written: 5 101 6 110 1 001 4 100

This returns the binary number 1011 1000 1100 Binary to octal conversion Break the binary number into sections of three. For example, the binary value 1110011000110 will be written: 001 1 110 6 011 3 000 0 110 6

This returns the octal number 16306

?
a

1.5

Convert these binary digits to octal. 110011 b 111010110 c 1100110011

Convert octal to binary. d 171 e 256 f 6427 g 375134

SQA Version 1

24

Developed by COLEG

Computer Architecture 1

DH2T 34

Other number systems It follows that any number system with base R can employ the column headings: Powers R7 R6 R5 R4 R3 R2 R1 R0

Base conventions
Decimal notation Binary notation Hexadecimal notation numbers without any subscript are decimal. all binary numbers are followed by a subscript of 2 unless it is clear from the context. all hex numbers are followed by a subscript of 16 unless it is clear from the context.

One important convention should be made clear and almost goes without saying. The convention is to read, write and pronounce strings such as 1011 0101, from left to right. For example you read 1011 0101 as one, zero, one, one, zero, one, zero, one. The table below shows the relationship between binary, decimal and hexadecimal numbers:

SQA Version 1

25

Developed by COLEG

Computer Architecture 1

DH2T 34

Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F

It would be beneficial if you took some time to memorise the table above, so that when you are presented with a binary 4-bit pattern you are immediately able to translate the pattern into a decimal or hexadecimal value.

SQA Version 1

26

Developed by COLEG

Computer Architecture 1

DH2T 34

Converting between base 10, base 2 and base 16 number systems


Decimal to binary To convert a number from decimal to binary you divide the number repeatedly by 2. The remainder at each stage is either a 1 or a 0. This continues until the quotient is 0. The binary equivalent is the remainder digits, read from the bottom to the top of the list. Example Convert 11310 to a binary number. 2 113 1 2 3 4 5 6 7 113/2 = 56 56/2 = 28 28/2 = 14 14/2 = 7 7/2 = 3 3/2 = 1 1/2 = 0 Remainder 1 Remainder 0 Remainder 0 Remainder 0 Remainder 1 Remainder 1 Remainder 1 2 56 2 28 2 14 2 7 2 3 2 1 0 R1 R0 R0 R0 R1 R1 R1

Reading the remainder digits from bottom to top gives 111 00012 i.e. 11310 = 111 00012 Check using the technique from Table 3: Binary to decimal equivalence. Powers Equal to Binary no. 27 128 26 64 1 25 32 1 24 16 1 23 8 0 22 4 0 21 2 0 20 1 1

113

64 +

32

16

SQA Version 1

27

Developed by COLEG

Computer Architecture 1

DH2T 34

Example Convert 23510 to a binary number. 2 235 1 2 3 4 5 6 7 8 235/2 = 117 117/2 = 58 58/2 = 29 29/2 = 14 14/2 = 7 7/2 = 3 3/2 = 1 1/2 = 0 Remainder 1 Remainder 1 Remainder 0 Remainder 1 Remainder 0 Remainder 1 Remainder 1 Remainder 1 2 117 2 58 2 29 2 14 2 7 2 3 2 1 0 R1 R1 R0 R1 R0 R1 R1 R1

Reading the remainder digits from bottom to top gives 111010112 i.e. 23510 111010112 Check using the technique from Table 3: Binary to decimal equivalence. Powers Equal to Binary no. 235 = 27 128 1 128 + 26 64 1 64 + 32 25 32 1 + 24 16 0 8 23 8 1 + 22 4 0 2 21 2 1 + 1 20 1 1

SQA Version 1

28

Developed by COLEG

Computer Architecture 1

DH2T 34

1.6

Complete the following questions and check your answers with those given at the back of the section. Convert the following decimal numbers to binary: a e i 8110 8810 5810 b f 5710 9910 c g 12210 23110 d h 15610 13110

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Binary to decimal The easiest way is to use the base 2 table, as shown in Table 3: Binary to decimal equivalence. You may have to extend the table for larger numbers. Example Convert 1001 11012 to a decimal number. Powers Equal to Binary no. 15710 = 27 128 1 128 + 26 64 0 25 32 0 24 16 1 16 + 23 8 1 8 + 22 4 1 4 21 2 0 + 20 1 1 1

i.e. 1001 11012 = 15710

SQA Version 1

29

Developed by COLEG

Computer Architecture 1

DH2T 34

Example Convert 1101 0110 1000 11112 to a decimal number. Powers Equal to Binary no. 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

32 768 16 384 8 912 4 096 2 048 1 024 512 256 128 64 32 16 8 4 2 1 1 1 0 + 4 096 1 0 1 1 0 1 0 0 0 1 1 1 1 +8+4+2+1

54 92710 = 32 768 + 16 384

+ 1 024 + 512 + 128

i.e. 1101 0110 1000 11112 = 54 92710

?
a d g j

1.7

Complete the following questions and check your answers with those given at the back of the section. Convert the following binary numbers to decimal: 1101 01012 1000 10102 0000 10002 1 11012 b e h 0011 10102 0010 00012 1110 00002 c f i 1111 11102 1101 11112 1111 01012

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

30

Developed by COLEG

Computer Architecture 1

DH2T 34

Decimal to hexadecimal To convert a number from decimal to hexadecimal, the same technique is used as in the conversion from decimal to binary, except we divide repeatedly by 16. Since this is slightly trickier and usually requires a calculator, any conversions of this type in the assessment should contain no more than three decimal digits. Example Convert 5492710 to a hexadecimal number. 16 54 927 1 2 3 4 5 6 54 927/16 = 56 3 432/16 = 214 214/16 = 214 13/16 = 0 Remainder 15 Remainder 8 Remainder 6 Remainder 13 16 3 432 16 214 16 13 16 0 R15 R8 R6 R13

Read the remainder digits from bottom to top Convert remainders to hex numbers: 13, 6, 8, 15 = D68F16 54 92710 = D68F16

SQA Version 1

31

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a d

1.8

Complete the following questions and check your answers with those given at the back of the section. Convert the following numbers to hexadecimal: 41810 67510 b 88810 c 7810

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Hexadecimal to decimal Again the base table is used, this time for base 16 (Table 5: Hexadecimal to decimal equivalence). Example Convert D68F16 to a decimal number. Powers Equal to Hex no. 163 4 096 D 162 256 6 161 16 8 160 1 F

= = = = 54

(D 4

096) + (6 256) + 1 536

+ +

(8 16) (8 16) 128

+ (F 1) + (15 1) + 15

(13 4 096) + (6 256) + 53 248 92710 92710

D68F16 = 54

SQA Version 1

32

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a d g

1.9

Complete the following questions and check your answers with those given at the back of the section. Convert the following hexadecimal numbers to decimal: 3F16 123416 22216 b e AAB16 34316 c f B1116 1416

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Hexadecimal to binary To convert from hexadecimal to binary is relatively simple since 16 = 24. This means that each hexadecimal digit is equivalent to 4 binary digits. Example Convert D68F16 to a binary number. Hexadecimal no. Decimal equivalent Binary powers Equivalent to Binary no. D 13 6 6 8 8 F 15

23 22 21 20 23 22 21 20 23 22 21 20 23 22 21 20 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 1 1

D68F16 = 1101 0110 1000 11112 With practice you can miss out the intermediate steps.

SQA Version 1

33

Developed by COLEG

Computer Architecture 1

DH2T 34

Example Convert 2B3A16 to a binary number. Hex no. Dec. equivalent Binary no. 2 2 0010 B 11 1011 3 3 0011 A 10 1010

Remember you require 4 binary digits for each hexadecimal digit. i.e. 2B3A16 = 0010 1011 0011 10102

?
a d g j

1.10

Complete the following questions and check your answers with those given at the back of the section. Convert the following hexadecimal numbers to binary: 41816 2 FF16 3 88916 88810 b e h 3 21916 1 36416 67516 c f i ABC16 5 12416 4 13816

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

34

Developed by COLEG

Computer Architecture 1

DH2T 34

Binary to hexadecimal With binary to hexadecimal the binary digits are arranged in groups of 4 starting from the right. Each group of 4 digits is converted to its hexadecimal equivalent. Example Convert 1101 0110 1000 11112 to a hexadecimal number. Binary powers Equivalent to Binary no. Decimal equivalent Hexadecimal no. 23 22 21 20 23 22 21 20 23 22 21 20 23 22 21 20 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 1 1 13 D 6 6 8 8 15 F

i.e. 1101 0110 1000 11112 = D68F16 Again, with practice, you can miss out the intermediate steps. Example Convert 11 0101 10102 to a hexadecimal number. Include leading 0s to make a 4-digit number. Remember to start from the right.

Binary no. Dec. equivalent Hex no. i.e. 11 0101 10102 = 35A16

0011 3 3

0101 5 5

1010 10 A

Now its time to complete the last SAQ of this section.

SQA Version 1

35

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a d g j

1.11

Complete the following questions and check your answers with those given at the back of the section. Convert the following binary numbers to hexadecimal: 1101 01012 1000 10102 0000 10002 1 11012 b e h 0011 10102 0010 00012 1110 00002 c f i 1111 11102 1101 11112 1111 01012

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

36

Developed by COLEG

Computer Architecture 1

DH2T 34

1.1

This will help your understanding of the implications of number systems to the computing professional. Using books, the internet or computer magazines, identify some of the areas where the following computer professionals might apply their knowledge of number systems: a Software developers .. .. .. b Support staff .. .. .. c Network staff .. .. .. d Multimedia developers .. .. ..

SQA Version 1

37

Developed by COLEG

Computer Architecture 1

DH2T 34

T
a b c d

1.1

To complete the work of the section, you should now attempt the tutor assignment which follows and send it off to your tutor for marking. 1 Convert from decimal to binary: 3 82410 4 09410 10610 85310

2 Convert from binary to decimal: a b c d 10 0011 10012 1 0101 1000 01112 10112 10 0110 10002

3 Convert from binary to hex: a b c d 1010 0010 1100 11002 1111 0001 1111 00002 0011 11102 110 1101 1001 11112

SQA Version 1

38

Developed by COLEG

Computer Architecture 1

DH2T 34

4 Convert from hex to binary: a b c d ED0816 2B6716 DAF16 D10E916

5 Convert from decimal to hex: a b c d 9 31210 24 15810 21010 3 21510

6 Convert from hex to decimal: a b c d 3D9416 FF1116 4B616 7C2F16

SQA Version 1

39

Developed by COLEG

Computer Architecture 1

DH2T 34

Summary of this section


By this stage you should have learned about different number bases, particularly the binary, decimal and hexadecimal systems. You should also be competent in converting integer values between these three number bases. If you are experiencing any difficulties with this section, or you have any enquiries, you should contact your tutor for advice.

SQA Version 1

40

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to SAQs
SAQ 1.1 a d 34 = 81 26 = 64 b e 102 = 100 91 = 9 c f 73 = 343 30 = 1

SAQ 1.2 a b c d 9 821 = (9 1 000) + (8 100) + (2 10) + (1 1) 11 342 = (1 10 000) + (1 1 000) + (3 100) + (4 10) + (2 1) 1 102 = (1 1 000) + (1 100) + (2 1) 99 874 = (9 10 000) + (9 1 000) + (8 100) + (7 10) + (4 1)

SAQ 1.3 a c e g i k m 102 = 210 1101 = 1310 0100 00012 = 6510 1000 11102 = 14210 0001 01102 = 2210 0111 1100 00112 = 1 98710 1111 1111 0000 11112 = 65 29510 b d f h j l 1012 = 510 11012 = 21310 1110 10012 = 23310 1010 01012 = 16510 1100 1001 10112 = 3 22710 1000 0111 0111 01012 = 34 67710

SAQ 1.4 a c e g i A62116 = 42 52910 3BB16 = 95510 1CC116 = 7 36110 ABBA16 = 43 96210 AA16 = 17010 b d f h j F216 = 24210 E41E16 = 58 39810 213416 = 8 50010 D79116 = 55 18510 B18716 = 45 44710

SAQ 1.5 a c e g 110011= 63 1100110011= 1463 256= 0 1010 1110 b d f 111010110= 726 171= 0 0111 1001 6427= 1101 0001 0111

375134= 01 1111 1010 0101 1100

SQA Version 1

41

Developed by COLEG

Computer Architecture 1

DH2T 34

SAQ 1.6 a c e g i 8110 = 101 00012 12210 = 111 10102 8810 = 101 10002 23110 = 1110 01112 5810 = 11 10102 b d f h 5710 = 11 10012 15610 = 1001 11002 9910 = 110 00112 13110 = 1000 00112

SAQ 1.7 a c e g i 1101 01012 = 21310 1111 11102 = 25410 0010 00012 = 3310 0000 10002 = 810 1111 01012 = 24510 b d f h j 0011 10102 = 5810 1000 10102 = 13810 1101 11112 = 22310 1110 00002 = 22410 111012 = 2910

SAQ 1.8 a c 41810 = 1A216 7810 = 4E16 b d 88810 = 37816 67510 = 2A316

SAQ 1.9 a c e g 3F16 = 6310 B1116 = 2 83310 34316 = 83510 22216 = 54610 b d f AAB16 = 2 73110 123416 = 4 66010 1416 = 2010

SAQ 1.10 a b c d e f g h i j 41816 = 0100 0001 10002 3 21916 = 0011 0010 0001 10012 ABC16 = 1010 1011 11002 2 FF16 = 0010 1111 11112 1 36416 = 0001 0011 0110 01002 5 12416 = 0101 0001 0010 01002 3 88916 = 0011 1000 1000 10012 67516 = 0110 0111 01012 4 13816 = 0100 0001 0011 10002 88816 = 1000 1000 10002

SQA Version 1

42

Developed by COLEG

Computer Architecture 1

DH2T 34

SAQ 1.11 a c e g i 1101 01012 = D516 1111 11102 = FE16 0010 00012 = 2116 0000 10002 = 816 1111 01012 = F516 b d f h j 0011 10102 = 3A16 1000 10102 = 8A16 1101 11112 = DF16 1110 00002 = E016 1 11012 = 1D16

SQA Version 1

43

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to activity
Responses to activity 1.1

Software developers are likely to need to understand the implications of number systems so that informed decisions can be made about the choice of variable types when programming. Support staff will be faced with the need to perform base conversions when installing hardware. Network staff will be required to perform base conversions and masking operations when calculating network addresses. Multimedia developers will benefit from knowledge of underlying representations when selecting file formats to store images.

b c d

SQA Version 1

44

Developed by COLEG

Computer Architecture 1

DH2T 34

Section 2: Data representation internal representation of values

SQA Version 1

45

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

46

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction to this section


What this section is about This section addresses the issues of how some further data types are represented in computer memory, and how logical (Boolean) operations can be performed on binary numbers. Outcomes, aims and objectives The aims of this section are to introduce: 1 2 3 4 5 6 ASCII representations of characters Boolean logic operators simple combination of logic gates signed notation binary addition fixed point numbers.

Approximate study time 8 hours. Other resources required A working internet connection will be indispensable for some of the activities. A calculator will be helpful for some of the calculations. The desktop calculator supplied with most GUI operating systems will be sufficient.

SQA Version 1

47

Developed by COLEG

Computer Architecture 1

DH2T 34

Assessment information for this section


How you will be assessed The topics in this section form the second part of the materials for Outcome 1. The other part of this outcome can be found in Section 1. There is a tutor assignment at the end of this section for your guidance. The summative assessment comes after you have completed Section 2. Upon successful completion of the summative assessment you will have also completed the using number component of the numeracy core skill which has been embedded in this outcome. When and where you will be assessed The assessment at the end of Section 2 will be in the form of an in-class assessment. The assessment will be closed book and carried out under supervised conditions. This is a formal assessment and it will be held in college but if you are likely to have a problem in attending college then ask your tutor for advice. What you have to achieve The summative assessment for Outcome 1 takes the form of 20 multiple-choice questions that must be completed in an hour. Calculators are not allowed. A candidate must achieve 60% (i.e. 12 correct from the 20 questions) to successfully achieve the required standard. Opportunities for reassessment If you are unsuccessful on your first attempt you will be given an opportunity to be reassessed. The reassessment will be carried out under the same supervised, closed book arrangements as the first attempt. A different selection of questions should appear in the reassessment.

SQA Version 1

48

Developed by COLEG

Computer Architecture 1

DH2T 34

ASCII characters and their representation


As with all data values stored in a digital computer, characters are stored as bit patterns. One of the more important ways of storing text in computer memory is American Standard Code for Information Interchange (ASCII). This standard was defined for seven-bit values, so only 128 character codes are possible. The characters have code numbers ranging from 0 to 127, and the bit patterns are assigned in the same way that we have already seen the numbers 0 to 127 assigned previously. The characters in the ASCII set are in general those used in English-speaking countries. As only 128 characters codes are possible in ASCII a provision was required to accommodate the many additional character codes required for different languages (Greek, Japanese, etc.). Unicode is the provision available which allows 65,000 character codes. Note that some of the codes are assigned to control characters, such as carriage return (CR), line feed (LF), escape (ESC), fast forward, etc. These control characters can be used to control data transmission as well as how text is displayed on output devices.

SQA Version 1

49

Developed by COLEG

Computer Architecture 1

DH2T 34

Name NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US

Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Name SPACE ! " # $ % & ' ( ) * + , . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ?

Code 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
50

Name @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _

Code 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Name ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL

Code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127

SQA Version 1

Developed by COLEG

Computer Architecture 1

DH2T 34

There are a few things worth noting about the previous table. The first thing is that all of the characters with a code of less than 3210 (space) are control characters. The next thing is that all of the alphabetic characters A to Z form a sequence, as do the characters a to z. Notice also that there is always a consistent gap between a lower case letter and the corresponding upper case letter. Although by no means the only way of encoding characters, ASCII is still very important. A useful site for ASCII code is http://www.asciitable.com. This site states decimal, hexadecimal and octal values.

Unicode characters and their representation


The Unicode character set is a superset of the ASCII character set with provisions made for handling international symbols and characters from other languages. Unicode is sixteen bit, which means that it can represent more than 65,000 unique characters. This is not required for English, but it is necessary for some other languages, such as Greek, Chinese and Japanese. Since there are so many characters a Unicode sheet is not provided in these notes. Go to the website http://www-atm.physics.ox.ac.uk/user/iwi/charmap.html and look at the Basic Latin character set. One circumstance in which character coding is important is when sorting. The order in which strings (a string is a sequence of characters, such as a name) will be sorted will depend on the collation sequence (the order in which codes are given to characters). For example, in ASCII any string starting with a space will sort before a string starting with any other printing character. Some languages use characters not included in seven-bit ASCII. These include accented characters and currency symbols. Some of these can appear in an eight-bit version of ASCII, which makes a further 128 symbols possible. Different national language character sets tend to offer different characters tailored for that country, so there is large scope for variation.

SQA Version 1

51

Developed by COLEG

Computer Architecture 1

DH2T 34

?
a (i) (ii) (iii) b (i) (ii) (iii) (iv) c d e f

2.1

Complete the following questions and check your answers with those given at the back of the section. Using the ASCII chart on the previous page: Convert the ASCII code for C into a binary number. .. Convert 2316 into the corresponding ASCII character. .. Convert the ASCII character H into hexadecimal. .. Using the website on the previous page: Convert the Unicode for C into a binary number. .. Convert 2316 into the corresponding Unicode character. .. Convert the Unicode character H into hexadecimal. .. Convert the digit 9 into binary. .. What is the value for ASCII code 9? .. Work out the byte sequence for XYZ. .. Work out the byte sequence for xyz. .. Work out the byte sequence for 123. .. If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

52

Developed by COLEG

Computer Architecture 1

DH2T 34

Boolean or logic operators


There are four Boolean logic operations that we will discuss in this section. They are the NOT (also called INVERT) operation, the AND operation, OR and XOR (also referred to as Exclusive OR). These operations are more or less familiar to us in everyday usage, and also form the basis of the electronic circuits that make up computer systems. When they appear in computer systems they are also called gates. Boolean logic operates on the two Boolean truth values, TRUE and FALSE. Inside a computer, these truth values are usually represented by binary 1 and binary 0. Each of the logic operators will have one or more inputs which will be processed to deliver one output. It is useful to visualise a logic gate as a black box that has truth values going into it and a truth value coming out of it. The value of the output is determined by the values sent to it and the particular type of the logic gate. The NOT operator The NOT operation is the simplest, and the action of a NOT operation is to turn any TRUE values into FALSE, and any FALSE values into TRUE. This is possibly most easily shown by drawing the truth table for the operation. The column labelled A is the input to the operation, and the column labelled X is the output. A TRUE FALSE In words we say: and: X FALSE TRUE

NOT TRUE is FALSE NOT FALSE is TRUE.

The symbol for the NOT gate is:

We can also present the truth table in binary as: A 1 0 e.g. NOT 1100=0011 NOT 0110011=1001100 NOT 101000110= 010111001 X 0 1

SQA Version 1

53

Developed by COLEG

Computer Architecture 1

DH2T 34

2.2

Now apply the logical NOT operator to the following binary numbers: 10101010 10001101 00110010 10000000

The AND operator The next operation that we will look at is the two-input AND. This takes two truth values as inputs and delivers one truth value as a result. For clarity, the first input is labelled A, the second input is labelled B and the output is labelled X. The rules for AND can be summarised by the following truth table:

A 0 0 1 1

B 0 1 0 1

X 0 0 0 1

Notice that the AND operation will only deliver TRUE when both of the inputs are TRUE. If either of the inputs is FALSE then the output will be FALSE. Consider the following sentences: I will only go to the cinema if there is a film I want to see AND I have enough money to go. This contains an AND operation, and both conditions must be TRUE for the outcome of going to the cinema to be TRUE. If either (or both) of the conditions is FALSE, then I will not go to the cinema. The logic gate symbol for AND is:

A X B

SQA Version 1

54

Developed by COLEG

Computer Architecture 1

DH2T 34

There are two different forms of layout as shown in the two examples below: e.g. 1100 AND 1111 = 1100 1100 1111 AND 1100 10111 AND 01101= 00101 10111 00101 AND 00101

2.3

Now apply the logical AND operator to the following pairs of binary numbers. 11001100 11110110 AND 00110011 00100111 AND 11111111 11100001 AND 10100001 01110100 AND

11100 AND 10011=

11100101 AND 10011010=

SQA Version 1

55

Developed by COLEG

Computer Architecture 1

DH2T 34

The OR operator The next operation that we will consider is the two-input OR statement. This also takes two truth values as inputs and delivers one truth value as a result. The rule for OR is that if either input is TRUE then the output will be TRUE. In everyday language we say things like, If it is raining OR if the forecast is for rain later then I will take an umbrella. Notice that if both conditions are true, then the outcome will also be true. The OR operator is sometimes called the inclusive OR. We can draw a truth table for OR. It looks like this: A 0 0 1 1 The diagram for a hardware OR gate is: B 0 1 0 1 X 0 1 1 1

A X B

2.4

Now apply the logical OR operator to the following pairs of binary numbers. 11001100 11110110 00110011 00100111 11111111 11100001 10100001 01110100

SQA Version 1

56

Developed by COLEG

Computer Architecture 1

DH2T 34

The NAND and the NOR operator The NAND gate and the NOR gate are said to be universal gates as the combinations can be used to produce an inverter, an OR gate or an AND gate. The NAND gate (Not AND) This is an AND gate with the output inverted. The output is true if input A AND input B are NOT both true: X = NOT (A AND B). A NAND gate can have two or more inputs; its output is true if NOT all inputs are true.

A B

For clarity, the first input is labelled A, the second input is labelled B and the output is labelled X. The rules for AND can be summarised by the following truth table:

A 0 0 1 1

B 0 1 0 1

X 1 1 1 0

Notice that the NAND operation will only deliver TRUE when one or both of the inputs are FALSE. If both of the inputs are TRUE then the output will be FALSE. e.g. 10100 10011 01111 1001110 1011011 0110101 0110110101 1001101101 1111011010

SQA Version 1

57

Developed by COLEG

Computer Architecture 1

DH2T 34

2.5

Now apply the logical NAND operator to the following pairs of binary numbers: 10110 10010 11010001 10010000 1000110001 0110010111

The NOR gate (Not OR) This is an OR gate with the output inverted. The output X is true if NOT inputs A OR B are true: X = NOT (A OR B) A NOR gate can have two or more inputs; its output is true if no inputs are true.
A B

For clarity, the first input is labelled A, the second input is labelled B and the output is labelled X. The rules for OR can be summarised by the following truth table A 0 0 1 1 B 0 1 0 1 X 1 0 0 0

Notice that the NOR operation will only deliver TRUE when both of the inputs are FALSE. If any of the inputs are TRUE then the output will be FALSE. The examples below are the same as for the NAND gates on the previous page. Notice the different results. e.g. 10100 10011 01000 1001110 1011011 0100000 0110110101 1001101101 0000000000

SQA Version 1

58

Developed by COLEG

Computer Architecture 1

DH2T 34

2.6

Now apply the logical NOR operator to the following pairs of binary numbers. 10110 10010 11010001 10010000 1000110001 0110010111

The XOR operator The next gate to consider is the two-input XOR function (also called the eXclusive OR). The function will return a TRUE if either input is TRUE. If both inputs are FALSE then the output will be FALSE. So far this looks the same as for OR , but for an XOR if both inputs are TRUE, then the output will be FALSE. The truth table for this is: A 0 0 1 1 The diagram for an XOR gate is: B 0 1 0 1 X 0 1 1 0

A X B
XOR is perhaps less used in everyday conversation than the others presented here, but can be useful in computing situations.

2.7

Now apply the logical XOR operator to the following pairs of binary numbers. 11001100 11110110 00110011 00100111 11111111 11100001 10100001 01110100

SQA Version 1

59

Developed by COLEG

Computer Architecture 1

DH2T 34

2.1

Without referring to notes, write out the binary truth tables for NOT, AND, OR, NAND, NOR and XOR. Once you have done this, check back to make sure that you have remembered them correctly.

SQA Version 1

60

Developed by COLEG

Computer Architecture 1

DH2T 34

Simple combinations of logic gates A computer system can be viewed as a large collection of these logic gates, combined in such a way that the inputs of some gates are provided by the outputs of others. For example, one way of providing a three-input AND gate is to combine two AND gates in the fashion shown below.

A B

X C
We could also write this as (A AND B) AND C (remember that anything in brackets is evaluated first). To check that this is a three-input AND, we should construct a truth table. Note that there is an intermediate value D (the result of input A.B) inserted in the table to make things easier to follow. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D 0 0 0 0 0 0 1 1 X 0 0 0 0 0 0 0 1

Note: The inputs in the table are written in ascending binary order (000, 001, 010, etc.). As there are three inputs, each of which can have two different values, there will be 2*2*2 (= 8) entries in the table. The value of D can be determined by looking at A AND B, and the value of X can be determined by looking at C AND D. From this table we can see that the only time that X is TRUE is when all three inputs are TRUE.

SQA Version 1

61

Developed by COLEG

Computer Architecture 1

DH2T 34

2.8

Complete the following questions and check your answers with those given at the back of the section. Draw the truth table for the following arrangement of gates.

A B

X C
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D X

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

62

Developed by COLEG

Computer Architecture 1

DH2T 34

2.9

Complete the following questions and check your answers with those given at the back of the section. Draw a truth table for the following set of gates, and confirm that it is ((A AND B) AND (C AND D)).

A B

E X

C D
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

F
E F X

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

63

Developed by COLEG

Computer Architecture 1

DH2T 34

Logic operations on bytes


Most CPUs provide a facility for performing logic operations between two values. As most CPU operations operate on groups of bits (usually bytes or words), the logic operations operate on groups of bits. Remember that a byte is 8 bits, and that a word is the number of bits that the processor can manipulate in one operation. Words are usually a number of bytes, e.g. 8 bits, 16 bits, etc. The simplest is the NOT operation. This operates on all of the bits in a group, and changes each one to a zero and each zero to a one. If we assume that a processor operates on 8 bits (one byte) at a time, the effect of applying the NOT operator to the byte: 1 is 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0

Or as shown previously: NOT 10011000 = 01100111

As the operator is applied to each bit in turn, these operations are sometimes called bitwise operations. Note that as each bit is effectively dealt with on an individual basis, there is no need to concern ourselves with having to carry information from one column to another. Similarly, the processor can apply the two-input logic operations. This of course requires two bytes to be processed to give a third (output) byte. In the case of the AND logical operator, if we have the byte: 1 1 1 1 0 0 0 0

perform the AND operation with: 1 the result will be: 1 I 0 1 0 0 0 0 0 0 1 0 1 0 1 0

SQA Version 1

64

Developed by COLEG

Computer Architecture 1

DH2T 34

n effect the output bye is the result of eight AND gates whose inputs are the bits in the first two bytes. 11110000 10101010 AND 10100000 Using the same reasoning: 1 OR 1 will give an output of: 1 1 11110000 10101010 11111010 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 0

A X B

A X B

The use of the bitwise operators allows some quick manipulations to be made to data. This is particularly useful when dealing with low level information such as data being passed to and from a computer.

SQA Version 1

65

Developed by COLEG

Computer Architecture 1

DH2T 34

Calculating the range of bit patterns A binary digit can have two different values, 0 and 1. In order to represent larger values it is necessary to combine bits into groups. In this section we will see how to calculate the number of different patterns that can be represented by binary values with a given number of positions. Apart from one bit, the smallest bit pattern that we can use is two bits. As each bit can have two different values, 0 and 1, we can draw up a table showing all of the possible combinations. Bit 1 0 0 1 1 Bit 0 0 1 0 1

There are no other combinations of two binary digits, so we can see that there are four possible unique combinations. The formula can help calculate the number of possible unique combinations. 2n = X 3 bits 2 =8 If we extend this to three bits, we can draw the following table: Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1
3

i.e. 2the number of bits = possible unique combinations i.e. 2 x 2 x 2 = 8

This gives us eight unique patterns. Notice that the pattern for the two bits, bit 0 and bit 1, appears twice in this pattern, once in lines 0 to 3 where they are combined with bit 2 set to zero, and once in lines 4 to 7, where bit 2 is set to one.

SQA Version 1

66

Developed by COLEG

Computer Architecture 1

DH2T 34

We can start to draw a table to show how the number of possible patterns changes with the number of bits. A formula to work out the number of possible patterns is: 2n = X if 4 bits i.e. 2no of bits = number of bit patterns then 24 = 16

Number of bits 1 2 3

Number of patterns 2 2*2 2*2*2

It seems that each time we add another bit to the number of bits, the number of patterns is doubled. Drawing the table for four bits we get: Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

SQA Version 1

67

Developed by COLEG

Computer Architecture 1

DH2T 34

Using four bits permits the generation of sixteen unique patterns, twice that of three bits.

2.10

Complete the following question and check your answers with those given at the back of the section. Using the rule developed above, complete the following table:

Number of bits 1 2 3 4 5 6 7 8 9 10

Number of patterns 2 4 8 16

If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

Adding numbers in binary


Addition in binary works very much the same as addition in base ten, except that it is very much simpler. Here are the rules: 02 + 02 = 02 12 + 02 = 12 12 + 12 = 102 (or to put it another way a carry is generated). As with arithmetic in base ten we start at the right-hand column (the least significant) and work to the left, dealing with any carries.

SQA Version 1

68

Developed by COLEG

Computer Architecture 1

DH2T 34

For example:

1102 +0112 First add the right-hand columns (1 + 0 = 1). Then add the next column (1 + 1 = 0 carry 1). Add the third column (0 + 1 = 1, plus 1 carried from previous column = 0 carry 1). Create a new fourth column, and place the carry into it to give 1.

1102 +0112 10012 To check our work, we can do the same sum in base 10.
1102 +0112 10012 610 +310 910

SQA Version 1

69

Developed by COLEG

Computer Architecture 1

DH2T 34

Signed notation

One drawback of the positional notation that we have seen so far is that it only allows us to represent positive whole numbers. One way of overcoming this limitation is to have the most significant bit value represent the negative quantity. For eight-bit numbers this would mean that the left-hand column no longer represents the number of 128s (27), but now represents the number of 128s. This is called signed notation. Using this signed notation the 8-bit binary number 1011 01012 is interpreted as 7510. If we draw a table with the positions and their meaning we get: 1 1 * 128 0 0 * 64 1 1 * 32 1 1 * 16 0 0*8 1 1*4 0 0*2 1 1*1

Performing the arithmetic:


1 +4 +16 +32 128 75 The highest number that can be represented using 8 bits is: 0111 11112 1000 00002 (0 + 64 + 32 + 16 + 8 + 4 + 2 + 1) (128 + 0 + 0 + 0 + 0 + 0 + 0 + 0) This converts to 12710. This converts to 12810. The lowest number that can be represented using 8 bits is: The range of an eight-bit signed integer is thus 128 to +127. Notice that this still gives a total of 256 different possibilities, but the way in which we interpret the binary patterns is modified. Note that in signed notation it is always the most significant bit that is used as the sign bit, so in a sixteen-bit value the most significant bit represents 32 768 rather than the 32 768 that it would represent in the unsigned representation.

SQA Version 1

70

Developed by COLEG

Computer Architecture 1

DH2T 34

2.11

Complete the following question and check your answer with the one given at the back of the section. Convert the eight-bit signed value 1001 01102 into its decimal equivalent. .. If you have anything wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Converting negative base 10 numbers into signed representation binary can be performed in much the same way as converting positive numbers, but it is important not to try and convert a number that is out of range, for example it is not possible to convert 200 into an eight-bit signed representation. If the number is negative, remember to add the value of the first column rather than subtract it as used in the repeated subtraction method.
Example

Convert 9410 into an eight-bit signed binary representation. Step 1: Subtract 94 from 128. 3410 = 10 00102 Step 3: Write this down as a 7-digit number. 1010 00102 From this we can see that 9410 converts to 1010 00102. To check our work we will reconvert this: 010 00102 Step 4: Now write it as an 8-digit number. It starts with a 1 since it is negative. (128 94 = 34) Step 2: Using the rules given in Section 1, convert 3410 to binary.

128 +32 +2 94
There is another way of converting 94 into a signed notation. The process involves three steps. 1 Ignore the minus sign for now, and convert the number into binary in the usual fashion. So, for example we would start converting 9410 by converting 9410 into 0101 11102. It important in this operation to include any leading zeros.

SQA Version 1

71

Developed by COLEG

Computer Architecture 1

DH2T 34

Invert each of the bits in the result from the previous stage, so 0101 11102 would become 1010 00012. As each bit has been inverted or complemented, this is sometimes known as ones complement. Add 1 to the result of the previous operation. In this example, 1010 00012 + 1 = 1010 00102. This representation is usually known as twos complement.

It is also possible to convert a negative number back into a positive number (effectively multiplying by 1) by performing the same sequence of steps. This can be very useful when checking your work.

2.12

Complete the following question and check your answer with that given at the back of the section. Convert 7710 into signed eight-bit binary. .. .. .. If you have anything wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

72

Developed by COLEG

Computer Architecture 1

DH2T 34

Subtracting binary numbers

Although it is perfectly possible to perform subtraction operations using binary numbers, many processors do not provide a subtract operation. This is in an attempt to reduce the complexity of the processor. The failure to provide a subtract operation is not a significant handicap, as we can take advantage of a trick to obtain the same result, using only the invert and add operations. Consider the following subtraction:
35 17 18 00100011 00010001 00010010

The rules of arithmetic allow us to say that subtracting a number (such as 17) is the same as adding the corresponding negative number (in this case this would be 17). This allows us to rewrite the previous subtraction as:

35 +( 17) 18 In the previous section we have seen how to convert a positive number into its negative counterpart (using the twos complement notation), so we can rewrite the above subtraction as: 35 +( 17) 18 00100011 +11101111 00010010

Notice that this operation generates an extra carry which falls off the end. Remember that we are only dealing with eight-bit quantities here. If an operation like this generates an overflow, it is usually worth checking your work in this case looking at the base 10 version is sufficient to give us confidence that the sum has worked properly.

SQA Version 1

73

Developed by COLEG

Computer Architecture 1

DH2T 34

Step through the above calculation to make sure that you get the same result as me. As long as the numbers are within the range of the representation, this way of performing subtraction works for all values. As a second example, consider the subtraction: 17 22 39 This can be rewritten as: 17 +( 22) 39 11101111 +11101010 11011001

2.13

Complete the following question and check your answer with one at the back of the section. Use signed notation and addition only to perform the following subtraction: 22 43

SQA Version 1

74

Developed by COLEG

Computer Architecture 1

DH2T 34

Adding numbers in hexadecimal

The procedure for adding hexadecimal numbers is similar to that used for decimal, except a carry is generated when a total equals or is greater than 16. In decimal, we carry a 1 to the next column each time the total is greater than 9, so in hexadecimal addition, we carry a 1 to the next column each time the total is greater than 15.
Example in decimal

Add 597 and 873. Carry 1 1 1 597 +873 1470 The right-hand column (3 + 7 = 0 carry 1) Next column (7 + 9 plus 1 carried = 7 carry 1) Next column (8 + 5 plus 1 carried = 4 carry 1) Create a new column and place the carry into it to give 1. (10 - 10 = 0 carry 1) (17 - 10 = 7 carry 1) (14 10 = 4 carry 1) ( bolded 1s are carried bits )

Example in hexadecimal

Add 567 and ABC. Remember that A to F corresponds to 10 to 15 in decimal. Carry 1 1 1 5 67 +ABC 10 23 The right-hand column (12 + 7 = 3 carry 1) Next column (11 + 6 plus 1 carried = 2 carry 1) Next column (10 + 5 plus 1 carried = 0 carry 1) Create a new column, and place the carry into it to give 1.
1 1 1

5 6 7 10 11 12 1 0 2 3 (19 - 16 = 3 carry 1) (18 - 16 = 2 carry 1) (16 - 16 = 0 carry 1)

SQA Version 1

75

Developed by COLEG

Computer Architecture 1

DH2T 34

The following table shows the result of adding together any two hexadecimal digits:

SQA Version 1

76

Developed by COLEG

Computer Architecture 1

DH2T 34

Subtracting hexadecimal numbers

The procedure for subtracting hexadecimal numbers is similar to that used for decimal, except a borrow is required when the number on the bottom is greater than the number on the top. In decimal, we borrow 10 each time the number on the bottom is greater than the number on the top, so in hexadecimal subtraction, we borrow 16 each time the number on the bottom is greater than the number on the top. When we borrow however, the top number on the column to the left must be reduced by 1.

Example in decimal

Subtract 597 from 873.


76

873 597 276 The right-hand column (3 7 = 6 we borrow 10) (3 +10 7 = 6)

Since we did a borrow, the number on top of the next column is reduced by 1.

Next column (6 9 = 7 we borrow 10)

(6 + 10 9 = 7)

Since we did a borrow, the number on top of the next column is reduced by 1.

Next column (7 5 = 2)

(7 5 = 2)

Example in hexadecimal

Subtract 8CF from ABC. Remember that A to F corresponds to 10 to 15 in decimal. 9A ABC 8C F 1E D 9 10 10 11 12 8 12 15 1 14 13

SQA Version 1

77

Developed by COLEG

Computer Architecture 1

DH2T 34

The right-hand column (C F = D we borrow 16)

(12 +16 15 = 13)

Since we did a borrow, the number on top of the next column is reduced by 1.

Next column (A C = E we borrow 16)

(10 + 16 12 = 14)

Since we did a borrow, the number on top of the next column is reduced by 1.

Next column (9 8 = 1)

(9 8 = 1)

SQA Version 1

78

Developed by COLEG

Computer Architecture 1

DH2T 34

Congratulations on reaching the end of this rather long section. Now that you are confident on the topics covered, you should be in a position to attempt these tutor assignments.

2.1

Write out the truth table for the following diagram, and write down the equivalent logic expression for it. When you have completed this task, it will be ready to give to your tutor for marking.

A B

X C
A B C D X

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

..

2.2

A certain microprocessor has a data bus width of eight bits. What is the number of different data values that can be represented in one memory location of this machine? ..

SQA Version 1

79

Developed by COLEG

Computer Architecture 1

DH2T 34

2.3

A system displays using 24 bits per pixel. How much memory would be required if the screen resolution is set to 1152 * 864 pixels? ..

2.4

Convert the eight-bit signed value 1010

10102 into base 10.

.. Convert 3510 into a signed 8-bit binary value. .. Apply the logical NOT operator to the following binary numbers. 10101010 10001101 00110010 10000000

Now apply the logical AND operator to the following pairs of binary numbers. 11001100 11110110 00110011 00100111 11111111 11100001 10100001 01110100

Now apply the logical OR operator to the following pairs of binary numbers. 11001100
SQA Version 1

00110011

11111111
80

10100001
Developed by COLEG

Computer Architecture 1

DH2T 34

11110110

00100111

11100001

01110100

Now apply the logical XOR operator to the following pairs of binary numbers. 11001100 11110110 00110011 00100111 11111111 11100001 10100001 01110100

..

SQA Version 1

81

Developed by COLEG

Computer Architecture 1

DH2T 34

Summary of this section


This section dealt with a number of important concepts of how data is represented within a computer system, and some of the operations that can be performed on them. The topics were: the representation of characters within memory, especially ASCII negative numbers. conversions between bases NOT AND OR NAND NOR XOR binary addition binary subtraction (by using twos complement and add) hexadecimal addition hexadecimal subtraction.

The operations performed were:

SQA Version 1

82

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to SAQs
SAQ 2.1 a

(i) (ii) (iii)

C is character 6710. This is 100 00112. 2316 is 3510. This is character # (usually called hash). H is 7210, or 4816. C is character 004316. This is 0000 0000 0100 00112. 2316 is character #. H is 4816. 9 is 5710 and 1110012.

(i) (ii) (iii) (iv)

c d e f

The value of 9 in ASCII is HT (horizontal tab). Byte sequence for XYZ is 01011000 01011001 010110102. Byte sequence for xyz is 01111000 01111001 011110102. Byte sequence for 123 is 00110001 00110010 001100112.

SAQ 2.2

NOT 10101010 = 01010101 NOT 10001101 = 01110010 NOT 00110010 = 11001101 NOT 10000000 = 01111111
SAQ 2.3

11001100 11110110 AND 11000100

00110011 00100111 AND 00100011

11111111 11100001 AND 11100001

10100001 01110100 AND 00100000

11100 AND 10011= 10000 11100101 AND 10011010= 10000000


SAQ 2.4

11001100 11110110 11111110

00110011 00110111 00110111

11111111 11100001 11111111

10100001 01110100 11110101

SQA Version 1

83

Developed by COLEG

Computer Architecture 1

DH2T 34

SAQ 2.5

10110 10010 01101


SAQ 2.6

11010001 10010000 01101111

1000110001 0110010111 1111101110

10110 10010 01001


SAQ 2.7

11010001 10010000 00101110

1000110001 0110010111 0001001000

11001100 11110110 00111010


SAQ 2.8

00110011 00110111 00010100

11111111 11100001 00011110

10100001 01110100 11010101

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 1 1 1 1 1

0 0 0 1 0 1 0 1

This can be written as (A OR B) AND C, so X will be TRUE when C is TRUE AND either A OR B is TRUE. Remember that it is usually easier if you work out the intermediate values first.

SQA Version 1

84

Developed by COLEG

Computer Architecture 1

DH2T 34

SAQ 2.9

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

The output is only TRUE when all four inputs are TRUE, so ((A AND B) AND (C AND D)) is another way of writing this.

SQA Version 1

85

Developed by COLEG

Computer Architecture 1

DH2T 34

SAQ 2.10 Number of bits Number of patterns

1 2 3 4 5 6 7 8 9 10

2 4 8 16 32 64 128 256 512 1024

SAQ 2.11

1 1*-128

0 0*64

0 0*32

1 1*16

0 0*8

1 1*4

1 1*2

0 0*1

128 +16 +4 +2 106

SQA Version 1

86

Developed by COLEG

Computer Architecture 1

DH2T 34

SAQ 2.12

Step 1: 7710 is 0100 11012. Step 2: invert to give 1011 00102. Step 3: add 1 to give 1011 00112. Checking:

128 +32 +16 +2 +1 77


SAQ 2.13

Step 1: convert 2210 to binary 0001 01102. Step 2: convert -4310 to binary 0010 10112. Step 3: invert to get 1101 01002 (ones complement). Step 4: add one to get 1101 01012 (twos complement). Add:

000101102 000101102 111010112


Check:

22 43 21

1110 1011, invert to give 0001 0100, add one to give 0001 0101. This is 21, so 1110 1011 is 21.

SQA Version 1

87

Developed by COLEG

Computer Architecture 1

DH2T 34

Answer to activity
Response to activity 2.1 NOT A X

1 0
AND A

0 1

0 0 1 1
OR A

0 1 0 1

0 0 0 1

0 0 1 1
NAND A

0 1 0 1

0 1 1 1

0 0 1 1

0 1 0 1

1 1 1 0

SQA Version 1

88

Developed by COLEG

Computer Architecture 1

DH2T 34

NOR
A B X

0 0 1 1

0 1 0 1

1 0 0 0

XOR
A B X

0 0 1 1

0 1 0 1

0 1 1 0

SQA Version 1

89

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

90

Developed by COLEG

Computer Architecture 1

DH2T 34

Section 3: Memory

SQA Version 1

91

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

92

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction to this section


What this section is about

The main topics in this section are types of memory. It is intended as a first introduction to the workings of the CPU and should be completed before Section 4. The only practical work in this section is in using the internet so you should be able to complete the section at home before sending the tutor assignment to your tutor.
Outcomes, aims and objectives

The intention of this section is to introduce you to the types of memory used in a computer system and how different devices may use memory. You will also learn how to interpret graphical/tabular information. The objectives of this section are to: identify the different types of memory that can be attached to a processor describe the types of memory in terms of cost, speed and usage interpret graphical/tabular information.

Approximate study time

6 hours.
Other resources required

Use of the internet. Access to current computer magazines. Use of a calculator.

SQA Version 1

93

Developed by COLEG

Computer Architecture 1

DH2T 34

Assessment information for this section


How you will be assessed

This section forms part of Outcome two. The other part of this outcome is in Section 4. There is a tutor assignment at the end of this section for your guidance. You will do the summative assessment after you have completed Section 4.
When and where you will be assessed

The assessment at the end of Section 4 will be in the form of an in-class assessment. This will be an open book assessment so you will be able to use your notes. This is a formal assessment and it will be held at your centre. If you think that this may be a problem then ask your tutor for advice.
What you have to achieve

The summative assessment takes the form of a list of tasks. It is necessary to complete all tasks satisfactorily but it is not necessary to achieve 100% in each task to do this.
Opportunities for reassessment

There will be one opportunity for reassessment of this section and Section 4.

SQA Version 1

94

Developed by COLEG

Computer Architecture 1

DH2T 34

Memory
There are a number of ways that programs and data can be held in a computer system. Floppy disk, hard disk, CD-Rom and DVD are types of long-term storage. These hold programs and data that are available for use, but are not currently in use. Memory is where the computer holds programs and data while they are in use. Long-term storage can be compared with a filing cabinet full of files. There may be an unlimited number of files and they may only be used infrequently. Memory is like a desk. When the computer needs to do a piece of work it will take one or more files out of the cabinet and open them onto the desk. When the work is finished the desk is cleared. Anything written on the notepad on the desk is either filed away or torn up. If there are too many open files on the desk and not enough working space, the work is carried out less efficiently.
Access time is the time it takes to locate, from memory, a single piece of data and make it available for processing. Dynamic RAM (DRAM), which is described later, has an access time of about 5070 nanoseconds and static RAM (SRAM) has an access time of about 1530 nanoseconds. Cycle time is a more important measurement of a memory chips speed. This is a measurement of how quickly two back-to-back accesses can be made, i.e. the time taken between the start of one RAM access to the time when the next access can begin. A DRAM chip's cycle time is usually longer than its access time, which measures only a single access. This is because there is time lost in the refreshing process between successive memory accesses owing to latency, time taken to find the right location for the memory access, and time taken to transfer bits.

When the processor runs a program, it is first loaded into memory along with data files. There are two principal types of memory: read only memory (ROM) and random access memory (RAM). Both of these use random access rather than serial access, meaning that all access operations should take the same length of time regardless of where in memory the data is stored. However, the uses of ROM and RAM are quite different.

SQA Version 1

95

Developed by COLEG

Computer Architecture 1

DH2T 34

RAM

RAM is a grid of cells that can hold data and program instructions. Typically the RAM will have part of the operating system permanently in place while it is switched on. When a user opens a word processing package, the required part of the package is copied from the hard disk into RAM and remains there until the user closes the package. When the user creates a data file, the data is stored in RAM until saved to disk or discarded. The contents of RAM are always lost when the computer is switched off, making it necessary to save any data files to backing store. RAM is inexpensive. Below is an example of the contents of RAM memory.
Memory address Memory content

Binary 000 001 010 011 100 101 110 111

Decimal 0 1 2 3 4 5 6 7 11100111 11000011 10000001 00111100 10001111 01100011 10110011 00001111

There are two forms of RAM used in most computer systems.


DRAM

Dynamic RAM is the less expensive of the two. It comprises a grid of cells and the memory address identifies the row and the column separately. DRAM stores information in arrays of tiny capacitors, each of which can be charged or discharged. DRAM allows the processor to access any part of the memory directly (random access rather than sequential access). The charge in a DRAM cell is not fixed; it starts to leak away as soon as the cell has received its charge. To maintain the charge on the cells, all the cells are refreshed (recharged) on a continual basis, many times per second. This refreshing process takes processor time and DRAM is therefore not the fastest form of RAM. It is, however, fast enough and economically this is the preferred type of RAM for main memory in most systems.

SQA Version 1

96

Developed by COLEG

Computer Architecture 1

DH2T 34

SRAM

Static RAM, which does not need to be refreshed constantly, is more expensive than DRAM but significantly faster. SRAM stores information as patterns of transistor ons and offs to represent binary digits. Typically a computer will use SRAM for cache memory. This is memory that lies between the processor and main memory. Blocks of memory are copied into cache according to the most recently used areas of memory. When the processor does a fetch from memory, it looks first in the cache memory for the address it needs. If the address is not in cache then it will go to main memory. That means that for any data not in cache, the processor does two searches, one in cache and one in main memory. However, the speed advantage of the cache makes this worthwhile in terms of processor speed.

3.1

Complete the following question and check your answers with those given at the end of the section. What are the principal differences between SRAM and DRAM? .. .. .. If you have anything wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. Now you should spend some time researching current data about SRAM and DRAM.

SQA Version 1

97

Developed by COLEG

Computer Architecture 1

DH2T 34

ROM

ROM is not volatile; its contents are not lost when the machine is switched off. This type of memory is used to hold information that is not expected to change during the lifetime of the computer. A device like a calculator or a video recorder has all of its programming on a ROM chip. ROM holds the power on self test (POST) basic input output system (BIOS), part of the operating system and the basic machine control programs. When the computer is switched on the BIOS instructions are immediately executed. This identifies the peripheral devices, keyboard, mouse, etc. and then loads part of the operating system into RAM. At that point the operating system assumes control of the computer. The system ROM enables the computer to pull itself up by its bootstraps or otherwise known as boot up the computer by performing basic checks and starting the operating system and storing the relevant data into RAM. The programming of a ROM chip is an integral part of the manufacturing process. They are manufactured in layers using specifically designed masks. ROM chips are produced on a large scale and then passed on to the computer manufacturer. This makes the production cost relatively low. The speed of ROM is slow.
Programmable ROM (PROM)

PROM is used to allow the computer manufacturers to add their own instructions to the ROM chip. PROM uses a different method of programming the chip that makes it possible for the computer company to add programming after the initial production process. This allows the chip manufacturer to have large-scale production runs of generic chips that can then be programmed by other companies for use in calculators, games or toys. This programming technique involves blowing the fuses in selected cells and is irreversible.
Erasable PROM (EPROM)

For the purpose of research and development it is useful for the computer company to be able to program a ROM, test it, and then make changes to the programming. To enable this it is possible to use ultraviolet light to repair the blown fuses and reprogram the chip. This is a slow process, not suitable for personal use. The EPROM chip has a transparent window in it to enable the ultraviolet light to penetrate. This type of chip is expensive and only suitable for testing purposes.
Flash memory (EEPROM)

This is a special type of electrical EPROM that can be erased and reprogrammed in blocks at time. Many PCs have their BIOS stored on a flash memory chip so it can be easily updated without specialist equipment. It is also used as a backing store in devices like the digital camera and many students carry it around as a memory stick. It is smaller and faster than the hard disk equivalent, however it is much more expensive per unit of storage.

SQA Version 1

98

Developed by COLEG

Computer Architecture 1

DH2T 34

3.2

Complete the following questions and check your answers with those given at the back of the section. What are the principal differences between PROM and electrical EPROM? .. .. .. If you have anything wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

3.1

Interpret graphical information


The processing efficiency number (in cycles/FLOP) tells you how many processor cycles are used to calculate one floating point operation, or FLOP. The lower this number, the more efficient is your processor. Below is a table which shows the cache size and efficiency of different processors and on the next page is the same information in graph form.
Processor AMD Athlon 64 FX Intel Pentium III Xeon Intel Pentium III Xeon Sun UltraSPARC-II Intel Pentium Pro Intel Celeron Sun UltraSPARC-IIi MIPS R5000 PowerPC G4 Sun UltraSPARC-IIe Intel Celeron Dual Intel Pentium PowerPC G3 Intel 486DX Cache size (kB) 1024 2048 1024 4096 256 128 256 512 1024 256 128 512 512 256 Processing efficiency 3.5 3.6 3.8 4.5 5.0 5.5 5.9 6 6 6.3 6.6 7.1 7.6 21.3

SQA Version 1

99

Developed by COLEG

AM

Cache size (kB)


AM

D
4500 4000 3500 3000 2500 2000 1500 1000 500 0

Efficiency (FLOPs)
10 15 20 25 0 5

SQA Version 1

Computer Architecture 1

Efficiency

Processor Type

Size of cache

Processor Type

100

At In hl te on lP en 64 In t iu FX te m lP III en X t Su ium eon n III Ul tra Xeo SP n In te l P AR C en tiu -II m Pr Su Inte lC o n Ul el tra e SP ro n AR M CIP II i S R 50 Po Su 00 we n rP Ul C tra G SP 4 In AR te lC Cel I Ie er on In D te ua lP l en Po t iu m we rP C In G te 3 l4 86 DX

D At In hl te o lP en n 64 In t iu FX te m lP III en X t Su ium eon n III Ul tra Xe SP on In te l P AR C en tiu -II m Pr Su Inte lC o n Ul el tra e SP ro n AR M CIP IIi S R 50 Po Su 00 w n Ul e rP C tra G SP 4 In AR te lC Cel IIe er on In D te l P ual e Po ntiu m we rP C In G te 3 l4 86 DX

DH2T 34

Developed by COLEG

Computer Architecture 1

DH2T 34

From the table or the efficiency graph, list all the processors where the processing efficiency is less than 5. 1)____________________________ 3)____________________________ 2)____________________________ 4)____________________________

Again, from the table or the size of cache graph, list all the processors where the cache is greater than 1500 kB. 1)____________________________ 2)____________________________

SQA Version 1

101

Developed by COLEG

Computer Architecture 1

DH2T 34

T
1

Explain what each of these types of memory is used for. SRAM .. .. .. .. DRAM .. .. .. .. PROM .. .. .. .. EPROM .. .. .. .. ROM .. .. .. .. RAM .. ..

SQA Version 1

102

Developed by COLEG

Computer Architecture 1

DH2T 34

.. .. 2 For each of these types of memory describe their comparative speeds. .. .. .. .. .. .. 3 What would a private user be able to do with flash memory that would not be possible with ROM? .. .. .. .. ..

SQA Version 1

103

Developed by COLEG

Computer Architecture 1

DH2T 34

Summary of this section


By this stage you have learned about different types of computer memory. You should be able to describe them in terms of their speed, and typical usage. You should also be able to interpret graphs.

SQA Version 1

104

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to SAQs
SAQ 3.1

DRAM must be refreshed constantly to maintain charge; SRAM doesnt require this. DRAM is cheaper than SRAM. DRAM is not as fast as SRAM. DRAM is generally used for main memory while SRAM is generally used for cache.
SAQ 3.2

PROM cannot be reprogrammed, EEPROM can be reprogrammed electrically. EEPROM is generally available in current systems for individual users. PROM is used generally by manufacturers as part of the production process for a computer

SQA Version 1

105

Developed by COLEG

Computer Architecture 1

DH2T 34

Answer to activity
Responses to activity 3.1.
1) AMD Athlon 64 FX 3) Intel Pentium III Xeon 2) Intel Pentium III Xeon 4)Sun UltraSPARC-II

1) Intel Pentium III Xeon

2) Sun UltraSPARC-II

SQA Version 1

106

Developed by COLEG

Computer Architecture 1

DH2T 34

Section 4: Communication between the processor and peripherals

SQA Version 1

107

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

108

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction to this section


What this section is about

This section will introduce you to the functional components of a computer system. You will then examine the way in which the processor is physically connected to memory and to the input/output devices using the system buses. The section will then discuss the ways in which data is transferred between the processor and peripheral drives, where polling and interrupt techniques will be examined. Finally, the section will conclude with an examination of the use of direct memory access (DMA) in computer systems and how it affects performance. The only practical work in this section is in using the internet for some of the activities, so you should be able to complete this section at home before sending the tutor assignment to your tutor.
Outcomes, aims and objectives

The aim of this section is to introduce you to computer system components and the ways they communicate internally, and with peripheral components.
Approximate study time

8 hours.
Other resources required

Use of the internet.

SQA Version 1

109

Developed by COLEG

Computer Architecture 1

DH2T 34

Assessment information for this section


How you will be assessed

This section forms part of Outcome 2. Section 3 forms the other part of this outcome. There are tutor assignments at the end of this section for your guidance. After you have received feedback from these assignments you will be ready to complete the summative assessment for Outcome 2.
When and where you will be assessed

The summative assessment for Outcome 2 will be in the form of an in-class assessment. This will be an open book assessment so you will be able to use your notes. This is a formal assessment and it will be held in college, but if you are likely to have a problem in attending college then ask your tutor for advice.
What you have to achieve

The summative assessment takes the form of a list of tasks. It is necessary to complete all of the tasks satisfactorily, but it is not necessary to achieve 100% in each task to do this.
Opportunities for reassessment

There will be one opportunity for reassessment of Outcome 2.

SQA Version 1

110

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction
Section 3 introduced the concept of memory that could store information which could subsequently be used by the computer. The information that can be used by the computer is either: 1 2 programs that are stored in memory, or data that is stored in memory.

The memory store can be the computers main RAM memory or the system ROM (e.g. the BIOS chip). Programs cannot be run straight from disk; they must be loaded into the computers memory and run from there. Similarly, all data, whether incoming or outgoing, will have to reside in memory at some stage. The CPU is the heart of any computer system; it is responsible for the constant reading of instructions from the programs residing in memory. The instructions will be fetched from memory, interpreted and executed, which usually results in the manipulation of data. This process is called the fetch-execute cycle and will be discussed fully in Section 5. Prior to the study of Section 5, it is important to know the main components of the CPU and how they communicate with other devices.

SQA Version 1

111

Developed by COLEG

Computer Architecture 1

DH2T 34

Main components of a computer system

MAIN MEMORY

INPUT DEVICES

PROCESSOR

OUTPUT DEVICES

AUXILIARY STORAGE Major components of a computer

CPU Main memory (RAM and ROM) Peripherals (devices and interfaces)

Each of these major components can be broken down into main components.
Main components of the main memory

RAM ROM

Main components of the peripherals

Devices (keyboard, mouse, printer, etc.) Interfaces

Main components of the CPU

The main components are the: Registers (general purpose registers and special purpose registers) Arithmetic and logic unit Control unit Clock

SQA Version 1

112

Developed by COLEG

Computer Architecture 1

DH2T 34

In a microcomputer, the control unit (CU) and arithmetic and logic unit (ALU) are both contained on a single chip called a microprocessor.
CPU Registers ALU CU Clock

Registers

The CPU has small areas of storage known as registers. These are similar in composition to main memory cells. There are two types of registers: general purpose and special purpose.
General purpose registers

General purpose registers are those which are under the control of the programmer or the system software. Different architectures will have different numbers of these types of registers, each with different names and of different sizes.
Special purpose registers

Special purpose registers, as the name suggests, are used for a specific purpose. These are working registers used only by the CPU during the fetch-execute cycle. They are: 1 Memory address register (MAR). This is used to hold the memory address of the data or instruction currently being accessed. It will also be used to hold the address in memory where data should be written to after processing has taken place. Memory data register (MDR), sometimes referred to as a data buffer (DB). This is used to hold data read from main memory or data to be written to main memory. All transfers (both data and instructions) between memory and the processor must pass through the memory data register. Instruction register (IR). This holds the instructions currently being executed. This will be used to hold the current instruction, i.e. the instruction that has just been fetched from memory and has been moved from the MDR to the IR.

SQA Version 1

113

Developed by COLEG

Computer Architecture 1

DH2T 34

Program counter (PC), also called the instruction pointer (IP).The PC determines the sequence in which program instructions are to be executed. It will hold either the address of the instruction currently being executed, or the address of the next instruction to be executed. In most processors, the PC is incremented immediately after fetching a program instruction. The PC is initially loaded with the address of the first instruction of the program, then for each instruction cycle, it is automatically incremented by 1 to point to the address of the next instruction in contiguous memory. If the program instruction invokes a jump or branch, which interrupts the sequence, then the contents of the PC are overwritten with the appropriate address.

Arithmetic and logic unit (ALU)

The ALU is the part of the CPU where all the arithmetical operations such as addition, subtraction, multiplication and division, and logical operations such as AND, OR and NOT are performed. These are carried out at enormously high speeds. The results of these operations are placed in a general purpose register called the accumulator (AX).
Control unit (CU)

The CU coordinates the operation of the processor by providing control signals. It acts under the direction of the clock and manages all the internal paths inside the processor to ensure that data gets from the right location and goes to the right place using the internal bus on the CPU, which essentially connects all the necessary components. It is responsible for the operations required to fetch the instructions to be executed from main memory, decoding them and for the execution of the instructions. The CU is the nerve centre of the processor. The CPU can be thought of as being made up of a number of component parts as illustrated below:
CPU General Purpose Registers ALU PC IR MAR MDR Control Unit Main memory

All communication between the CPU and main memory are via the MAR and MDR.

SQA Version 1

114

Developed by COLEG

Computer Architecture 1

DH2T 34

CPU in operation
Lets look at the following section of memory.
Memory Meaning

Memory location 98 99

Contents LDA 23 Load the accumulator with the contents of the next memory location. Number 23.

Following this small program through: 1 The PC would be initialised to 99. PC 98 2 The contents of the PC are passed to the MAR. PC 98 3 MAR 98

The instruction (LDA) is read from memory and placed in the MDR. PC 98 MAR 98 MDR LDA

The PC is incremented by 1. PC 99 MAR 98 MDR LDA

The instruction is passed from the MDR to the IR. PC 99 MAR 98 MDR LDA IR LDA

The contents of the PC are passed to the MAR. PC 99 MAR 99 MDR LDA IR LDA

The data (number 23) is read from memory and placed in the MDR. PC 99 MAR 99 MDR 23 IR LDA

The PC is incremented by 1. PC 100 MAR 99 MDR 23 IR LDA

The contents of the MDR are placed in the AX. PC 100 MAR 99 MDR 23 IR LDA Ax 23

As you can see, its quite a lengthy process but thankfully the computer does it a lot faster!

SQA Version 1

115

Developed by COLEG

Computer Architecture 1

DH2T 34

The instruction used above needed two memory locations and it is an example of immediate addressing. Youll learn more about different types of addressing in Section 5. In summarising the fetch-execute scenario previously described, the contents of the registers would be as follows:
CPU General Purpose Registers AX 23

ALU PC 100 IR LDA MAR 99 MDR 23 CU Main memory LDA 23 98 99

Note: the contents of the registers would contain their binary equivalents.

SQA Version 1

116

Developed by COLEG

Computer Architecture 1

DH2T 34

4.1

Complete the following question and check your answer with that given at the end of the section. If the following lines were added to the program, what would the final registers read?
Memory Meaning

Memory location 100 101

Contents ADD 7 Add the contents of the next memory location to the contents of the accumulator. Number 7.

.. .. .. .. .. .. .. .. .. .. .. .. If you have anything wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor. The fetchexecute cycle will be explored more fully in Section 5.

SQA Version 1

117

Developed by COLEG

Computer Architecture 1

DH2T 34

Interconnection methods
The various components of the computer are interlinked by means of one or more buses. A bus connects different parts of the computer, including the processor, memory and a range of input/output (I/O) devices such as disks, keyboards, monitor and mouse, allowing the transfer of data between them. A number of features concerning buses can be identified: A bus is a group of paths, one for each bit of a word, along which data can flow (as electrical signals). A computer will usually have several buses used for specific purposes. The width of a bus determines the length of word which can be handled at one time. For example, a processor that uses a 32-bit bus but requires a 64-bit word to address memory would have to concatenate two 32-bit words in two separate fetch operations to access the memory location. control signals, address signals and data signals. 1 Control bus a control bus carries the signals concerning the timing of various operations such as memory read (MEMR), memory write (MEMW) and I/O device read (IOR)and I/O device write (IOW). The PCs main control lines are: MEMR goes low to indicate a read of memory MEMW goes low to indicate a write of memory IOR goes low to indicate a read of an I/O device IOW goes low to indicate a write of an I/O device 2 Address bus this carries the address of the location for the required data. This is one way only and is used to tell the main memory which address is to be used. Devices such as parallel and serial ports are also part of this addressing system. The size of the address bus affects the amount of main memory or I/O devices offered. If there were 8 lines available then the maximum number of different addresses would be 28 = 256. Data bus this is for the transfer of data subject to processing or manipulation in the processor. This is two way since data can travel into and out from the memory to the processor and I/O devices. Typically the data bus will be the same size as one memory location. Information never flows into the processor from the address bus. The address bus is only used to allow the CPU access to main memory and various peripheral chips, i.e. the address bus is one way (unidirectional). Since ROM is read only, data only flows on to the data bus from the ROM chip.

Three types of signals are generally carried on buses:

Notes:

SQA Version 1

118

Developed by COLEG

Computer Architecture 1

DH2T 34

Since RAM can be either read or written, there is a need to allow data to flow between memory and the CPU (but only in one direction at a time), i.e. the data bus can transfer data in both directions (bidirectional), outwards for a write operation and inwards for a read operation. The I/O expansion bus is an extension of the main computer bus that includes expansion slots for use by compatible adapters, such as including memory boards, video adapters, hard disk controllers, and SCSI interface cards. The I/O expansion bus also has to be capable of both receiving and transmitting data on to the data bus (e.g. a modem has to transfer data in both directions).

The interconnections between the CPU and memory and I/O devices are shown in the diagram below.

CPU General Purpose Registers ALU PC IR I/O Devices, e.g. disks, keyboard, monitor, mouse Address MAR Data MDR Control CU Bus Bus Bus Memory

SQA Version 1

119

Developed by COLEG

Computer Architecture 1

DH2T 34

Initiating the read/write operation

Typically, the memory of even a small computer will comprise many devices. Each chip will correspond to a range of locations in the memory map. This means that some system must be provided to indicate which chip is currently required by the system. The system usually adopted uses a feature of the chips called chip select, an extra line provided on the chip which is used to indicate if the chip is required for the current operation. The signal for chip select can be generated from a combination of control bus and address bus signals. These signals are fed through logic gates to provide the chip select signal. Consider a very simple system with the following map: ROM 0 255 RAM 511

As each of the devices has only 256 addresses we need eight address lines within each device, but some way of deciding whether we want to select the ROM or RAM device. Assuming for the moment that for the chip select signal to be active it is at logic 1, we can adopt the following type of arrangement:

Address line A8

CPU

Invert (NOT) gate

Address bus A0 to A7

CS ROM

Address bus A0 to A7

CS RAM

If the ninth address line (A8) is at 0, then the invert gate will change this to a 1, and the ROM device will have 1 at its chip select (CS) pin. Under the same condition, the CS line of the RAM device will be at 0. This means that the ROM device will be active, and the RAM device will not be active. If, however, the address line A8 is at 1, then the inverter will change this to a 0 and the ROM device will not be active, but the CS of the RAM device will be 1 and therefore active. This means that if we select an address in the range 0255, then the ROM on the system will be active. Conversely, if we select an address in the range 256511 the RAM device will be active.

SQA Version 1

120

Developed by COLEG

Computer Architecture 1

DH2T 34

Realistic systems will combine more than one address line with control bus signals to select between multiple chips. Note that systems that provide separate I/O space will use the I/O pin on the processor to indicate whether memory or I/O is required. This signal is part of the control bus. The following steps detail the process involved when the processor is required to write to a specified memory location. 1 2 3 4 5 6 7 Processor puts the required address on the address bus. Any addresses that invoke chip select lines are decoded. Chip select is generated. Wait for memory access time. Processor puts data on the data bus. Processor generates memory write control bit. The contents are written to memory.

4.2

Complete the following question and check your answer with the one given at the back of the section. Outline the steps required for a memory read. .. .. .. .. .. .. If you have anything wrong, look back over the topic then try again. If youre still not sure, then check with your tutor.

SQA Version 1

121

Developed by COLEG

Computer Architecture 1

DH2T 34

Input/output devices
We have looked at how the processor transfers data between its internal components the CPU and memory. Now we will examine how it deals with transfers to external or peripheral devices, such as visual display units (VDUs), disks and tape units.
The input/output bus and the input/output interface

The term input/output, or more usually I/O, is taken to include communication between the CPU and devices other than main memory, such as disks, tape units, keyboards, VDUs, printers and other devices that communicate with the outside world. Since a number of these peripheral devices are usually connected to a computer, there has to be some means by which only one of these devices can be selected to perform some input or output task. This can be achieved through the use of an input/output bus the I/O bus. I/O peripheral interfaces are different functional units of an information processing system that are used to communicate with each other. Inputs are the signals received by the unit, and outputs are the signals sent from it. Typical types of I/O peripheral interfaces are the parallel interface and serial interface. A serial interface is a link between data processing devices on which all the data moves over one wire, one bit at a time. Think of it as transmitting words one letter at a time until a total of eight letters or bytes (eight bits) has been received. The byte is then processed by the processor. A parallel interface is a protocol for transmitting data whereby all bits in a word (typically two or more bytes) are sent simultaneously. This method is generally more expensive to implement than serial protocols as the connectors and cable must have a wire for each bit. Connected to the wires which form the bus are registers in the peripheral device interface. However, unlike registers in the CPU, which are completely under the control of the CPU, those in the peripheral device act in an autonomous way. The CPU initiates their actions, but does not subsequently have any control over their operation. A bus to which I/O devices are connected consists of three sets of lines used for the transmission of address, data and control signals. When the CPU wishes to send data to a particular I/O device, it places a unique identity code, or address, onto the address line. Only the device that recognises that code will respond to the command that is placed on the control line. The following diagram shows a typical structure of a computer system with a single I/O bus.

SQA Version 1

122

Developed by COLEG

Computer Architecture 1

DH2T 34

CPU General Purpose Registers ALU


I/O interface

PC I/O bus Address MAR Data MDR Control CU Bus IR Bus Memory Bus

Device

In the system above, reading data from a peripheral device and storing it in memory is a three-stage process (output being in reverse): 1 2 3 Device I/O interface Register I/O interface register memory

A device is attached by cable to an I/O interface. The interface is plugged into one of a number of I/O slots, each of which is assigned a fixed address. There are two ways in which computers can be designated to address I/O devices. One is called memory mapping, the other way is called dedicated I/O. In memory-mapped I/O, all devices have addresses that are virtually indistinguishable from ordinary memory addresses. In other words, in the address range allowable on the bus, some addresses will be memory cells and others will be I/O devices, but the method of addressing is exactly the same. Computers that use dedicated I/O have particular instructions that are reserved especially for performing I/O. When such an instruction is used, the computer will produce signals on the bus which indicate that the transaction is an I/O transaction and not a memory transaction.

SQA Version 1

I/O interface

Device

I/O interface

Device

123

Developed by COLEG

Computer Architecture 1

DH2T 34

The interface is the communication link; all data passing into or out of the system must do so through the I/O interface port, which is the logical channel, or channel endpoint in an I/O communication system. This port has eight external inputs d0d7 that connect directly to the buffer chip. It includes three basic elements: 1 2 3 A control bit this is a one-bit register (flip-flop) which when turned on generates a start command to the device to start its I/O. A flag bit this is set on by the device when transmission between the device and its interface is complete. It can be tested or cleared under program control. A buffer register this is the register in which the data that has been read, or which is to be written, is stored.

When a start command is generated, one character is transferred between the interface buffer register and the device, or vice versa. The following steps detail the process involved when the processor is required to read from an I/O port. 1 2 3 4 5 6 7 8 Processor puts required address on to the address bus. Processor activates I/O line. Any address lines that invoke chip select lines are decoded. Chip select is generated. Wait for I/O access time. Processor selects I/O read control bit (IOR) Peripheral puts data on data bus. Processor reads data from data bus.

Peripheral management
Polling

Before interrupts were used as a mechanism for I/O, CPUs used to have to poll an I/O device to check its status. With this technique a CPU can check if a peripheral device is ready to send or receive data. Each device is checked or polled in turn to determine if that device needs service. The device must wait until it is polled in order to send or receive data. This method is useful if the device's data can wait for a period of time before being processed, since each device must wait its turn in the polling scheme before the processor will service it. The process is repeated continuously. Using this technique, however, a lot of time is wasted while each device is interrogated to check if it needs any processor time. For example, you might be printing to the printer and waiting until the print job is complete. To poll an I/O device, the CPU typically uses memory-mapped I/O. I/O devices are assigned memory addresses which aren't used by memory at all but are, instead, special addresses that the I/O device recognises. (Memory mapped I/O is usually done when the CPU is started up.) The CPU can then check the status of the device by reading a byte or word at some predetermined address for that particular I/O device.

SQA Version 1

124

Developed by COLEG

Computer Architecture 1

DH2T 34

Problems with polling

The problem with polling is that the CPU operates at a much faster speed than most I/O devices. Thus a CPU can get into a busy wait, checking the device many times even though the device is very slow. Occasionally, polling is the right thing to do, especially if devices are quick enough. The main advantage of polling is that the CPU determines how often it needs to poll. An interrupt causes the CPU to stop and determine what device is interrupting. Thus, if the CPU can be late handling the device, then polling prevents the CPU from being interrupted. A more efficient technique is the use of interrupts, where the device interrupts the CPU when it requires attention.
Interrupts

During the execution of a program by a computer, many situations can arise which require prompt attention, either to utilise the whole computer system efficiently or to prevent a serious mishap occurring. In order to ensure that such situations are dealt with as quickly as necessary, the execution of the current program is interrupted. The computer is then able to execute a program which determines the cause of the interrupt and deals with it accordingly. After this interruption has been dealt with, the original program can be resumed at the point of interruption, unless the situation that caused the interruption was a CPU error or a programming error. The processor can be interrupted at any point by outside events, such as: those generated by the computers own hardware those generated inside the CPU in response to unexpected conditions (e.g. divide by zero error) those generated by input/output devices (e.g. transfer to slow printer devices) those deliberately embedded inside the software program so that it can gain access to external routines in the ROM (e.g. BIOS routines).

Interrupt handling

Suppose the CPU is running a program when it receives a request from, say, a peripheral to interrupt its processing and deal with the peripheral. This will involve transferring control to a second program which will deal with the peripheral. The second program is often called an interrupt service routine. On completion of the interrupt service routine, control will have to transfer back to the original program at the point at which it was interrupted in order for it to continue. In order for the CPU to be in the same state after an interrupt has been serviced as it was before, it is necessary for it to preserve the state of all the components of the CPU when the interrupt occurs. The CPU consists essentially of a series of registers and lines containing control signals. When an interrupt occurs, the CPU finishes executing the current instruction before it accepts the interrupt. It is then merely necessary for the interrupt service routine to store the appropriate registers immediately it is given control and to reset the registers back to these values immediately before giving control back to the original program. In an IBM PC, 256 different routines are available for interrupts and each routine has its own interrupt number, from interrupt 0 up to interrupt 255.
SQA Version 1 125 Developed by COLEG

Computer Architecture 1

DH2T 34

When one of the interrupts occurs, the processor looks in memory for the required interrupt service routine (ISR). Many of the ISRs are stored in ROM. When an interrupt is received, the process of events is as follows. The contents of internal registers are stored in an area of memory called the stack. The address of the ISR is found. The processor will jump to this service routine and process it. The internal registers will be reloaded from the stack. Processing will continue from where it was stopped.

Finally, when two or more devices require service at the same time, then a priority order has to be established. If polling is used then the priority is simple: the order in which the devices are polled. The first device requiring service that the CPU comes to will be dealt with. Interrupts can be prioritised in hardware by examining the priorities of the interrupt. If an interrupt arrives while the processor is already dealing with one, it can do one of two things. If the second interrupt is of a lower priority then the processor will carry on until the current interrupt has been serviced. If the new interrupt is of a higher priority then the processor will store its current state on the stack and start to process the newer interrupt. When that one is finished, it will complete the processing of the first interrupt and then revert to the original process. This is known as nested interrupts.

Generally, the processor can mask or delay the servicing of interrupts until it is ready, but there is a group of interrupts that cannot be ignored. These are known as nonmaskable interrupts (NMIs) and they indicate a serious problem such as loss of power requiring the computer to shut down immediately. Consider two different scenarios in a programming class of 20 students. In the first case, the lecturer goes round each student in turn (polling), checking to see if they need any help. If the lecturer spends on average three minutes with each person then it will be almost an hour before the last student has been attended to. But everyone gets a chance to talk to the lecturer. In the second case, the lecturer waits until someone calls for help (interrupt), and then goes to help them. It could be the case that someone shouts louder and more frequently than the others, therefore taking up much more of the lecturers time. What happens when two or more students call for attention at the same time or when the lecturer is working with one student and others call for attention?

SQA Version 1

126

Developed by COLEG

Computer Architecture 1

DH2T 34

Speeding up the processor


So far it has been assumed that each new instruction has been fetched from memory after the previous instruction has been fully executed. We will now examine two methods for improving the efficiency of the processor.
Cache memory

Standard memory speeds have not progressed at the same rate as processor speeds. As a result, the CPU can process data faster than the data can be fetched from memory or placed in memory. If it can be arranged that, at any given time, the active segments of a program are in a faster memory then the execution time will be reduced. This is achieved by using a faster memory known as cache or buffer memory, placed between the CPU and the main memory.

CPU

Cache memory (level 2)

Main memory

The cache memory is likely to be faster memory (SRAM), and will have an access time much faster than the main memory, which is likely to be DRAM. SRAM and DRAM were discussed in Section 3. Many computers also have a cache memory actually on the CPU, and this is known as Level 1 cache memory. Any data held in the cache memory can be transferred to the CPU at greater speeds owing to its faster access times at between 2 ns and 10 ns. Consider what happens when the CPU handles a READ request. When the control unit makes a READ request, the memory access circuitry will check first of all to see if the required word is in the cache memory. If it is, it will be accessed from the cache memory and the main memory will not be involved. If the required word is not in the cache memory, then the required word will be accessed from the main memory. In addition to this, a block of memory words containing the specified location will be moved from the main memory to the cache. The cache memory is capable of storing several blocks of memory words, and a mapping function will determine where in the cache a particular block of memory words will be stored. The aim is to try to ensure that the data most likely to be required next is stored in cache memory. This means that the CPU can access memory without the need for wait states. The result of using cache memory is with a reduction of wasted CPU time and an increase in computer efficiency.

SQA Version 1

127

Developed by COLEG

Computer Architecture 1

DH2T 34

Cache organisation

We have looked so far at how data is read from main memory to cache then to CPU. Of course, data that is written to cache also has to be reflected in changes to main memory. Different methods for reading and writing cache exist, and predictably the faster the method then the more costly the product. Read methods:
Look through the CPU requests data from the cache. If it is not in the cache, the CPU requests the data from the main memory. Although there is a slight loss of time in reading twice, the overall time saving in using cache is quite significant. Look aside the CPU interrogates the cache memory and the main memory at the same time. If the data is in the cache memory, it is transferred at the faster rate; otherwise it is fetched more slowly via main memory. Write through cache when cache is updated, main memory is updated at the same time. Write back similar to write through method except the main memory is only updated if there is a difference in the contents of the cache.

Write methods:

Direct memory access (DMA)

DMA is the name given to a method by which blocks of data can be sent from memory to a device and vice versa without detailed attention by the CPU. This relieves the CPU of the burden of handling numerous interrupts during the transfer of a block of data from disk to memory or vice versa. DMA requires another bus control device called a DMA controller, shown in the following illustration, which is able to work autonomously after it has been initialised by the CPU.
Bus CPU DMA controller Start address Count Device identifier Direction flag Memory Device 1 Device 2

Typically, the CPU loads the following for registers in the DMA controller: a memory start address, a count of the number of words to be transferred, a device identifier and a direction flag to indicate input or output. The DMA controller can then be left to get on with the job until it interrupts the CPU to tell it that the transfer has been completed. Meanwhile, the CPU can perform other tasks, provided that they do not conflict with this transfer.
SQA Version 1 128 Developed by COLEG

Computer Architecture 1

DH2T 34

There is, however, the possibility of a conflict when both the CPU and the DMA controller wish to access memory at precisely the same time. Because the transfer of data from very fast peripheral devices attached to the DMA cannot be held up, priority is usually given to the DMA in preference to the CPU. In most cases the CPU will originate the majority of memory access cycles, and hence in the case of contention the DMA can be thought of as stealing a cycle from the CPU. Hence this is often known as cycle stealing. The DMA controller is used to transfer data from: memory to memory I/O to memory memory to I/O.

Typically a machine has more than one DMA channel. The advantages of DMA are: A computer that has DMA channels can transfer data to and from devices faster than a computer without them. They are useful for making backups since the data being sent does not require any CPU processing. The CPU can be carrying out other tasks while the backups are taking place.

DMA fell from favour for a while when CPU speeds increased and DMA bus technology did not. But it has made a comeback with the development of I/O bus technologies (the peripheral component interconnect bus (PCI), universal serial bus (USB), and the card bus) that are much faster and comparable with those on the main memory bus.

?
a

4.3

Complete the following questions and check your answers with those given at the back of the section. Describe the sequence of events that take place when an interrupt occurs. .. .. .. b What are the two ways in which the processor can deal with a device wanting attention? .. .. If you have any wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

129

Developed by COLEG

Computer Architecture 1

DH2T 34

T
1

4.1

To complete the work of the section, you should now attempt the tutor assignment that follows and send it off to your tutor for marking. Complete the following diagram by writing the names in full.
CPU

General purpose registers i ii iii iv v vi

i ii iii iv v vi 2 i ii iii

This component performs calculations on behalf of the CPU. This component is used to hold information about which memory location is to be accessed. This component holds information about the location of the next instruction to be executed. This component holds the program instruction currently being decoded. This component holds data transferred between the CPU and memory. This component coordinates the activities of the CPU. cache memory main memory I/O interface.

Extend the diagram to show the major interconnections between the CPU and:

Remember to identify the major interconnections.

SQA Version 1

130

Developed by COLEG

Computer Architecture 1

DH2T 34

Briefly describe the function of cache memory and explain the difference between write-through and write-back cache. .. .. .. .. .. ..

Match the following components to functions.


Functions

Component

(a) CPU (b) Cache

1. Conduit through which all data passes within system. 2. Provides high-speed data storage facility. 3. Sends and receives data from peripheral devices. 4. Provides large amounts of slower memory. 5. Moves and processes data.

(c) Main memory (d) I/O interface

(e) The system buses

Briefly outline the steps involved in writing to an I/O port. .. .. .. .. .. ..

How are multiple interrupts handled by the processor? .. ..

SQA Version 1

131

Developed by COLEG

Computer Architecture 1

DH2T 34

.. What, if any, are the disadvantages of such an approach? .. .. .. ..

SQA Version 1

132

Developed by COLEG

Computer Architecture 1

DH2T 34

Summary of this section


You should now know all of the functional components of the processor and how they are connected to internal and external devices. You should also be able to differentiate between polling and interrupts, and the effect they have on the processor. If you are experiencing any difficulties with this section, or have any enquiries, then you should contact your tutor for advice.

SQA Version 1

133

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to SAQs
SAQ 4.1

Continuing the example: PC 100 1 MAR 99 MDR 23 IR LDA Ax 23

The contents of the PC are passed to the MAR. MAR 100 MDR 23 IR LDA Ax 23

PC 100 2

The instruction is read from memory and placed in the MDR. MAR 100 MDR ADD IR LDA Ax 23

PC 100 3

The PC is incremented by 1. MAR 100 MDR ADD IR LDA Ax 23

PC 101 4

The instruction is passed from the MDR to the IR. MAR 100 MDR ADD IR ADD Ax 23

PC 101 5

The contents of the PC are passed to the MAR. MAR 101 MDR ADD IR ADD Ax 23

PC 101 6

The data is read from memory and placed in the MDR. MAR 101 MDR 7 IR ADD Ax 23

PC 101 7

The PC is incremented by 1. MAR 101 MDR 7 IR ADD Ax 23

PC 102 8

The ALU will perform the calculation and the results will be placed in the Ax. MAR 101 MDR 7 IR ADD Ax 30

PC 102
SAQ 4.2

Steps required for a memory read: 1 2 3 4 5 Processor puts the required address on the address bus. Any addresses that invoke chip select lines are decoded. Chip select is generated. Wait for memory to settle. Memory puts data on the data bus.

SQA Version 1

134

Developed by COLEG

Computer Architecture 1

DH2T 34

6 7

Processor generates memory write control bit. The contents are written to the MDR.

SAQ 4.3 a

The sequence of events that take place when an interrupt occurs: 1 2 3 4 5 The contents of the internal registers are stored. The ISR is found. The ISR is processed. The internal registers are reloaded from the stack. Processing continues from where it was stopped. Polling all devices are examined in turn. Interrupts a signal is sent indicating a device requires attention.

SQA Version 1

135

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

136

Developed by COLEG

Computer Architecture 1

DH2T 34

Section 5: The fetchexecute cycle

SQA Version 1

137

Developed by COLEG

Computer Architecture 1

DH2T 34

SQA Version 1

138

Developed by COLEG

Computer Architecture 1

DH2T 34

Introduction to this section


What this section is about

This section is about the processing of machine-level program instructions. It will cover the format of a typical instruction, and how the processor will access and execute an instruction. Before you start it is important that youve completed the work for Section 3, covering memory and the functional units of the processor. There is no practical work in this section so you will be able to complete the work at home.
Outcomes, aims and objectives

The aim of this section is to introduce you to the exact steps the processor has to take when it reads and executes a program instruction. The objectives of this section are to: know how machine operations are organised and represented understand the different addressing modes used by the processor detail the activities involved in the fetchexecute cycle.

Approximate study time

6 hours.
Other resources required

None.

SQA Version 1

139

Developed by COLEG

Computer Architecture 1

DH2T 34

Assessment information for this section


How you will be assessed

This section forms part of Outcome 3. There is a tutor assignment at the end of this section so that you can check your progress.
When and where you will be assessed

The assessment for Outcome 3 will be in the form of an in-class assessment. It will be an open book assessment so you will be able to use your notes. This is a formal assessment and it will be held at your centre. If attending the centre is likely to be a problem for you, you should consult your tutor.
What you have to achieve

The assessment will be in the form of a set of tasks. It will be necessary for you to successfully complete all the tasks.
Opportunities for reassessment

There will be one opportunity to resit any task or tasks that you did not pass the first time.

SQA Version 1

140

Developed by COLEG

Computer Architecture 1

DH2T 34

Programming languages
Some of the earliest working computers, like ENIAC built in 1946, were programmed by the manual resetting of switches. Anyone programming such a machine would have to know exactly how the machine worked and be able to code every instruction directly into strings of binary. In contrast, the high-level languages like COBOL, C++, Pascal or Java are easier for the programmer to work with because the instructions are composed using recognisable words, like PRINT and READ, and it is not essential to know exactly how the processor works. Before any computer program can be processed it has to be converted into a binary code known as machine code. There are two ways of doing this.
Compiler

A compiler reads and checks the code for syntax or logical errors. It then produces a version of the program in machine-executable (binary) code, so machine-code instructions are bit patterns. This can be stored and run when required. This process is slower the first time around as the whole of the source code is compiled together. Once the program has been compiled, the original code, the source code (high-level language) need not be used again. The program will be executed faster as the program is now in machine code and the processor can carry out the instructions immediately. The user does not require access to the source code or require a compiler to run the program.
Interpreter

An interpreter reads and executes the program at the same time. The interpreter deals with one line of source code (high-level language) at a time and translates it into machine code. The machine code is passed to the processor to carry out that instruction. This produces a faster result the first time as the user does not have to wait until the whole source code is translated. The source code has to be interpreted every time the program is run which is a waste of the computers resources and the user must have access to both the interpreter and the source code.

Assembly language
Assembly language is a low-level language that uses mnemonics, operands and comments to give instructions to the computer. (Mnemonics are codes that are easier to remember than the corresponding machine-language instructions. Load register A might be abbreviated as LDA.) The instructions closely mirror the operations of the processor but are in a form that can be read and understood by the programmer. A program written in assembly language uses many more instructions than a high-level program would use to do the same thing, and each instruction accomplishes less than most high-level instructions. In general there is a one-to-one relation between the assembly language instruction and the corresponding machine-language instruction.

SQA Version 1

141

Developed by COLEG

Computer Architecture 1

DH2T 34

High-level instruction Z=X+Y

Equivalent assembly LDA a, X

Take the value from location X and put it in the accumulator. Add the value in location Y to the accumulator. Copy the result into the location Z

ADD a, Y STO Z, ,a

Before looking in detail at the format of assembly language instructions, it is necessary to know how the processor stores values during the accessing and execution of an instruction.

Registers
In Section 4 you were introduced to the functional units of the processor. Can you remember them? Here is an activity to remind you.

A
ALU MAR

5.1

Complete the table below. If you are in doubt, use your notes from Section 4.
Component Function

DB (MDR) IR PC Control Unit

Now look at the end of the section to make sure that you have the correct answers. The registers you already know about, PC, MAR, DB (MDR), IR and AX are each used for one specific purpose. Most processors also have a number of other generalpurpose registers that are used to hold data temporarily as part of the processing operation. If extra registers were not available these data items would have to be written back out to memory and then fetched again when needed. There is an area in memory called the stack used for this purpose.

SQA Version 1

142

Developed by COLEG

Computer Architecture 1

DH2T 34

For example, when the processor has to deal with an interrupt, the values from the internal registers are placed on the stack until the interrupt has been dealt with. Having extra registers at the disposal of the processor enables it to work faster. The set of extra registers varies from one machine architecture to another but the principle remains the same. For the purposes of this section we will refer to these registers as AX, BX, CX, DX, etc. Some processors use a general-purpose register AX as the accumulator and some use a special purpose accumulator.

Assembly language instructions


Assembly language programs are written using the instruction set for the processor being used. An instruction can have the following: Mnemonic Operand Comment This is the name of the instruction and it will be recognised by the instruction decoder. For example: ADD. Most instructions have zero, one or more operand values. For example: AX, [378]. A comment is on the same line as the instruction and is preceded by a semi-colon ;. For example: ; add the value in location 378 to the accumulator (AX). A label allows the program to jump backwards or forwards rather than executing the coding lines in exact sequence. A label name is followed by a colon :.
ADD Label ADD AX, [378] ; add the value in location 378 to the accumulator operand comment

Label

NEXT :

mnemonic AX, [76]

This instruction will take the value held in memory location 76 and add it to the accumulator.
LDA SUB AX, #245 AX, [673]

This will take the value 245 and copy it into the accumulator. This will subtract the value in memory location 673 from the value stored in the accumulator.
JUMP NEXT

This will transfer the control back to the instruction that starts with the label NEXT.

SQA Version 1

143

Developed by COLEG

Computer Architecture 1

DH2T 34

?
LDA ADD

5.1

Complete the following questions and check your answers with those given at the back of the section. What do you think these mean? AX, #65 AX, [99] If you have anything wrong, look back over the topic then try again. If you are still not sure, then check with your tutor.

Addressing modes
Built into each instruction is information about how each operand is to be interpreted. For example, does the operand represent a value to be added, is it the location in memory of a value to be added or is it the address of another register that holds the location of a value to be added? There are different ways of using operand values. Using the memory extract: 76 77 78 79 80 81 82 83 BX 81 99 205 81

SQA Version 1

144

Developed by COLEG

Computer Architecture 1

DH2T 34

Addressing mode

Explanation

Example

Value in AX after execution

Immediate Direct

The operand is the value to be used in execution The operand is the memory address that holds the value to be used in execution. The operand points to a register that holds a memory address where the value for execution is to be found.

LDA AX, #77 LDA AX, [77]

77 81

Indirect

LDA AX, [BX]

99

SQA Version 1

145

Developed by COLEG

Computer Architecture 1

DH2T 34

5.2

Using this memory extract: 100 101 102 103 104 105 106 107 BX 101 99 205 81

Complete the table below


Instruction Contents of accumulator after execution Addressing mode

LDA AX,[106] LDA AX, [BX] LDA AX, #105

SQA Version 1

146

Developed by COLEG

Computer Architecture 1

DH2T 34

The fetchexecute cycle


During the processing of a computer program the processor will fetch one instruction at a time from memory, place it in the instruction register, decode it, and then execute it. The process of reading a program instruction and executing it is known as the fetch execute cycle. It has two distinct phases: the fetch phase the execute phase.

The fetch phase is predictable. The processor performs a fixed series of steps each time, but the execute phase is of course dependent on what the particular instruction requires. The PC points to the address of the instruction in memory. PC [MAR] MAR, value in program counter put in the memory address register MDB, memory is read and the content of memory location put in data buffer or memory data register (the square brackets [MAR] indicate the content of the memory address location, rather than the address itself). IR, data from MDB put in instruction register PC, PC incremented by 1

MDB PC + 1 Decode IR Execute IR

This sequence is repeated until the program is finished. The processor knows when it is in fetch phase or execute phase. Therefore it knows when the data in the data register is an instruction and should be placed in the instruction register or when it is data and should be placed in a data register. The steps of the execute phase depend on the instruction. For example, if the instruction is LDA AX, [516] then the execute phase would be: 516 [MAR] MDB MAR MDB Accumulator

SQA Version 1

147

Developed by COLEG

Computer Architecture 1

DH2T 34

This complete cycle can be shown in the table below, assuming that the initial value in the PC is 66 and that the value in location 516 is 88. The addressing mode is direct.
STEP PC 66 MAR DB IR AX

1 2 3 4 5

66 66 66
67

66

66 66 66
67

LDA AX

LDA AX LDA AX LDA AX


[516]

LDA AX

LDA AX LDA AX LDA AX LDA AX LDA AX LDA AX LDA AX


88

6
7 8 9 10 11

67 67 67 67 67
68

67
516

[516]
88

516 516 516

88 88

88

The shaded line indicates when the decoding takes place. Notice that to read the value 88 from memory the address 516 must be put in the MAR to allow the processor to find the location. Data received from memory is always put in the MDB (MBR).

SQA Version 1

148

Developed by COLEG

Computer Architecture 1

DH2T 34

5.3

Complete the following question and check your answer with that given at the end of the section. Write down the steps of the fetchexecute cycle. .. .. .. .. .. If you have anything wrong, look back over the topic, then try again. If youre still not sure, then check with your tutor.

SQA Version 1

149

Developed by COLEG

Computer Architecture 1

DH2T 34

5.2

Now try to complete the tables below showing the steps of the fetchexecute cycle. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ADD AX #43 SUB AX [BX] LDA AX [30] 84 65 191 190 189 69 47 281

Based on the memory extract shown above, complete the following tables identifying the steps of the fetch execute cycle for each of the given instructions.

SQA Version 1

150

Developed by COLEG

Computer Architecture 1

DH2T 34

LDA AX, [30]


STEP PC

(this uses direct addressing)


MAR DB IR AX BX

The value in the PC at the start is 43. (The instruction is stored in location 43.)

SQA Version 1

151

Developed by COLEG

Computer Architecture 1

DH2T 34

ADD AX, #43 (this is immediate addressing) At the start the value in the accumulator is 150 and the value in the PC is 39.
STEP PC MAR DB IR AX BX

SQA Version 1

152

Developed by COLEG

Computer Architecture 1

DH2T 34

SUB AX, [BX] (this is indirect addressing) The SUB command subtracts from the accumulator. The content of BX at step 1 is 32. The content of AX at step 1 is 200. The value in the PC is 41.
STEP PC MAR DB IR AX BX

1 2 3 4 5 6 7 8 9 10 11

When you are finished, check your answers with the ones at the end of the section..

SQA Version 1

153

Developed by COLEG

Computer Architecture 1

DH2T 34

To complete the work of this section you should now attempt the tutor assignment that follows and send it to your tutor for marking.

5.1

782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 ADD AX [784] LDA AX #797 SUB AX [BX]

289 65 54 190 189 798 12 281

Based on the memory extract shown above, and using AX as the accumulator, complete the following tables identifying the steps of the fetchexecute cycle for each of the given instructions.

SQA Version 1

154

Developed by COLEG

Computer Architecture 1

DH2T 34

ADD AX, [784] (this uses direct addressing) The value in the PC at the start is 790. AX holds the value 32.
STEP PC MAR DB IR AX BX

SQA Version 1

155

Developed by COLEG

Computer Architecture 1

DH2T 34

SUB AX, [BX] (this uses indirect addressing) The value in the PC at the start is 794 and the value in AX is 417. BX holds the address 782.
STEP PC MAR DB IR AX BX

SQA Version 1

156

Developed by COLEG

Computer Architecture 1

DH2T 34

LDA AX, #797 (this uses immediate addressing) The value in the PC at the start is 792.
STEP PC MAR DB IR AX BX

SQA Version 1

157

Developed by COLEG

Computer Architecture 1

DH2T 34

Summary of this section


You should know the different addressing modes used by the processor and how assembly language instructions are formed. You should also be able to detail the steps of the fetchexecute cycle for a given assembly language instruction.

SQA Version 1

158

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to SAQs
SAQ 5.1

LDA AX, #65 Load the value 65 into the accumulator ADD AX, [99] Add the value found in the memory location 99 into the accumulator
SAQ 5.2 Instruction Contents of accumulator after execution Addressing mode

LDA AX,[106] LDA AX, [BX] LDA AX, #105

205 81 105

Direct Indirect Immediate

SAQ 5.3

PC [MAR] PC + 1 DB (MDR) Decode IR Execute IR

MAR, value in program counter put in the memory address register DB (MDR), memory is read and the content of memory location put in memory data register PC, PC incremented by 1 IR, data from MDR put in instruction register

This sequence is repeated until the program is finished.

SQA Version 1

159

Developed by COLEG

Computer Architecture 1

DH2T 34

Answers to activities
Response to activity 5.1 Component Function

ALU MAR

Performs the arithmetical and logical operations and places the result into the accumulator or GP registers. Memory address register holds the address of a location in memory that is to be accessed. An address being put on the address bus always goes to the MAR first. The address is transferred from the MAR onto the address bus. Data buffer or memory data register holds data that is being written to memory or an output device, or being read from memory or an IO device. Data being transferred to or from the data bus is always placed on the MDR. The data is transferred form the MDR onto the data bus, or from the data bus into the MDR Holds the instruction currently being decoded and executed. Holds the address of the next program instruction to be fetched Uses control signals to coordinate the operations of the processor.

DB (MDR)

IR PC Control unit

SQA Version 1

160

Developed by COLEG

Computer Architecture 1

DH2T 34

Response to activity 5.2

LDA AX, [30]


STEP PC 43 MAR DB 43 IR AX BX

1 2 3 4 5 6 7 8 9 10 11

43 43 43
44

43 LDA AX 43 LDA AX 43 LDA AX


44 LDA AX LDA AX

LDA AX LDA AX LDA AX LDA AX LDA AX LDA AX LDA AX


84

44 44 44 44 44
45

44 [30]
30 [30]

30 84 30 84 30 84

84

ADD AX, #43


STEP PC 39 MAR DB 39 IR AX 150 BX

1 2 3 4 5 6 7 8 9

39 39 39
40

150 150
ADD AX

39 ADD AX 39 ADD AX 39 ADD AX


40 ADD AX

150 150 150 150


193

ADD AX ADD AX ADD AX ADD AX ADD AX

40 40 40
41

40 #43 40 #43 40 #43

193

SQA Version 1

161

Developed by COLEG

Computer Architecture 1

DH2T 34

SUB AX, [BX]


STEP PC 41 MAR DB 41 IR AX 200 BX 32

1 2 3 4 5 6 7 8 9 10 11

41 41 41
42

200 200
SUB AX

32 32 32 32 32 32 32 32 32 32

41 SUB AX 41 SUB AX 41 SUB AX


42 SUB AX

200 200 200 200 200 200


9

SUB AX SUB AX SUB AX SUB AX SUB AX SUB AX SUB AX

42 42 42 42 42
43

42 [BX]
32 [BX]

32 191 32 191 32 191

SQA Version 1

162

Developed by COLEG