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A Generalized State-Space Averaged Model of the Three-Level NPC Converter for Systematic DC-Voltage-Balancer and Current-Controller Design
Amirnaser Yazdani, Student Member, IEEE, and Reza Iravani, Fellow, IEEE
AbstractA comprehensive dynamic model of the three-level Neutral Point Diode Clamped (NPC) converter, based on the generalized state-space averaging method, is presented. The developed model mathematically describes (i) the reason for and (ii) the impacts of the system parameter tolerances on the drift/imbalance of the DC-side capacitor voltages. Then, based on the developed model (i) a novel controller to prevent DC capacitor voltage drift/imbalance and (ii) a decoupled current controller in the dq-frame are designed. The paper also presents a feed-forward control to eliminate the coupling between the voltage balancer and the current controller. The accuracy of developed NPC converter model and the effectiveness of the proposed controls are veried by time-domain simulations of a study system in the PSCAD/EMTDC environment. Index TermsGeneralized averaging method, multi-level converter, neutral point voltage control, unipolar PWM.

I. INTRODUCTION

ONTINUOUS advances in semiconductor technology and availability of high-power, high-frequency switches have made the Voltage-Sourced Converter (VSC) a technically viable converter at the utility power level applications. The most widely used VSC topology is the two-level VSC [1]. Comprehensive analysis of performance and control aspects of the twolevel VSC, for the utility applications, are widely reported in the technical literature [2][5]. In spite of the rapid developments in semiconductor technology, a major challenge to the widespread utility applications of the two-level VSC is the economical availability of semiconductor switches at high-power, high-voltage and high-switching-frequency ratings. The multi-level VSC topologies [6][8], largely address this issue and permit utilization of the most economically available switch in a converter, which has a voltage rating well beyond that of the switch. Among the multi-level VSC congurations, the multi-level Neutral Point Diode Clamped (NPC) converter has been widely accepted for applications in high power drives and the utility systems [9][11]. As compared with the other prevalent multi-level converter topologies [8] the NPC converter uses a fewer number of capacitors and switches per phase to
Manuscript received October 20, 2003. Paper no. TPWRD-00514-2003. The authors are with the Center for Applied Power Electronics (CAPE), Department of Electrical and Computer Engineering, University of Toronto, ON M5S 3G4, Canada (e-mail: yazdani@power.ele.utoronto.ca; iravani@ecf.utoronto.ca). Digital Object Identier 10.1109/TPWRD.2004.834307

synthesize the desired output voltage levels. It is therefore more economical and reliable. The NPC converter topology also readily renders itself for (i) connection in a back-to-back conguration suitable for HVDC back-to-back schemes and (ii) interfacing a distributed generation (DG) unit, e.g. wind and micro-turbine based generation systems, to the utility grid. This paper is concerned with the three-level NPC converter, which is referred to as the NPC hereinafter. The main technical challenge in any application of the NPC is to maintain the voltages of the two DC-side capacitors equal and at a pre-specied level. The DC capacitors voltages can either (i) rapidly and drastically diverge during transients or (ii) slowly drift during normal operations due to the system imperfections. To retain the capacitor voltages at a desired value, the following approaches have been proposed in the technical literatures: The rst approach is to use separate DC sources, one per capacitor, to maintain the capacitor voltages [12], [13]. The DC sources are usually provided by a transformer through diode bridge rectiers. Such a source is large, heavy, inefcient, expensive and potentially with adverse impacts on the power quality of the prime power supply. The second approach is to use an auxiliary converter to inject a current in the neutral point of the NPC to balance the DC-side voltages [14][16]. The main shortcoming of this approach is the need for additional power hardware, which adds to the system cost and complexity, particularly at high voltage/power levels. The third method is to provide a current path between the neutral point of the NPC and the neutral point of the corresponding AC-side system [17]. The main problem of this approach is the zero sequence current through the AC-side, which may not be acceptable due to heating, saturation or other system dependent issues. Another approach is to modify the converter switching pattern according to a control strategy to balance and maintain the required value of the DC-side voltages [18][20]. Although this approach requires a more elaborate control strategy/algorithm as compared with the previous methods, it provides an economically viable approach to address the main technical issue of the NPC. This paper introduces a new controller to address the DC-side voltage imbalance of the NPC. To this end, a comprehensive dynamic model of the NPC, based on the generalized state-space averaging method, is presented. To the best of our knowledge, this model is novel and has not been reported in the literature. The proposed model not only predicts the dynamic behavior of

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voltage to the common point of the DC capacitors, 0, when both and are on. Consequently, regardless of the direction of , is clamped to 0 when both and are on. therefore swings between the neutral-point potential (here reduring the rst half-cycle and the neuferred to as zero) and during the second half-cycle. Thus, tral-point potential and or . each switch when off, is subjected to at most either Therefore, if and are equal, each switch has to tolerate . Thus, the NPC only half of the total DC voltage of permits utilization of switches at lower voltage ratings. and is to maintain Another motivation for equalizing the harmonic distortion of the terminal voltage at minimum. and leads to even harmonics in the terAny inequality of minal voltage of the NPC due to asymmetry. It is also possible, as is shown in the next sections, that and voltages diverge so that the NPC ceases to operate. III. DYNAMIC MODEL A. The Generalized Averaging Method The generalized state-space averaging method is a tool for large signal dynamic modeling of power converters [21][23]. can be approximated Based on this method, a waveform to any desired accuracy by the Fourier on the interval series:
Fig. 1. A three-phase, three-level NPC and unipolar PWM waveforms.

(1) where and (2) is the kth coefcient of the Fourier series expansion and is an integer. Ideally if approaches innity, the approximation error becomes nil. However, in most cases it sufces to consider only a few terms. The generalized averaging method ento study the dynamic ables one also to consider behavior of the rst harmonic of the signal and/or for the second harmonic and so on. The application of this method to the state-space modeling is based on the following [21]: (3)

all the AC and DC-side variables of the NPC, also provides a mathematical means to describe the reason for the DC capacitor voltage drift and the effects of system imperfections and component tolerances on the voltage imbalance of the capacitors. Based on the developed model, this paper introduces a new controller which provides a simple and efcient approach to maintain balance of the DC-side capacitor voltages of the NPC. The rest of this paper is organized as follows. Section II briey describes the principles of operation of the NPC, based on the unipolar PWM switching strategy. Section III develops a dynamic generalized state-space average model of the NPC and highlights similarities of the NPC and the two-level VSC. Section V (i) veries the accuracy of the developed NPC model and (ii) demonstrates performance of the proposed control method. Conclusions are stated in Section VI. II. PRINCIPLES OF THREE-LEVEL NPC AND THE PWM STRATEGY Fig. 1 shows the NPC and its corresponding AC-side equivalent circuit. Fig. 1 also shows the sinusoidal PWM waveforms, and line switching functions and, the AC-side phase voltages, based on the unipolar switching strategy. Consider phase-a of the NPC of Fig. 1. During the rst halfis kept on (off). cycle of the modulating signal, switch and are turned on and off At the same time switches based on the comparison of the absolute values of the modulating and the carrier waveforms. Similarly during the second is kept on (off) and half-cycle of the modulating signal, and are turned on and off. Diodes and provide paths for bidirectional current ow from the AC-side terminal

(4) Based on (3) and (4) both sides of the state-space equation can be expanded to any desired number of terms to nd the dynamic behavior for the time evolution of each of the signals rather than dealing only with the original signals themselves. The following sections apply the method to the dynamic modeling of the NPC. B. The NPC Dynamic Model Based on the Generalized Averaging Method 1) Basic Mathematical Equations of the NPC: Prior to development of the dynamic model of the NPC, the following assumptions are made:

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The carrier frequency is assumed much larger than that of the modulating signal (e.g. more than 10 times). The switching and conduction losses of the converter are represented by the series resistance of the AC-side. The DC capacitors are adequately large so that the changes of their voltages within one carrier period can be neglected. Thus, during the rst half-cycle of the modulating signal: (5) (6) (7) and during the second half-cycle of the modulating signal: (8) (9) (10) And during a complete cycle:

The angular frequency of the modulating signal, , is equal to . To avoid over-modulation (21) (22) Substituting (19) and (20) in (18) and neglecting high frequency yields harmonics of rst half-cycle second half-cycle (23) (24)

and based on (2) indicates that neCalculation of glecting the high-frequency harmonics of is a valid apwith frequencies proximation, since the components of and . other than do not contribute to and : From (5) and (8), 2) Calculation of can be written as

(25) where function (11) (26) (12) (13) (14) (15) (16) (27) (17) is the switching function. where For the type of studies reported in this paper, it is sufcient to , and for the DC-side quantities and consider , , and for the AC-side quantities. The period over which these averages are calculated is the period of the modulating signal. The switching function , can be expressed as harmonics (18) (29) where is the average of within one carrier period. As Fig. 1 illustrates, if the carrier frequency is much larger than the frequency of the modulating signal, at any given time is approximately the same as the instantaneous value of the modulating signal. Thus, let Similar equations for phases and voltages can be obtained by and respectively. substituting with 3) Calculation of and : Assuming that the , contains no zero-sequence three-phase voltage source, components, we have (30) Taking the zeroth and the rst averages of both sides of (30), we deduce (31) (32) Equation (27) can also be written as (28) Similar expressions can also be developed for the corresponding phases and quantities. In a similar manner, we can obtain as Taking the zeroth averages of both sides of (25) yields is dened as

during rst half-cycle during second half-cycle

(19) (20)

be the functions describing the modulating waveform where is the initial phase angle and, and are the DC offsets of the sinusoidally varying modulating waveform in each half-cycle.

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Equation (31) shows that a difference between and results in a nonzero DC component in the voltage of the AC-side null point. 4) Calculation of and : Substituting (19) in (6) and (20) in (10), we deduce (33) (34) If then is replaced by in (1) and is considered,

Substituting (44) and (45) into (15) yields (46) 5) DC-Side Dynamics: Subtraction of (17) from (16) results in

(47) (35) Equation (47) gives the dynamics of the voltage difference of the DC capacitors. Although, the capacitances practically are not exactly equal, (47) can still be used as a good approximation of the voltage difference. The dynamics of the net DC voltage is obtained by adding (16) and (17)

Assume (36) (37) then

(38)

(48) 6) AC-Side Dynamics: Taking the zeroth averages of both for results in sides of (12) and substituting

(39) The procedures to deduce (38) and (39) are given in the Appendix. and we Since obtain

(49) Equations (28) and (31) conclude that and are equal. However, due to the tolerances of switch voltage drops, they are not exactly identical and consequently is not precisely zero. Therefore, is not zero in the steadystate and a DC offset exists in the current of each phase of the NPC. With the typical tolerances of the voltage drops of the power semiconductor switches, the DC offsets are negligible as compared with the AC-side rated currents of the NPC and no longer considered in our analysis. Taking the rst averages of both sides of (12) and replacing by according to (3), result in

(40)

(41) (50) (42) Substituting (29), (32) and (37) into (50) and splitting the result into the real and imaginary parts, yields

(43) (51) Since , from (38) to (43), we deduce (44) (45) where and .

(52)

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7) Expression of the Dynamic Model in dq0-Frame: We conclude the dynamic modeling of the NPC by describing the averaged model in a dq0-frame. To be consistent with those researchers who express all waveforms in the cosine form [3], in (47), (48), (51) and (52). [4], let be replaced by and Substituting (36) and (37) into (35), assuming as rewriting the result in the real form, yields (53) (54) (55) Similarly, the AC-side source voltages are (56)

(69) Equations (66) to (69) describe the dynamic behavior of the , and is three-phase NPC of Fig. 1. If we assume replaced by , the dynamic model of the three-level NPC, (67) to (69), becomes the same model as that of the two-level VSC implies that no DC [3], [4]. The assumption of neutral-point current exists and the equivalent capacitance of the , in series, is . This is an important two capacitors, each at outcome which permits all the analytical techniques developed for the two-level VSC, to be also applicable to the NPC. IV. CONTROL STRATEGY and/or from zero cause a drift From (66), deviations of in the voltage of each DC capacitor. This is, practically, the case regardless of the type of control implementation adopted. In an analog implementation, the offset of the comparators is the cause while in a digital implementation the numerical errors are the reason. Not only are the intrinsic nonzero values of and problematic, but the DC components of the phase currents can also initiate the drift. In developing (44) and (45), it is , implicitly assumed that the corresponding coefcients of and , in (38) to (43), are identical. Thus, the assumprequires that the DC components tion of of the AC-side currents do not appear in (44) and (45), which is an approximation and not precisely true. In the next section, and a DC-side voltage-balancer based on (66) is proposed. are the control variables of the proposed controller. Furthermore, based on the developed dynamic model of Section III, a decoupled AC-side current controller is proposed. A. DC-Side Voltage Balancer The voltage balancer maintains the DC voltage difference of the two capacitors at the set-point value. Based on the voltage difference of the DC capacitors, the voltage balancer determines the updated values of the DC offsets and . These values are added to the modulating waveforms at the successive half cycles (or ) changes the width of each of the modulating signal. switching pulse in the corresponding half-cycle, to correct the mid-point current. Let (70) (71) (72) where is given by (26). Substituting (70), (71) and (72) in (66) results in

(57)

(58) Transforming transformation and into the dq0 frame, based on the [24], we deduce: (59) (60) (61) (62) (63) (64) where

(65) Equations (47), (48), (51) and (52) can be written in terms of dq0 quantities as (66)

(67) (73) Let the control action be dened as (68) (74)

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Fig. 2. Block diagram of the proposed DC voltage balancer.

where is a small positive number to prevent division by zero and is a positive number which determines the loop-gain value. Substituting (74) in (73) yields (75)
Fig. 3. Block diagram of the decoupled dq-frame current controllers.

is the voltage which is a rst-order closed-loop system. difference command and usually is set to zero. The sign of must be taken into account in the control action to avoid a positive feedback. The control action can be to make the closed-loop speed divided by of response independent of the operating point. Fig. 2 shows the block diagram of the proposed controller. B. AC-Side Decoupled Current Controller Equations (68) and (69) can be rewritten as (76) (77) where (78) (79)

TABLE I SYSTEM PARAMETERS

Equations (82) and (83) are the same as the corresponding expressions of the two-level VSC [3]. It is also possible to take and as well as the DC voltages into account the effects of in determining the modulating index

(84) A decoupled current controller can be dened by [4] (80) (81) where and are new control signals obtained from two independent PI controllers. One PI controller processes to produce and the other performs the same on to produce . Then and are translated into phase and magnitude to produce the modulating waveform. It is expected and are nearly zero and can that, in a steady-state regime, be ignored in (78) and (79). Therefore (82) which suggests a feed-forward compensation. The effect of this feed-forward compensation is presented in the subsequent case studies. Fig. 3 shows the current controller block diagram. V. CASE STUDIES The studies reported in this section were performed on the three-phase NPC system of Fig. 1, using parameters of Table I. The studies are conducted: To demonstrate the performance of the NPC DC voltage balancer developed in Section IV and to verify its effectiveness in preventing the drift of the DC capacitor voltages. To verify the accuracy of the averaged NPC model combined with the developed controllers. Two study models of the system of Fig. 1 are developed. The rst one is an exact switching model of the system including

(83)

YAZDANI AND IRAVANI: GENERALIZED STATE-SPACE AVERAGED MODEL OF THE THREE-LEVEL NPC CONVERTER

1111

Fig. 5. Zoomed portion of top four graphs of Fig. 4 superimposing the exact and the averaged model results.

A. Case-1 Initially the system current components and are equal to 355 A and 112 A respectively. The net DC voltage of the system , is set is 1500 V. The DC voltage difference command, to 0 and the feed-forward compensation is enabled. Therefore the voltages of the two capacitors are equal, namely at 750 V. , the DC difference command, , is changed At is changed from 100 V to from 0 to 100 V and at 100 V. Fig. 4 shows the system response. The right and the left columns of Fig. 4 correspond to the exact model (developed in PSCAD/EMTDC environment) and the averaged model, respectively. The waveforms of the exact model contain higher order ripples and harmonics. Fig. 4 illustrates that although the average model does not include the higher order ripples and harmonics (unless they are intentionally taken into account in calculation of the generalized average of the each quantity of the system), it provides the same pattern of response as that of the exact model. As shown in Fig. 4, the voltage controller (balancer) effectively imposes the desired voltage difference between the two capacitors. Fig. 4 also shows that the AC-side currents remain unaffected when the DC voltages are changed. This is due to the feed-forward compensation employed in the voltage balancer which rapidly corrects the modulation index, , during the abrupt changes of . Fig. 5 closely compares the results of the exact and the averaged models. Fig. 5 shows magnied top four graphs of Fig. 4

Fig. 4. The DC voltage-balancer with feed-forward compensator in service, (a) exact switching model (PSCAD/EMTDC), (b) averaged model.

the controllers. This model is developed in the PSCAD/EMTDC environment. The second one is the averaged model of the system described in Section III including the controllers. The averaged model can be implemented in an equation solver environment, e.g. MATLAB.

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Fig. 7. Active power ow is reversed at t = 1:2 s from 250 kW to Fig. 6. The DC voltage-balancer performance when the feed-forward compensator is disabled, (a) exact switching model (PSCAD/EMTDC), (b) averaged model.

0250 kW.

when the exact and the averaged model results are superimposed. Fig. 5 veries the accuracy of the averaged model. B. Case-2 The operating conditions and the imposed commands for this case study are exactly the same as those of Case-1, except that

the feed-forward controller is disabled. Fig. 6 shows that without the feed-forward compensation, the AC-side currents experience signicant changes due to the relative changes of the DC voltages of the two capacitors. Fig. 6 also shows a close match between the corresponding results of the exact and averaged models and veries accuracy of the averaged model. C. Case-3 This case study demonstrates the effectiveness of the DC voltage balancer in preventing the voltage drift of the DC

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results and veries the validity and accuracy of the averaged model during large signal transients. D. Case-4 Fig. 8 shows the system behavior when the DC voltage-bal. Fig. 8 shows that the DC voltages ancer is disabled at and gradually drift even if the system is not exposed to any disturbance. Fig. 8 also indicates that the net DC voltage remains fairly constant in spite of the capacitor voltage drifts. In other word, a regulated net DC voltage at a desired value does not indicate that the voltage balancer of the NPC is not required. VI. CONCLUSION A comprehensive dynamic model of the three-level, Neutral Point Diode Clamped (NPC) converter, based on the generalized state-space averaging method, was developed. The developed model was used (i) to describe the reason for the DC voltage drift/imbalance of the two DC-side capacitors of the converter and (ii) to devise a controller to balance the DC voltages. The model also was used (i) to systematically design a decoupled current controller for the NPC in the dq-frame and (ii) to decouple the current controller and the voltage balancer through a feed-forward method. The developed mathematical model also shows that under simplifying assumptions, the model of the conventional two-level voltage-sourced converter (VSC) can be deduced from that of the three-level NPC. The accuracy of the developed dynamic model of the NPC and the effectiveness of the proposed voltage balancer and the current controller were veried by time-domain simulation studies in the PSCAD/EMTDC environment. APPENDIX Expanding (33) yields:

(85) If we dene (86) (87) the averaged form of (85) can be written as: (88)
Fig. 8. The DC voltage-balancer disabled at t = 0:5 s.

Equation (88) can be expanded based on (4):

capacitors. Initially the system is under a steady-state condition and transfers 250 kW from the DC-side to the AC-side. At the active power ow is reversed from the AC-side to the DC-side by changing the active current component, , from 355 A to 355 A while the reactive current component is constant. Fig. 7 shows the system response to this disturand are bance. Fig. 7 demonstrates that the DC voltages regulated within a narrow range even in response to the power reversal. Fig. 7 also compares the exact and the averaged model

(89) Thus, it can be shown that (90) (91)

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(92) (93) where denotes the complex-conjugate operator. Substituting (36), (37), and (90) to (93) in (89) concludes . (38). A similar procedure can be applied to REFERENCES
[1] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics, 2nd ed. New York: John Wiley & Sons, Inc., 1995. [2] A. N. Niaki and M. R. Iravani, Steady-state and dynamic models of unied power ow controller (UPFC) for power system studies, IEEE Trans. Power Syst., vol. 11, no. 4, pp. 19371942, Nov. 1996. [3] P. W. Lehn and M. R. Iravani, Experimental evaluation of STATCOM closed-loop dynamics, IEEE Trans. Power Delivery, vol. 13, no. 4, pp. 13781384, Oct. 1998. [4] C. Schauder and H. Mehta, Vector analysis and control of advanced static VAR compensators, IEE Proc.-C, vol. 140, pp. 299306, Jul. 1993. [5] N. Hingorani and L. Gyugyi, Understanding FACTS: Concepts and Technology of Flexible AC Transmission Systems. New York: IEEE Press, 2000. [6] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, Sep./Oct. 1981. [7] F. Z. Peng, J. S. Lai, J. W. Mckeever, and J. Vancoevering, Multilevel voltage-source inverter with separate DC sources for static VAR generation, IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 11301138, Sep./Oct. 1996. [8] J. S. Lai and F. Z. Peng, Multilevel convertersa new breed of power converters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509517, May/Jun. 1996. [9] J. Rodriguez, J. Pontt, G. Alzamora, N. Becker, O. Einenkel, and A. Weinstein, Novel 20-MW downhill conveyor system using three-level converters, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 10931100, Oct. 2002. [10] J. Shen and N. Butterworth, Analysis and design of a three-level PWM converter system for railway-traction applications, IEE Proc.-Electr. Power Appl., vol. 144, pp. 357371, Sept. 1997. [11] J. B. Ekanayake and N. Jenkins, Mathematical models of a three-level advanced static VAR compensator, IEE Proc.-Gener. Trans. Distrib., vol. 144, pp. 201206, Mar. 1997. [12] R. Sommer, A. Mertens, C. Brunotte, and G. Trauth, Medium voltage drive system with NPC three-level inverter using IGBTs, in IEEE PWM Medium Voltage Drives Seminar, May 11, 2000, pp. 3/13/5. [13] R. W. Menzies, P. Steimer, and J. K. Steinke, Five level GTO inverter for large induction motor drives, in IEEE Industry Application Society Annual Meeting, IAS93, vol. 1, Oct. 28, 1993, pp. 595601. [14] D. H. Lee, S. R. Lee, and F. C. Lee, An analysis of midpoint balance for the neutral-point-clamped three-level VSI, in IEEE Power Electronics Specialists Conf., PESC98, vol. 1, May 1722, 1998, pp. 193199. [15] C. Newton and M. Sumner, A novel arrangement for balancing the capacitor voltages of a ve-level diode clamped inverter, IEE Power Electronics and Variable Speed Drives, no. 456, pp. 465470, Sep. 2123, 1998.

[16] M. K. Mishra, A. Joshi, and A. Ghosh, Control schemes for equalization of capacitor voltages in neutral clamped shunt compensator, IEEE Trans. Power Delivery, vol. 18, no. 2, pp. 538544, Apr. 2003. [17] S. K. Lim, J. H. Kim, and K. Nam, A DC-link voltage balancing algorithm for 3-level converter using the zero sequence current, in IEEE Power Electronics Specialists Conf., PESC99, vol. 2, June 27July 1 1999, pp. 10831088. [18] C. Newton and M. Sumner, Neutral point control for multi-level inverters: theory, design and operational limitations, in IEEE Industry Application Society Annual Meeting, Oct. 59, 1997, pp. 13361343. [19] G. Scheuer and H. Stemmler, Analysis of a 3-level-VSI neutral-pointcontrol for fundamental frequency modulated SVC-applications, IEE AC and DC Power Transmission, no. 423, pp. 303310, Apr. 29May 3 1996. [20] C. Osawa, Y. Matsumoto, T. Mizukami, and S. Ozaki, A state-space modeling and a neutral-point voltage control for an NPC power converter, in Power Conversion Conf., vol. 1, Aug. 36, 1997, pp. 225230. [21] S. R. Sanders, J. M. Noworolski, X. Z. Liu, and G. C. Verghese, Generalized averaging method for power conversion circuits, IEEE Trans. Power Electron., vol. 6, pp. 251259, April 1991. [22] J. Mahdavi, A. Emaadi, M. D. Bellar, and M. Ehsani, Analysis of Power Electronic Converters Using the Generalized State-Space Averaging Approach, IEEE Trans. Circuits Syst., vol. 44, no. 8, pp. 767770, Aug. 1997. [23] S. Farhangi, A. Yazdani, and B. Fahimi, Model-reference adaptive control of a PFC-equipped battery-charger, in IEEE Industrial Electronics Conf., IECON01, vol. 2, Nov. 29Dec. 2 2001, pp. 10151020. [24] P. C. Krause, O. Wasynczuk, and S. D. Sudhoff, Analysis of Electric Machinery. New York: IEEE Press, 1995.

Amirnaser Yazdani (S02) received the B.Sc. degree (with honors) from Sharif University of Technology, Tehran, Iran, in 1995, and the M.Sc. from the University of Tehran, Iran, in 2001, both in electrical engineering. In September 2002, he joined the Power Devices and Systems Group of the University of Toronto, ON, Canada, where he is currently a Research Assistant, working toward the Ph.D. degree. From 1995 to 2002, he was a Design Engineer at Maharan Engineering Corp., Tehran, Iran, where he worked on the design and control of switching power supplies, UPS systems, and railway signaling systems. His research interests include design, dynamic modeling and control of switching power converters, electric drives and custom power devices.

Reza Iravani (M85SM00F03) received the B.Sc. degree from Tehran Polytechnic University, Tehran, Iran, in 1976, and the M.Sc. and the Ph.D. degrees from the University of Manitoba, Winnipeg, MB, Canada, in 1981 and 1985, respectively, all in electrical engineering. He is currently a Professor at the University of Toronto, ON, Canada. His research interests include power electronics and power system dynamics and control.