EEE523: ADVANCED ANALOG IC DESIGN PROJECT 1 CMOS -MULTIPLIER BASED CONSTANT-GM CURRENT REFERENCE Current Mirrors DUE Tuesday

Feb 21, 2013 IMPORTANT NOTE: FOR ALL CADENCE/EDA/SIMULATOR/PDK/CDK/MODEL FILES/PC ACCESS QUESTIONS PLEASE CONTACT YOUR LAB TA. FOR LAB HOURS, PLEASE SEE THE SYLLABUS.

NAME (LAST, FIRST, MI) ASU ID #

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EEE523: ADVANCED ANALOG IC DESIGN PROJECT 1: In this project youll be designing three beta-multiplier based current reference, using only CMOS transistors in TSMC 0.25u CMOS design library. For the current setting resistor R you can use an ideal zero-temperature coefficient resistor from analogLib library. As we discussed in class, the resistor R and beta multiplication value K sets your branch currents. Design 1:

K,

Design 2:

K, K, R

Design 3:

K, R

Designs 1,2 and 3: You will size the transistors, K and R optimize, in such a way that the reference currents Iref1, Iref2 match for a wide range of supply voltage VDD for both designs 1, 2 and 3. Also, you would use this current to bias an NMOS transistor and prove that its gm is constant, just like the current setting resistor R across process, voltage and temperature. Parameter Min Nom Max VDD 2.0V 2.5V 3.0V Iref1, Iref2 10uA DESIGN QUESTIONS: Provide this information for both Design 1, Design 2 and Design 3. 1) Define the current setting resistor value R and transistor sizes that give a nominal Iref1, Iref2 value of 10uA at VDD=2.5V at room temp. Show all your derivations for the resistor value and device parameters. Generate a table that state sizes of your devices and nominal, room temp biasing conditions. Include the start-up circuit transistors. Device W L VGS-Vt VDS Ibias R M1 M2 M3T M3B . . .

2) Plot Iref1, Iref2 currents for the VDD range given above ( for the plots use 200mV increments from 2V to 3V). Define the VDD range that Iref1 and Iref2 matches each other within +/- 5%. Note: matching is defined
I I as: matching(%) ref 1 ref 2 100 . Iref 2

3) Use this current as a bias for an NMOS diode connected transistor. Provide schematics for this arrangement. Plot the gm of this transistor from -20C to +85C. Prove that the beta-multiplier approach generates a constant gm in this transistor. Report the maximum % deviation across temperature for the biased transistor. DESIGN QUESTIONS: 1) Define the current setting resistor value R and transistor sizes that give a nominal zero temp coefficient VREF at VDD=2.5V at room temp. Show all your derivations for the resistor value and device parameters. Generate a table that state sizes of your devices and nominal, room temp biasing conditions. Include the start-up circuit transistors. Device W L VGS-Vt VDS Ibias R M1 M2 M3T M3B . . . 2) Plot VREF for the Vdd range given above ( for the plots use 200mV Vdd increments from 2V to 3V).

3) Plot VREF from -20C to +85C for Vdd=2.5V with nominal models