49 Semtech

Network Synchronization Tel Aviv Israel June 14, 2007
Patrick Diamond PhD Director Systems Engineering Advanced Communications and Sensing
Semtech Patrick Diamond PhD Director Systems Engineering
What makes a Network Synchronous? A synchronous network is one that provides a common clock. - Voice and Video are isosynchronous types of information - Data is asynchronous - The circuit that carries these info types is synchronous and provides the ingress and egress clocks. Network Service providers implement BITS and SSU machines in their central and serving offices to deliver the network clock to the network equipment. A network is synchronized if all elements operate on the same Epoch. A network is syntonized if all elements operate at the same frequency.
Semtech Patrick Diamond PhD - Director Systems Engineering
Basic System Reference Clock Architectures
Autonomous - No system reference clock or clock distribution system. Line cards generate local clocks. Depends upon logic buffers and inter-card memory stores for data stability. No protection switching or frequency/phase transient control. Not capable of performing SSM or clock transit node functions. Centralized - Centralized reference clock generation and distribution. Protection switching capability typically limited to frequency matching. Not capable of input to output phase build-out control. Cannot correct for phase disturbances. Line cards have same limitations. Distributed - Reference clock generation and distribution with phase build-out and frequency control on clock card and selected line cards.
Why is Synchronization so Important to Services Delivery? Transport Networks of the last 20 years have always been built using the circuit technology E-1, T1, SDH and Sonet. These transport techniques have a fundamental need for physical layer clock synchronization.
The BIT rate and the Line utilization are always the same value, ie an E1 has 2048 bit periods as well as 2048 clock cycles.
The Network Clock provides the perpetual heartbeat for the services using the network.
The source of the Network Clock is a caesium beam oscillator located in a GPS satellite, a BITS or SASE. This is called the G.811 Clock in ITU standards parlance.
Circuits use a frequency synchronous clock to control the ingress and egress of the information streams to be transported.
Why has Syncronization been so Important to Transport? The Synchronization standards guarantee the performance of today's transport networks. The Currency of Synchronization is TDEV and MTIE. Time Deviation is measured for 10000 seconds and compares a reference clock, G.811 quality to a derived clock. The amount of time drift allowed from the derived clock is tightly regulated. The measurement is presented in the form of a graphic mask target and the actual measured. Maximum Time Interval Error is measured for 100000 seconds and accumulates the time error between the above clocks. This measurement is also presented in graphic form with a target mask and actual measured plot. Synchronization standards define the limits of reference and nodal system clock wander, phase gain, phase jump and jitter.
Why has Syncronization been so Important to Transport? The ITU and ANSI standards organizations have defined the rules for Synchronization. These rules are expressed as a numerical standard. The ITU standards typically start with a G. and the ANSI standards start with a GR-. There are hundreds of standards issued by each organization.
ITU Synchronization Standards
ANSI Synchronization Standards
Synchronization Clock Quality Distribution Rules
Synchronization Distribution Hierarchy
Synchronization Currency in Todays Circuit Transport Networks

PRC (Cs) G.811
100us
SECs (Quartz) E1 G.813
10us
G.823 Traffic
SSU (Rb) G.812
1us
G.823 Sync SEC SSU PRC
}
SDH
E3
100ns
SECs (Quartz) G.813 SSU (Rb) G.812
10ns 100ms 1s 10s 100s 1,000s 10,000s 100,000s
E1
G.823 (Traffic) G.823 (Sync)
Obs. Interval (sec)

2.5us phase tolerance (TDD) Requires GPS to achieve Phase alignment BTS/NodeB (50ppb) BTS/NodeB (50ppb)
PLL
CDR
Framer
SETS - Functionality as Defined by ITU Standards
SelectA n x T1 p x T2 1 x T3
Squelch
SelectC
T4
SelectB
SETG
Squelch
T0
OSC
T1 T2 T3 T0 T4
- Clocks recovered from SONET/SDH line - Clocks supplied from PDH tributary input - Clock supplied from HSC - Clocks supplied to SONET/SDH equipment - BITS clocks supplied back to HSC source
Synchronization Solution - Upstream / Downstream
Network Input SEC References
Backplane SECs
BITS SEC Clock PDH SEC Clock Line Input Framed Data Mb/s Line Input Framed Data Mb/s Line Input Framed Data Mb/s
Line Interface 1 SETS Clock Generator Master
Line Card DS1

Frequency Translation
Line Output
SEC MFrSync
Line Card 622M

Frequency Multiplier
Line Interface 2 SETS Clock Generator Slave Line Interface N
Line Output
SEC MFrSync Line Card 2.5G

Frequency Multiplier
Line Output
SSM Input Reference Source Selection Priorities
Traditional Home Grown SETS Implementation
High component count means: high component cost board space consumption layout problems
Extremely difficult to get manufacturing repeatability and achieve standard compliant performance.
PDH BITS
MUX
Phase Detector
Low Pass Filter
MC68xx16 ADC uP Digital Filter, Temperature Compensati on,Control ADC
DAC
Low Pass Filter
TCVCX O
Temp. Sensor
Ref Clk
Restricted choice gives Temp. compensation inadequate flexibility must be calibrated and back-up - ignores differential aging coefficients
DSP uP runs complex, proprietary algorithm
Sensitive analog circuitry needs special care in layout
Oscillator Performance Requirements
Parameter
Unit
Stratum3 GR1244-II G.813
Stratum 3E GR1244-III G.812

4.6 4.6 0.012 0.01 0.001 0.001 4.6 4.6 2.06 2.0 0.01 0.05
ETSI 300-462-5
Free run accuracy Freq offset (total) Holdover stability (total) Temp Drift (24 Hrs) Initial Offset
ppm ppm ppm
4.6 4.6 0.37 0.28 0.04 0.05
Aging (20 years) Pull-in/Hold-in range Filter bandwidth Jitter (generation) RMS
ppm ppm Hz UI
4 4.6 + 4.6 1-10 (3) 0.01
4 4.6 + 4.6 0.001 0.01
2 4.6 + 4.6 1-10 0.01
The difference between initial offset and drift is that drift directly relates to the performance of the external XO. The initial offset is directly tied to the performance of the timing control when switching from a locked state to holdover.
Semtech Timing Technology for Traditional Chassis
XO
Clock
Sync A (Optional) Clock B
High Rate Line Clock A XO Holdover Card With Sync Clock A A (Optional) High Rate Line ACS89xx XO Holdover Clock B Sync A (Optional) Card Line Clock A ACS89xxHigh Rate With Sync B (Optional) Clock Clock B XO Holdover Sync A (Optional) Distribution Card With Sync B (Optional) ACS89xx Clock Clock A XO Clock B Holdover Recovered Clock Distribution Sync A (Optional) B (Optional) Sync Clock A ACS89xx Clock XO Recovered Clock Clock B Distribution Sync A (Optional) Framer Dat ACS89xx A Sync B (Optional) Clock SERDES Recovered Clock Clock B a
Sync B (Optional)
High Rate Line Card With
ACS85x x ACS85xx High Rate Line LC/P LC/P Card With ACS85xx High Rate Line Holdover LC/P Card With ACS85xx Holdover LC/P Distribution Framer ACS85xx
Recovered Clock
Sync B (Optional)
ACS85xx Recovered Clock LC/P
LC/P
ACS89xx
Data SERDES Clock Distribution Framer Clock Data SERDES
Framer Framer
Distribution
Data
Recovered Clock
SERDES
Sync Card A
Sec Clock (to each Line Card) A Optional Sync Clock (to each Line Card) A Sec Clock (to each Line Card) Optional Sync Clock (to each Line Card) Recovered Clocks From Line Cards
Data
SERDES
Sync Card B
Clock Distribution
Clock
Framer
Data
SERDES
BB AB C K P L A N E
Clock Distribution
Clock Sync
Sync
Clock BI TS
LIU
Recovered Clocks From Line Cards Data Monitors
ACS85xx SETS ACS85xx SETS

XO
To/From Network
XO
BITS
LIU
Data
Control, Data Clock & SSM Processing Control, Data & SSM Processing
Priorities Monitors Config. Priorities Config.
ACS8520/22/30- Two independent PLL paths for ITU Compliance
Two PLLs, known as the T4 & T0 path are completely independent

They are different for good reasons
The T4 path is to select a clock to output to a local BITS or SSU

It is not filtered, no phase buildout BITS/SSU will filter it to a much higher degree than our SETS (T0) function
The T0 path is used to generate the clock for the egress ports ITU Sync Trail PRC SECs T0 Path SECsline timed SEC & colocated SSU T0 Path SSU may well provide time from GPS or other source. But can simply clean up the line recovered clock Sync Trail Sync Trail
T0 Path
T4 Path SSU T0 Path
SSU
ACS8530 Block Diagram
Programmable pulse width and polarity 2 kHz and 8 kHz Frame Sync Pulses 1.544 MHz or 2.048 MHz (E1 or DS1) Output Configurations N x E1 or N x DS1, N = 1 to 16 19.44 MHz 44.736 MHz or 34.368 MHz (E3 or DS3) 6.48, 25.52 MHz 38.88 MHz, 51.84 MHz, 77.76 MHz 155.52 MHz
Existing Sync Card Family
311.04 MHz Number of Outputs Input Configurations 2, 4, 8 kHz N x 8 kHz (N = 1 to 12499)
10
10
1.544 MHz or 2.048 MHz (E1 or DS1) 6.48, 19.44, 25.52, 38.88, 51.84, 77.76 MHz 155.52 MHz Number of Inputs Phase Measurement Output Phase Adjustment
Features
10
Revertive/Non-revertive mode Los of Lock Indication General Features Activity Monitoring Frequency Monitoring 8 bit micro-processor modes Holdover (with appropriate TCXO, OCXO) PBO on currently locked reference
Hit-less Source Switching Stratum 3E compliance
Stratum 3 SONET/SDH Compliance Hardware Master/Slave control mode
Automatic Reference switching
ACS8522
4
14
14
Part No.
ACS8510
ACS8520
ACS8530
14
High-Rate (d d 16 TDM Line card, oldover

XO Clock A Sync A (Optional) Clock B Sync B (Optional)
ACS89xx ACS85xx LC/P
High Rate Line Card With Holdover Clock Distribution
Recovered Clock
Framer
Data
SERDES
ACS8525/26/27 for stability and Holdover

Supports SEC frequencies from 2kHz to 155MHz
ACS894x for OC-12 & to STM-16 outputs
High-Rate (d d
16 TDM Line card
Clock A Sync A (Optional) Clock B Sync B (Optional)
High Rate Line Card (<STM-16) without holdover
ACS8946
Clock Distribution To/From Network Framer

Data
Recovered Clock
SERDES
ACS8946 directly generates STM-16 compliant clocks

Supports SEC frequencies from 1.554MHz to 155MHz Includes muxing and automatic detection/switching
Simple TDM Line card (d d
Low Rate Line Card (<STM-1) with holdover
ACS85xx LC/P
Clock Distribution To/From Network Framer

Data
Recovered Clock
SERDES
ACS8525/26/27 for stability and Holdover

Supports SEC frequencies from 2kHz to 155MHz SEC clock
Directly Produce outputs for E1/DS1, E3/DS3 up to STM-1
Existing Line Card Part Family- Feature Chart
Part No.
Minimum input frequency
Features
Microprocessor Interface Automatic Ref Switching Number of Sync inputs
Performance Level
Short Term Holdover (ms) Long Term Holdover (indef)
Avail ability
Sync outputs (kHz)
Number of outputs
Number of inputs 3 3 2 2 1 2
Maximum output Frequency
Phase Buildout
FEC Rates
STM-16
STM-64
STM-4
STM-1
ACS8525 ACS8595 ACS8526 ACS8527 ACS8944 ACS8946
2 6 2 2 1 4
2kHz 2kHz 2kHz 8kHz 19MHz 19MHz
155MHz 155MHz 155MHz 155MHz 622MHz 622MHz
3 3
2&8 2&8 2&8 2&8

LOS
LOS
2 or 8*
PICMG AMC.0
Advanced Mezzanine Card AMC defines

A modular add-on or child card Extends the functionality Allows multiple line cards off a single carrier blade
ATCA AMC Carrier bladeVendor 'A'

AMC Slot 1
Vendor 'A' AMC Card
ACS8595 LC/P
AMC Slot 2
Vendor 'B' AMC Card

Recovered Clock Selection
Mix and match line cards e.g. RecoveredClocks

DS1/E1/J1 DS3/E3 OC-3/12/48 GbE WAN Cards 10 GbE Optical WAN Card.
AMC Slot 3
AMC Slot 4 AMC Slot 2 Each Clock to AMC Module: 8kHz, E1, DS1 or 19.44MHz
Vendor 'C' AMC Card
Unique ACS8595 drop-in solution
Synchronization Status Message Processing per G.781

The process of selecting a synchronization source from the set of physical ports is performed in three steps:
Figure 6/G.781 - Visualization of the synchronization source selection process(es)
Synchronization Status Message Carriage SDH
RSOH Pointer MSOH
Qual Lev
S1 bits b5 b8
SDH Description
P O H
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Quality Level Unknown Reserved ITU Rec G.811 Reserved Rec. G.812 Transit Reserved Reserved Reserved Rec. G.812 Local Reserved Reserved Synchn Eqpt Time Src. SETS Reserved Reserved Reserved Do Not use for synchronization
Payload
1 2 3 4
STM-1 Section Overhead

A1 B1 D1 A1 A1 A2 E1 D2 Admin Unit Pointers B2 D4 D7 D10 S1 B2 B2 K1 D5 D8 D11 M1 K2 D6 D9 D12 E2 A2 A2 J0 F1 D3
5 6 7 8 9 10 11 12 13 14 15
SSM Allocation Definitions for SDH From G.707 (03/96) Table 5
Synchronization Byte
1 2 3 4 5 6 7 8
Synchronization Status Message Carriage SONET
Section OH Pointer LOH
Qual Lev
S1 bits b5 b8
SONET Description
P O H
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Synch Tracability Unknown - STU Stratum 1 Traceable ST1 Reserved Reserved Reserved Reserved Reserved Stratum 2 Traceable ST2 Reserved Reserved Stratum 3 Traceable ST3 Reserved SONET Minimum Clock Traceable Reserved Reserved for Network Synchronization Use Do Not Use for Synchronization
Payload
1 -
STS-N Transport Overhead

A11 B1 D1 B21 D4 D7 D10 S1 Z1 Z1 B2N A1N A21 E1 D2 SPE Pointers K1 D5 D8 D11 Z2 Z2 M1 K2 D6 D9 D12 E2 A2N J0 F1 D3 Z0 Z0
3 4 5 Use Assignable 7
Synchronization Byte
1 2 3 4 5 6 7 8
SSM Allocation Definitions for SONET From Bellcore GR253 CORE (12/97), Sect 5.4.2
Synchronization Status Message Carriage E1

San1, San2, San3, San4, - Note 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Frame Payload
TS0 TS1 TS16 TS31
Qual Lev
Description
E1 Frame - Time Slots 0 to 31 - 256 bits - 125 us One Time slot = 8 bits
MF S M F Frame Num 0 1 2 I 3 4 5 6 7 8 9 10 II 11 12 13 14 15 Bit Number 1 to 8 1 C1 0 C2 0 C3 0 C4 0 C1 0 C2 0 C3 E C4 E 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 4 1 Sa41 1 Sa42 1 Sa43 1 Sa44 1 Sa41 1 Sa42 1 Sa43 1 Sa44 5 1 Sa51 1 Sa52 1 Sa53 1 Sa54 1 Sa51 1 Sa52 1 Sa53 1 Sa54 6 0 Sa61 0 Sa62 0 Sa63 0 Sa64 0 Sa61 0 Sa62 0 Sa63 0 Sa64 7 1 Sa71 1 Sa72 1 Sa73 1 Sa74 1 Sa71 1 Sa72 1 Sa73 1 Sa74 8 1 Sa81 1 Sa82 1 Sa83 1 Sa84 1 Sa81 1 Sa82 1 Sa83 1 Sa84
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Quality Level Unknown Reserved ITU Rec G.811 Reserved SSU-A (Was G.812 Transit ) Reserved Reserved Reserved SSU-B (Was G.812 Local ) Reserved Reserved SETS Reserved Reserved Reserved Do Not use for synchronisation
SSM Allocation Definitions for E1 From G.704 10/98 Table 5C Note 1: n = 4,5,6,7 or 8 ( ie one Sa bit only ) depending on operator selection
E1 Time Slot 0 (TS0) Multi-Frame (MF) (SMF = Sub Multi-Frame ) - From G.704 10/98 Table 5D
Synchronization Status Message Carriage DS1
F-Bit
Fram Payload e
Bit 1 Bit 2 Bit 3 -------------------------------------------------------- Bit 192 Bit 193 --
DS1 Frame - 193 byte 125 us
G.811 G.812 Type II G.812 Type III G.812 Type IV Stratum 4 (Note) G.813 Option 3 G.812 Type V Synchronization Traceability Unknown Do not use for Synchronization Provisionable
11111111 00100000 11111111 00110000 11111111 00111110 11111111 00001000 11111111 00010100 11111111 01000100 11111111 00011110 11111111 00010000 11111111 00001100 11111111 00000010
Assigned SSM in DataLink acc G.704 10/98 Table 2, ANSI T1.403 Table 4, Bellcore GR-253 CORE (12/97), Sect 5.4.2. Note:All messages have the form 11111111 0 P1 P2 P3 P4 P5 P6 0 So each is one code of a basic 6 bit message
ESF Frame Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FPS 0 0 1 0 1 1
F-Bits CRC6 C1 C2 C3 C4 C5 C6 -
FDL m m m m m m m m m m m m -
Each F-Bit occurs in Bit 1 of each frame FPS = Framing Pattern Sequence (001011) CRC6 = CRC6 word C1 to C6 FDL = Facility Data Link, m = FDL bit
SSM-Based Network Resynchronization Flow
PRC - ST1 G.811
NE
NE
NE
NE
BITS ST2 G.812
NE
SSM carriage. Value = G.811 / Stratum 1
PRC FAIL
PRC - ST1 G.811
NE
NE
NE
NE
BITS ST2 G.812
NE
SSM carriage. Value = G.812 / Stratum 2 Timing direction
SSM - Network Synchronization Reconfiguration
NE 2
DUS ST1 DUS ST1 ST1
Primary Secondary
NE 1 PRC G.811 NE 2
DUS ST1 DUS ST1 DUS ST1 ST1 ST1 ST1 LOS
NE 1
PRC G.811
DUS
NE 3 NE 3
ST1
NE 4
ST1
NE 5
NE 5
DUS
All info before failure. THEN X happens

DUS ST1 ST1 DUS SMC LOS ST1
NE 4
DUS
DUS ST1 SMC
LOS
NE 4
NE 5
DUS
NE 4
1. NE 1, 2, 3 cfgd so if P&S = same, use Secondary for timing. 2. NE 4,5 cfgd so if P&S = same, use Primary for timing.
SSM Definitions : DUS: Do not Use for Synchronization ST1: Stratum 1 SMC: SONET Minimum Clock
Mobile Wireless Synchronization Requirements

Overview of sync requirements for cellular/mobile access networks: Clock rate synchronisation: Deviation of base station clock rate (= clock frequency) needs to be within certain limits from reference clock present in central radio control. Time or phase synchronization: Offset of base station clock phase (or time offset) needs to be within certain limits from reference clock phase (or time) present in central radio control. Sync required to ensure seamless connection hand-over of handsets moving between coverage areas of different base stations TDD (time division multiplex) requires both clock rate and phase/time synchronization to reference clock. Spectrally efficient. FDD (frequency division multiplex) requires only clock rate synchronization to reference clock. Spectrally inefficient. Classification of international mobile radio systems: CDMA2000 (3GPP2, US ,Asia): TDD system with a 50ppb frequency sync and time/phase within +/- 1.25us WCDMA (3GPP, Europe ME, Asia) and GSM: FDD system with a 50ppb frequency and no particular time/phase requirement & TDD system with a 50ppb frequency sync and time/phase within +/- 1.25us Pico RBS (WCDMA and GSM): FDD 100ppb frequency and no particular time/phase requirement
Break time
Coffee Break, standup and walk around, make your calls and eat lunch
Next Generation Networks are Packet Networks
Does synchronization change in Packet Networks?

Firstly the definition of and performance requirements for synchronization will not change. In Packet networks synchronization will become an access or last mile service aide to delivery of traditional services. In this model the service being delivered will determine the quality of synchronization required.
The financial drive to switch to a shared transport versus dedicated transport is overwhelming.
The ratio in cost per megabit for native ethernet backhaul service versus traditional private line service is 1 to 6 or greater.
A Financial Example
Traditional Leased Line Access pricing model;
Assumed 100Mbps of an STM1 is used at RNC and 3xE1 at each Node B (giving 17 Node Bs in RNS). Assumed distance between RNC and provider network POP to be 5 miles, and average distance between provider network POP and Node Bs to be 5 miles. Then, yearly rental costs: RNC: 100,295 + 18,000 Node Bs: 100M/E1 x (4098 + 1000 + 1192) Total annual cost:
= 118,295 = 314,500 = 432,795
Simple Ethernet Backhaul pricing model;

Assumed 100Mbps Ethernet at RNC: Assumed 6Mbps Ethernet at each of 17 Node Bs: Total annual costs: Potential ANNUAL SAVING : 17 x 2600 = 14,000 = 44,200 = 58,200
432,795 - 58,200 = 374,595.
($700k, E560k)
NOTE - While this is an example and cannot be promised by Semtech, it provides a glimpse into the new paradigm of cost structure for mobile wireless network backhaul services.
Synchronization Currency in Packet Networks

PRC (Cs) G.811
100us 50ppb freq alignment Minimum Node B FDD performance
SECs (Quartz) E1 G.813
10us
G.823 Traffic
SSU (Rb) G.812 Packet Network
1us
G.823 Sync SEC SSU PRC

Minimum node B TDD +/-1.25uS adjacent node phase alignment 1,000s 10,000s 100,000s
}
SDH
E3
100ns
SECs (Quartz) G.813 SSU (Rb) G.812
10ns 100ms 1s 10s 100s
E1
G.823 (Traffic) G.823 (Sync)
Obs. Interval (sec)

2.5us phase tolerance (TDD) Requires GPS to achieve Phase alignment BTS/NodeB (50ppb) BTS/NodeB (50ppb)
PLL
CDR
Framer
Alternatives for Synchronization Delivery over Packet Networks
Can circuit emulation services solve the Packet Backhaul synchronization problem? What are circuit emulation services anyway?
What is Circuit Emulation in Generally understood Terms
Circuit emulation is the process of packetizing bit stream services like a T-1, E-1 for transmission over a packet network. The network can be native Ethernet or Ethernet trunks between MPLS nodes. There are several standards for CES. The IETF has one called PWE3. The Metro ethernet forum has one called CESoE. The ITU has the SAToIP or USAToIP. They all take in a bit stream and create a packet stream and they are point to point.
Timing in Circuit Emulation Services

External Timing Reference CES IWF Data Clock
1588
TDM EXT line
Tx To & From Metro Ethernet Network Rx
IWF Processor
Data Clock
FR Eth line
SDiwf
MEF 3 Figure 13 : CES IWF Sync. Ref. Model

TDM Line: line-timing, from CE EXT: From BITS/SSU
Timing in Circuit Emulation Services Adaptive Clocking
Data
TDM service
Pktr Fr Clk. Rec. Inter-working Function
TDM DPktr service Fr Clk. Rec.
Data
Clk. Rec.
Mpll
Fs
Fs
Customer Premises Equipment
Inter-working Function
Adaptive-clocking can provide line-timing. Goal is to match the ingress service clock Fs, to the egress Fs while maintaining G.823 MTIE Adaptive-clocking has problems when :
- packet-loss rate significant - packet delay variation significant - path delay changes due to network reconfiguration or restoration
Timing in Circuit Emulation Services Network Clocking Network clocking uses a common network clock at each end of circuit:
Data
TDM service
Pktr
TDM DPktr service Fr
Data
Clk. Rec.
Mpll
Fs
Fs
Network Clock
Network-clocking has been providing line-timing (or external timing!) to NEs since the dawn of digital networks. Can still be used at end-points of Packet Networks. Noise is kept to G.823 limits by existing Network Clock distribution But network operators want to replace the TDM links with packet links:
Will just Circuit Emulation of G.823 Traffic do the job?

+/-50 ppb freq. Data CES PSN IWF
RNC
CES IWF 2.5us allowance IWF
CES
G.823 Traffic ports: CES is point to point so an ethernet path for each link is necessary G.823 service is frequency only so can only be used in FDD service To keep frequency transient below 50ppb needs a 20,000-second time constant for each millisecond of delay change (needs expensive, ultrastable OCXO)
G.8261 says CES impractical as a timing-transport mechanism using G.823 Traffic ports
Ethernet Transporting Synchronous Network Services?
Metro Ethernet Packet Network
Real Time Service such as node B backhaul traffic

Voice & Data Video
Real Time service such as node B traffic

Voice & Data
Node B Native Ethernet is an Asynchronous Service!
RNC
Video
Use a GPS receiver at every node to Synchronize the Network?
GPS Receivers GPS Receivers
GPS Receiver
GPS Receiver
Voice & Data Video
Voice & Data
Node B
RNC
Video
This is a very expensive to install and operate. Typical GPS receiver with High precision holdover oscillator is $500.00 USD +. Antenna installation is typically $$thousands$$ of USD and requires annual calibration.
Use a free run oscillator at every node to Synchronize the Network?
Precision free run oscillators
Free run oscillator
Free run oscillator
Voice & Data Video
Voice & Data
Node B
RNC
Video
This will not work unless the oscillators are caesium beam type which Typically cost $50,000.00 each.
Impairments Packet Networks Present to Synchronization? Most importantly traditional clock path continuity, the circuit, is broken due to Ethernets asynchronous timing. Line recovered timing with PRC traceability does not exist! In layer 3 IP networks the bi-path symmetry at any point in time is unknown and can change via route flap or RIP, BGP, or IS-IS mandated changes? The ITU in G.8261 has stated layer 3 networks are un-fit for circuit emulation services or cell site backhaul. Every packet is delayed by a differing amount of time as it passes through packet network switch queues. The result is a self-similar or fractional Brownian distribution model of PDV or Packet Delay Variation. There are 2 factors at play, switch queue depth and serialization delay.
Techniques for Synchronization over Packet Networks

The IETF has an RFC named Pseudo-wire emulation end to end, or PWE3. This RFC deals with encapsulation and transport of any circuit based service over an MPLS network. Everything from the basic T/E1 circuit emulation to ATM vc/vp emulation and VLAN emulation is included in this, except sync! The ITU-T standard G.8261 deals with delivering pseudo-wires over packet networks targeting the MTIE traffic mask for G.823. This standard does not cover delivering the MTIE sync mask for G.823 required for node B and BTS operation. A standard for Synchronous Ethernet does NOT exist as yet. This will eventually lead to pre-standard products in 2009 and the earliest.
Standards Bodies Activities
ITU meeting this week in Geneva is modifying G.8261 for the third time to include IEEE 1588. The draft standard for Synchronous Ethernet is to be completed at this meeting. Will take years for deployment.
There are 2 elements to this modification. First is the replacement of the 100ppm crystal on the PHY. Second is the slow protocol to carry the SSM like information for clock quality definition.
Semtech is contributing the concept of network profiles as a means of determining traditionally synchronous services delivery over packet networks.
Measuring each path is useless as networks changes continuously.
IEEE-1588 A Standard for Delivering Sync
What is IEEE 1588?

Originally developed by Agilent Technologies for the Test and Measurement community. V1 Approved by the IEEE-SA Review Committee on September 12, 2002 Published as IEEE 1588-2002 on November 8, 2002 Approved as IEC standard IEC 61588 on May 21, 2004 1588 V2 is Telecom friendly and WG draft standard spec is out to ballot on June 7th.

What does IEEE 1588 do? Official Title is Precision Time Protocol IEEE 1588 is a protocol originally designed to synchronize real-time clocks in the nodes of a distributed system that communicate using a network. IEEE 1588 calls for the use of the physical layer for timestamp inclusion.
NETWORK
Implementing IEEE 1588 Synchronization for UTRAN over Packet Networks?

IEEE 1588 Sync Master Packet Network
Interworking function
IEEE 1588 Sync Slave #1
Voice & Data Video
Interworking function
IEEE 1588 Sync Slave #2
Voice & Data
Node B
RNC
Video
IEEE 1588 delivers a precise copy of the Network Clock to each end point to enable Real time service & VoATM packets via some Circuit Emulation Services Technique
Network Timing Distribution using IEEE1588 IEEE 1588 V2 (IEC61588) Precision Time Protocol Distributes time and frequency via WAN ethernet with expected end point time alignment precision measured in nanoseconds. Gets UTC to the network elements and node b without GPS Distributes the network clock to ingress and egress points of interworking function with frequency precision of <1ppb.
GPS satellite
1588 Master Locked to GPS
NE
1588 Slave
NE
1588 Slave
NE
1588 Slave
NE
Ethernet
WiMAX
EoLOS Rradio

How does IEEE 1588 work? IEEE 1588 distributes a time base around a network using a twoway time transfer technique. Precise Frequency, Time and Phase can be generated. V2standard has Master, Boundary, Transparent and Slave clocks IEEE 1588 uses a Master Slave Hierarchy to distribute the time base. Slave Clocks are simple if Boundary Clocks and transparent are used, but there are no Boundary Clocks in a Telecom Network, This means the Slave Clocks become complex.
IEEE-1588-V2 A Standard for Delivering Sync
IEEE-1588 Code Network protocol stack & OS Sync detector & timestamp generator Physical layer
Master clock sends: 1. Announce message
Time at which a Sync message passed the Timestamp Point
Timestamp Point
Slave clock receives: 1. Announce message
Time at which a Sync message passed the Timestamp Point
Timestamp Point
Slave clock sends: Delay_Req message
Time at which a Delay_Req message passed the Timestamp Point Timestamp Point
Master clock receives: Delay_Req message Master clock sends: Delay_Resp message
Time at which a Delay_Req message passed the Timestamp Point Timestamp Point
IEEE-1588 Standard for Delivering Sync Synchronization computation in the Slave clock
Offset = receipt time precise sending time one way delay (for a Sync message) One way delay = {master to slave delay + slave to master delay}/2 (assumes symmetric delay) Master to slave delay = receipt time precise sending time (for a Sync message) Slave to master delay = Delay Request receipt time -precise sending time (of a Delay Request message) From this offset the slave corrects its local clock!
BUT: The standard says nothing about how to do this!
Real-World Experience:
Since April 2005, Semtech and Agilent and recently Symmetricom have been running a field trial on a live Public Metro Ethernet Network owned and operated by a major carrier. Agilent and Symmetricom provided the reference and measurement equipment. TIE data is gathered for every 24 hour period and analysed to get MTIE, TDEV and Frequency Offset. Semtech provided two ToPSync Evaluation boards to act as IEEE 1588 Master and Slave The Master and Slave are test-beds for 1588v2 concepts. The Master sends 1 Announce message every 2 seconds. The Slave sends 24 Delay-Request messages every second. The cost of sync in this test is 20kbps.
Arrangement of Field Trial

Public MPLS Packet Network To Semtech To Agilent VLAN #2
Atomic Clock
ToPSync Slave #2 20 km from master
VLAN #1 10MHz Master Agilent OmniBer 718

10MHz
ToPSync Slave #1 45 km from master
DS1
Packet delays seen on the Metro Ethernet Network
Single trip delays
Round trip delay
MTIE compared to ITU G.823 PDH Sync Interface allowance
TDEV compared to ITU G.823 PDH Sync Interface allowance
MTIE compared to ITU G.811 PRC allowance
TDEV compared to ITU G.811 PRC allowance
TCXO Slave MTIE compared to ITU G.823 PDH Sync allowance
TCXO
OCXO
Sprint Network Slave to Slave 1PPS Alignment
Nortel lab tests of Disciplined IEEE1588

PBT with high priority CES traffic load
Medium step load 1h40mins
0%
90ns/1000s (205ns ref. T1 g.823 sync) back-to-back 11ppb > back-to-back
23% 57% 68% 80% 91% 97% 0%
23% 80% 63%
Nortel lab tests of Disciplined IEEE1588 PBT with high priority CES traffic load
Large step load Held 9 hours 600ns/1000s (1s ref. T1 g.823 sync) back-to-back Still under G.8261 mask 11ppb > back-to-back
97% 57%
0%
80%
91%
68%
Semtech ToPSync Slave Output Frequency Accuracy over ADSL

ADSL1 Alcatel UD with ADLT-N Linecard. Simulated Line length = 2500 metres. Bandwidth = 0.224 Mb/s upstream, 3.552 Mb/s downstream. Interleaved path ACS9590T locked the frequency accuracy achieved never exceeds 60ppb.
Fractional Frequency Offset - Norway Test 4, TCXO
2.00E-07 Fractional Frequency Offset 1.50E-07 1.00E-07 5.00E-08 0.00E+00 0.00E+00 -5.00E-08 -1.00E-07 -1.50E-07 -2.00E-07 Time(s)
2.00E+03
4.00E+03
6.00E+03
8.00E+03
1.00E+04
1.20E+04
1.40E+04
Semtech ToPSync Slave Output Frequency Accuracy over ADSL

ADSL2+ Alcatel UD with ABLT-F Linecard. Simulated line length = 2500 metres. Bandwidth = 0.182 Mb/s upstream, 4.578 Mb/s downstream Interleaving enabled, which gives a maximum interleaving delay 16 msec. ACS9590T locked frequency accuracy achieved never exceeds 50ppb
Fractional Frequency Offset - Norway Test 4, TCXO
2.00E-07 Fractional Frequency Offset 1.50E-07 1.00E-07 5.00E-08 0.00E+00 0.00E+00 -5.00E-08 -1.00E-07 -1.50E-07 -2.00E-07 Time(s)
2.00E+03
4.00E+03
6.00E+03
8.00E+03
1.00E+04
1.20E+04
1.40E+04
Packet Timing Application Areas

Consumer
Femto Cell Residential Ethernet (802.1AVB)
TopSync Value Proposition
Mobile Wireless Backhaul
Wireline Access Aggregation
WiMAX Backhaul/Access
Network
Typical Node B System Design Architecture for IEEE 1588 Timing
GbE/FE Interfaces
Network Processor Network Processor

1588 PTP Packets
GbE/FE Interfaces
MII ports
Reference Clocks
ToPSyncTM
Timebase Generating Engine Processor running Proprietary Algorithms DDS Process Stratum 3 G.812, G.813, GR-1244 Line Clocks
SPI
TCXO (S3) OCXO (S3E)
SRAM
What is the Future of Network Synchronization?
Networks of tomorrow will use the most cost effective, manageable and reliable technique fitting the service model. Trunk networks will use traditional BITS based systems. Metro networks will use a combination of traditional systems and synchronous Gigabit ethernet. Access networks endpoints and wireless service delivery points will use IEEE 1558 V2 or some other packet based synchronization.
How can Synch Influence OPEX?
Enable UTRAN nodes to use lower cost backhaul technologies such as ADSL and ethernet versus PDH or SDH/SONET. Eliminate the need for expensive GPS holdover oscillators and antenna installations for low cost WiMAX in-building and outdoor basestations as well as for picoCDMA basestations. Intelligent layer 2 sync end point systems can have SNMP capability to allow the viewing of sync performance in real time remotely, no wasted truck roles for sync problems! Layer 2 synchronization techniques such as IEEE 1588 V2 use the existing infrastructure and are only required at the ends.
The Future for Sync?

Several possibilities exist for changing the way todays synchronization clocks and time bases are transmitted from source to sink via packet networks without damage to the integrity of the synchronization information itself.
IEEE 1588 permits easy timing distribution of the network clock over a packet infrastructure with a very low cost per sync stream. Standard NTP is not accurate enough for real-time applications and was not developed for this purpose. IEEE 1588 enables native ethernet backhaul for synchronous and time-based services. IEEE 1588 and circuit emulation services are NOT opposing or competing technologies.
Summary
We are migrating from a TDM network to packet network, but still need to support TDM services. Interworking Functions have been defined and offer many clocking schemes. The only clocking scheme which allows the Public Switched Network to extend to the Customer Premise and meets the timing requirements, is IEEE 1588. Experience with a long-term IEEE 1588 field trial shows that excellent long term viability, accuracy and stability is consistently available on an evolving Metro ethernet. Future services could be based on time rather than frequency. IEEE 1588 delivers time as well as frequency.

49 Semtech

Transféré par

Informations du document

Description originale:

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

49 Semtech

Transféré par

Droits d'auteur :

Formats disponibles

Network Synchronization Tel Aviv Israel June 14, 2007

Semtech Patrick Diamond PhD Director Systems Engineering

Semtech Patrick Diamond PhD - Director Systems Engineering

Basic System Reference Clock Architectures

Semtech Patrick Diamond PhD - Director Systems Engineering

Semtech Patrick Diamond PhD - Director Systems Engineering

Semtech Patrick Diamond PhD - Director Systems Engineering

Semtech Patrick Diamond PhD - Director Systems Engineering

ITU Synchronization Standards

Semtech Patrick Diamond PhD - Director Systems Engineering

ANSI Synchronization Standards

Semtech Patrick Diamond PhD - Director Systems Engineering

Synchronization Clock Quality Distribution Rules

Semtech Patrick Diamond PhD - Director Systems Engineering

Synchronization Distribution Hierarchy

Semtech Patrick Diamond PhD - Director Systems Engineering

Synchronization Currency in Todays Circuit Transport Networks

SECs (Quartz) E1 G.813

SSU (Rb) G.812

G.823 Sync SEC SSU PRC

SECs (Quartz) G.813 SSU (Rb) G.812

10ns 100ms 1s 10s 100s 1,000s 10,000s 100,000s

Obs. Interval (sec)

Semtech Patrick Diamond PhD - Director Systems Engineering

SETS - Functionality as Defined by ITU Standards

Semtech Patrick Diamond PhD - Director Systems Engineering

Synchronization Solution - Upstream / Downstream

Network Input SEC References

Line Card DS1

Line Card 622M

Line Interface 2 SETS Clock Generator Slave Line Interface N

SEC MFrSync Line Card 2.5G

SSM Input Reference Source Selection Priorities

Semtech Patrick Diamond PhD - Director Systems Engineering

Traditional Home Grown SETS Implementation

Low Pass Filter

MC68xx16 ADC uP Digital Filter, Temperature Compensati on,Control ADC

Low Pass Filter

DSP uP runs complex, proprietary algorithm

Sensitive analog circuitry needs special care in layout

Semtech Patrick Diamond PhD - Director Systems Engineering

Oscillator Performance Requirements

Stratum3 GR1244-II G.813

Stratum 3E GR1244-III G.812

ppm ppm ppm

4.6 4.6 0.37 0.28 0.04 0.05

4 4.6 + 4.6 1-10 (3) 0.01

4 4.6 + 4.6 0.001 0.01

2 4.6 + 4.6 1-10 0.01

Semtech Timing Technology for Traditional Chassis

Sync A (Optional) Clock B

High Rate Line Card With

ACS85xx Recovered Clock LC/P

Data SERDES Clock Distribution Framer Clock Data SERDES

Recovered Clocks From Line Cards Data Monitors

ACS85xx SETS ACS85xx SETS

Priorities Monitors Config. Priorities Config.

Semtech Patrick Diamond PhD - Director Systems Engineering

ACS8520/22/30- Two independent PLL paths for ITU Compliance

Two PLLs, known as the T4 & T0 path are completely independent

The T4 path is to select a clock to output to a local BITS or SSU

T4 Path SSU T0 Path

Semtech Patrick Diamond PhD - Director Systems Engineering