INTRODUCTION

A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing a set of partial products, and then summing the partial products together. This process is similar to the method taught to primary school children for conducting long multiplication on base-10 integers, but has been modified here for application to a base-2 (binary) numeral system. The first stage of most multipliers involves generating the partial products which is nothing but an array of AND gates. An n-bit by n-nit multiplier requires n2 AND gates for partial product generation. The partial products are then added to give the final results.

WALLACE TREE MULTIPLIER

The Wallace tree has three steps: Multiply (that is - AND) each bit of one of the arguments, by each bit of the other, yielding results. Depending on position of the multiplied bits, the wires carry different weights, for example wire of bit carrying result of is 32 (see explanation of weights below). 2. Reduce the number of partial products to two by layers of full and half adders. 3. Group the wires in two numbers, and add them with a conventional adder.
1.

It is based on the fact that a carry signal will be generated in two cases: The benefit of the Wallace tree is that there are only reduction layers, and each layer has propagation delay. As making the partial products is and the final addition is , the multiplication is only , not much slower than addition (however, much more expensive in the gate count). Naively adding partial products with regular adders would require From

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a complexity theoreticperspective, the Wallace tree algorithm puts multiplication in the class NC1. These computations only consider gate delays and don't deal with wire delays, which can also be very substantial. The Wallace tree can be also represented by a tree of 3/2 or 4/2 adders.

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Figure 1:The algorithm for multiplication performs by wallace tree multiplier

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COMPONENTS USED
Software For doing this project, the software which is used is Cadence, and the processes are carried out using 0.35 m technology. Devices Used The devices which are used for the project are as follows:

AND, HALF ADDER FULL ADDER cell taken from CORELIB Voltage source(Vdc), Ground(gnd) and Vdd, taken from Analoglib.

SCHEMATIC IN CADENCE

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Here is shown the figure is the schematic of Wallace tree multiplier done in Cadence.

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Here is shown the figure is the gate level schematic of AND done in Cadence.

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Here is shown the figure is the gate level schematic of full adder done in Cadence.

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Here is shown the figure is the gate level schematic of half adder done in Cadence.

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LAYOUT
Here is shown the figure is the layout of half adder done in Cadence.

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RESULTS
The graph below shows the input bits that are applied to the Wallace tree multiplier.

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The graph below shows the input bits that are applied to the Wallace tree multiplier.

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The graph below shows the output bits that are applied to the Wallace tree multiplier.

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The graph below shows the output bits that are applied to the Wallace tree multiplier.

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CONCLUSION
The wasted area problem of large Wallace tree multipliers can be solved using a new method of tree construction. The modified tree has a slightly smaller critical path but a slightly larger wiring overhead.

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REFERENCES
M.M.Mano and C. R. Kime, Logic and Computer Design Fundamentals, Pearson/Prentice Hall, Upper Saddle River, NJ, 2004. http://en.wikipedia.org/wiki/Wallace_tree

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