Agenda: Day One

DAY 1
Unit 0i 1 2 3 4 Register to Register Paths Welcome Introduction to Static Timing Analysis Writing Basic Tcl Constructs in PT Reading Data Constraining Internal Reg-Reg paths Lab

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Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Unit Objectives

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After completing this unit, you should be able to:

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Use a 3 step flow to read design(s) into PT memory Resolve errors and warnings associated with reading and linking a design Access design objects after a design has been read into PT memory

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

The Inputs and Outputs of PrimeTime

Gate-Level Netlist Setup File
Read at PT invocation

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Constraints
source

Exceptions

read_db read_verilog read_vhdl

source

Technology Libraries
Loaded at linking

PrimeTime

Reports Log File

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Constraint Script

Reading Data PrimeTime: Introduction to Static Timing Analysis

The PrimeTime setup file is .synopsys_pt.setup. Constraints and Exceptions are usually placed in script(s).

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Five Step Static Timing Analysis Flow

READ READ CONSTRAIN CONSTRAIN EXCEPTIONS EXCEPTIONS CHECK CHECK ANALYZE ANALYZE
Our Focus

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Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

PRIMETIME Interfaces
Two ways to interface to PrimeTime (PT)
primetime PT GUI Command line shell PRIMETIME (PT) Engine

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pt_shell

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Primetime only accepts Tcl mode.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Three Steps to Read Your Data into PT

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Three steps to read in the required design(s):

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Set Variables:
l l

search_path link_path

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Read Design Resolve References (Link design)

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

1: Set the search_path Variable

Synonymous with UNIX path variable
ProjectX/ db/ tech_lib.db projectX.log blockA.db blockB.db blockC.db vlog/ top.v blockD.v blockE.v Tom/ uart.db scripts/ top.pt proc1.pt proc2.pt

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set search_path $search_path db vlog scripts

printvar search_path
Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

What is a search_path? search_path contains a list of paths used to locate the designs, libraries and other files needed to perform STA. search_path variable usually includes paths to: Design Database(s) Timing Model(s) Technology Library Constraint files These two commands have the same effect: set search_path $search_path db vlog scripts. # lappend search_path db vlog scripts lappend search_path db vlog scripts The default value of search_path is empty string .

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Unit 3: Reading Data

1: Set the link_path variable

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The Link Path specifies where PT searches for designs and library files when linking the design:

set link_path {* tech_lib.db rams.db}

Link Path PT Memory * Technology + Library Custom Conditions IP Cores

During linking, PT will search (in sequence) the:

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PT Memory (*) Library file tech_lib.db IP core rams.db

printvar link_path
Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

link_library = link_path. Design Compiler uses link_library, PrimeTime uses link_path. These two commands are equivalent: set link_path {* core_slow.db rams.db} lappend link_path core_slow.db rams.db

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

2: Manually Read Design(s) into PT

top
U33

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blockA
U21 INV U4

blockB

pt_shell> read_db top.db pt_shell> read_db blockA.db pt_shell> read_db blockB.db OR pt_shell> read_db blockA.db blockB.db top.db

What is the current_design in each case?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

The last design read is the current design by default. You can make another design current with the current_design command. In the above example of 2 cases, the current designs are blockB and top respectively.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

2: Read Sub Designs Automatically

ProjectX/ db/ tech_lib.db projectX.log blockA.db blockB.db blockC.db vlog/ top.v blockD.v blockE.v Tom/ uart.db scripts/ top.pt proc1.pt proc2.pt

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pt_shell> read_verilog top.v pt_shell> link_design TOP

What should the search_path be?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Top.v is in the vlog directory, search_path should have this directory. Designs blockA.db AND blockB.db are in the DB directory; search_path should also have this directory.

set search_path ./vlog ./db

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Unit 3: Reading Data

2: Read Designs in Different Formats

top
U33

3-11

blockA
U21 INV U4

blockB

pt_shell> read_verilog top.v pt_shell> read_db blockA.db pt_shell> read_vhd blockB.vhd

Can you mix netlist formats? How does it work?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Example 1: Read Problem

set search_path $search_path db vlog scripts set link_path * tech_lib.db
ProjectX/ db/ tech_lib.db projectX.log blockA.db blockB.db blockC.db vlog/ top.v blockD.v blockE.v Tom/ uart.db scripts/ top.pt proc1.pt proc2.pt

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pt_shell> read_db uart.db Error ! Error: Cannot read file uart.db Error: Problem in read_db: No designs were read.

How would you fix this read problem?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Example 2: Read Problem

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set search_path $search_path db vlog scripts set link_path * tech_lib.db

ProjectX/ db/ tech_lib.db projectX.log blockA.db blockB.db blockC.db vlog/ top.v blockD.v blockE.v Tom/ uart.db scripts/ top.pt proc1.pt proc2.pt

pt_shell> pwd /../ISTA/ProjectX pt_shell> cd scripts pt_shell> read_db blockA.db Error: Cannot read file blockA.db

Error !

How would you fix this read problem?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

3: What is Resolving References?

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U33

RISC_CORE

What is INV?
BLOCKA U4 U21 INV BLOCKB

Where is BLOCKB?

How will PrimeTime know what each instance in RISC_CORE design netlist refers to?
Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Resolving references (aka link) means finding and replacing the space holders with the actual library cells or sub designs referenced.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

3: Link the Design to Resolve References

The link_design command:
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Resolves all references in a design using the link_path variable:

l

If it fails, it will use the search_path variable to resolve references

Reads the technology library if not already read in

What are blockA, blockB, and INV?

U33

top

blockA
U21 INV U4

blockB

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

link = link_design. Design Compiler (DC) uses link while PrimeTime (PT) uses link_design command to link a design. For convenience, PT has built-in alias link for link_design. Q: What happens if you accidentally try to link the same design that has been previously linked? A: If you originally used -remove_sub_designs then, black boxes will be resulted since sub design references could not be found in the memory (*). Solution: - Use the link -incr option (OR) - Remove the (corrupted) design in memory and start over from read again (Recommended).

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Example: Linking a Design

set search_path $search_path db vlog scripts set link_path * tech_lib.db
ProjectX/ db/ tech_lib.db projectX.log blockA.db blockB.db blockC.db vlog/ top.v blockD.v blockE.v Tom/ uart.db scripts/ top.pt proc1.pt proc2.pt

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top
U33

blockA
U21 INV U4

blockB

pt_shell> pt_shell> pt_shell> pt_shell>

read_db blockA.db blockB.db read_verilog top.v current_design top link_design

Where are the references found during linking?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PT found blockA.db and blockB.db in its memory and INV in the library. After linking, if current_design is set to a different design, all the previously established link information will be gone. PT automatically reads in Library file(s) when link_design is executed.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Example: Link Warning

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pt_shell> read_db CLOCK_GEN.db pt_shell> link_design pt_shell> link Linking design CLOCK_GEN... Linking design CLOCK_GEN... Warning: Unable to resolve reference to 'MUX21L' in 'CLOCK_GEN'. (LNK-005) Warning: Unable to resolve reference to 'MUX21L' in 'CLOCK_GEN'. (LNK-005) Warning: Unable to resolve reference to 'IVI' in 'CLOCK_GEN'. (LNK-005) Warning: Unable to resolve reference to 'IVI' in 'CLOCK_GEN'. (LNK-005) Warning: Unable to resolve reference to 'FD2' in 'CLOCK_GEN'. (LNK-005) Warning: Unable to resolve reference to 'FD2' in 'CLOCK_GEN'. (LNK-005) Creating black box for U31/MUX21L... Creating black box for U31/MUX21L... Creating black box for U32/MUX21L... Creating black box for U32/MUX21L... Creating black box for U34/IVI... Creating black box for U34/IVI... Creating black box for U35/IVI... Creating black box for U35/IVI... Creating black box for CLK_BY_2_reg/FD2... Creating black box for CLK_BY_2_reg/FD2... Designs used to link CLOCK_GEN: Designs used to link CLOCK_GEN: <None> <None> Libraries used to link CLOCK_GEN: Libraries used to link CLOCK_GEN: <None> <None> Design 'CLOCK_GEN' was successfully linked. Design 'CLOCK_GEN' was successfully linked. 11

WHAT!

Verify link_path and search_path

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Primetime create black boxes for unresolved references. This is because the link_create_black_boxes variable is set to true by default.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Black Boxes with link_design

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If link_design could not resolve a particular reference, PT will create black boxes A black box is an empty cell with no timing arcs
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The variable link_create_black_boxes is true by default:

l l

Substitute unresolved references with black boxes Design is linked and timing analysis can be performed

Set the variable link_create_black_boxes to false:

l l l

Unresolved references, cause a design to remain unlinked Most timing analysis commands will not function Fix any problems and re-link the design

What command would you use to set this variable to false?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

set link_create_black_boxes

false

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Test For Understanding

Name three design netlist formats that PrimeTime accept?
l l l ___ ___ ___

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Linking a design involves the use of:

a) _________________ and b) _________________ variables

What is the purpose of linking a design?

____________________________________________

What does * in the link_path mean?

____________________________________________

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Do You need to Set Variables Every Time? 3-20

Can you have search_path and link_path variables set automatically when you invoke PT?

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Create a .synopsys_pt.setup File

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set search_path $search_path db vlog scripts set link_path * tech_lib.db set sh_enable_page_mode true set sh_command_log_file projectX.log alias h history alias rc report_constraint -all_violators history keep 200
Within the setup file, you can:
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Create commands you want to execute every time PrimeTime is invoked, i.e. set search_path or set link_path Define aliases for interactive use Change log file name from its default pt_shell_command.log
Reading Data PrimeTime: Introduction to Static Timing Analysis

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Synopsys 34000-000-S16

history keep 200 specifies: the number of commands (200) to be retained in the history list. By default, only 20 commands are retained. You can control the naming of the Log file (default: pt_shell_command.log) via the variable: sh_command_log_file, but, it should appear inside the setup file (.synopsys_pt.setup) Example: set sh_command_log_file ./projectX.log. Do not source any script file in the setup file since it will increase invocation time and will make debugging difficult.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

PrimeTime Setup Files

2

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Users General Setup

~user

$SYNOPSYS/admin/setup .synopsys_pt.setup
1

~/.synopsys_pt.setup
3

Users Specific Project Setup Project_Directory ./.synopsys_pt.setup

Standard Setup

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime will read the .synopsys_pt.setup files from three directories (in the following order): 1. The primetime root directory, which contains the PrimeTime files. For example, if PrimeTime was installed under /tools/synopsys/PT, standard installation would include a setup file under /tools/synopsys/PT/admin/setup. 2. Once the standard setup file has been read in and executed, PrimeTime then searches for a setup file in the users login directory. If a setup file exists in this directory, it will be read in and executed. -- Warning: During project archiving (using tar -cvf) you need to think about it! 3. Last, PrimeTime will read in and execute the .synopsys_pt.setup file from the directory under which it was invoked. -- It makes life easier if this project specific setup file contains everything including the contents of your home directory setup file, if you have one -- recall the Warning above.

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Read/Link Problem Debug Check List

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Is PT invoked in the correct directory? Correct setup file? Is the design fully mapped to gate level instances?
l

No high level HDL constructs (such as if, case,...)

Are search_path and link_path variables set correctly?

l

printvar *_path

Are Black Boxes created for unresolved references?

l

set link_create_black_boxes false

Check Libraries in Memory & Library used:

l l

list_libraries list_libraries -used There can be only one linked design in PT memory
Reading Data

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PrimeTime: Introduction to Static Timing Analysis

Q: What happens if you accidentally try to link the same design that has been previously linked? A: If you originally used -remove_sub_designs , the result will be black boxes since sub design references could not be found in the memory (*). Solution: - Use the link -incr option (OR) - Remove the (corrupted) design in memory and start over from read again (Recommended).

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

How does PT Store My Design Netlist?

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Vocabulary of Design Objects

Design TOP Port U1
A B C D A B C D AIN BIN CIN DIN Q1 BUS1 U4 U2 BUS0 INV Q0 U3 INV INV0 D0 Q[1:0] OUT[1:0]

Cell

Net

INV1 D1 CLK REGFILE

Pin

Clock
CLK CLK

ENCODER

Reference and Design

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Here are some commands to access your design stored in PT memory: get_cells get_clocks get_nets get_pins ... all_clocks all_inputs all_outputs # Create a collection of all clocks in design # Create a collection of all input ports in design # Create a collection of all output ports in design # Create a collection of cells # Create a collection of clocks # Create a collection of nets # Create a collection of pins

all_registers # Create a collection of register cells or pins ..

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

What Information Is Found in the Library?

n n n n n n

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Units for time, capacitance, resistance List of library cells Cell Timing (propagation delay, setup, hold ...) Operating conditions Wire load model Design rules (max_capacitance, max_fanout ...)

list_libraries report_lib LIB_NAME

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

pt_shell> list_libraries Library Registry: * ssc_core_slow ./core_slow.db::ssc_core_slow pt_shell> report_lib ssc_core_slow **************************************** Report : library Library: ssc_core_slow Version: 2002.03 **************************************** Time Unit Capacitance Unit : 1 ns : 1 pF

Usually, library file is read in during link_design. You can also explicitly read in a library file using the read_db command: Example: read_db ssc_core_slow.db To remove all the designs and libraries from the memory: remove_design all remove_lib all NOTE: PT cannot remove a library if it is used by a design residing in memory.
PrimeTime: Introduction to Static Timing Analysis 3-25 Unit 3: Reading Data

Lab Overview
n
LAB

3-26
Given a set of design and library files, you will need to successfully read them into PrimeTime memory and access the design objects You will set the search_path and link_path variables correctly such that you can read:
l

45 min

A Top level Verilog/VHDL netlist and link using Verilog/VHDL sub blocks and the library A top level Verilog/VHDL netlist and link using DB sub blocks and the library A complete netlist in VHDL/Verilog/DB and library, link efficiently and access sevaral objects within the design

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data

Review

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Write 3 variable names that are used to read and link a design in PT:
________________________________________________ ________________________________________________ ________________________________________________

Write 3 command names that are used to read and link a design in Verilog format into PT:
________________________________________________ ________________________________________________ ________________________________________________

Reading Data Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

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Unit 3: Reading Data