Microwave/Millimeter-Wave Components

Low additive noise frequency tripler

Design of a frequency tripler is presented and its noise degradation, due to
the presence of additive noise of the multiplier, is measured and compared to
theoretical limits.
By Bogdan Sadowski

M any applications require a smaller fre-

quency to be converted to a higher one
by multiplication. But, frequency multiplica-
�� ��

tion inherently results in phase noise degrada-

tion at least by an amount of theoretical limit ���
as described by the equation:

∆LΦ[dB] = 20 log10 (N ) �� �������� ���

(1)
where: ∆LΦ[dB ] — phase noise degradation
in dB
— multiplication factor
Hence, it is desirable to use multipliers with
very low additive noise, and phase noise deg-
radation that approaches theoretical limits.
Often, odd-order multiplication is achieved
by limiting the input signal symmetrically for
both positive and negative half-waves—this in
turn reduces the level of even–order products
at the output of the multiplier.
In order to minimize AM-PM conversion
in such multipliers, the output signal should
have its zero crossings perfectly aligned with
zero crossings of the input signal[1].
Odd-order multiplier
In reference 2, Charles Wenzel had pro-
posed using a current-limiting switch to fulfill
such requirements and developed an original
odd-order diode multiplier[2]. To explain the
principle of operation, let’s consider first the
basic configuration of an analog four-diode
switch as shown in Figure 1.
Symmetry of the circuit is marked by the
dotted line, which also points to the virtual
ground for the balanced Uctrl voltage. Input
terminal (marked “IN” in Figure1) is driven
by the input voltage source ug (t) of internal
resistance Rg. Output terminal (“OUT” in
Figure 1) is loaded with load resistance RL.
Switch is in ON-state when dc control volt-
age Uctrl is applied with the polarity shown in
Figure 1 across the control terminals. Diodes
D1 and D4, as well as D2 and D3, are all
forward biased in this case. At the instance of
zero crossings of the input signal, i.e., ug (t)
= 0 V, diode bridge is perfectly balanced (if
all four diodes are identical) and there is no
��������
���
�� ��
Figure 1. Four-diode analog switch.
�� ��
� �
�� ���
�����
�� ��
� �
�� ��
Figure 2. Analog switch—equivalent circuit for control voltage.
current flowing in the load resistor RL. each diode is considered small as compared
To estimate the current flowing in the diode to R, Rg and RL.
D1 due to control voltage Uctrl, circuit is di-
vided into two halves along another symmetry For the case of u g (t ) ≠ 0V , the diode bridge
line (vertical) as shown in Figure 2. becomes unbalanced and output current flows
Due to the symmetry of the circuit, all in the load resistor RL as a result.
current flowing in the diode D1 also flows in Signal source (of internal resistance Rg)
the diode D4. driving the input (IN terminal in Figure 1)
Thus, dc (bias) current flowing in diode D1 produces ac current iD1(t) flowing in the diode
can be estimated as follows: D1 in the opposite direction (during its posi-
U − (2 ⋅ U F ) tive half-wave of the cycle) as compared to
I D1 =  ctrl  the direction of the bias current ID1.
 2⋅ R  (2) To estimate the current flowing in the
where: UF — diode forward voltage diode D1 due to signal source ug (t), circuit is
For simplicity, internal series resistance of divided into two halves along the symmetry

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 �� ��

���   2 ⋅ R ⋅ RL  
iD1 (t ) ⋅   (
 + 2 ⋅ Rg ) = u (t )
  R + (4 ⋅ RL )
g
���� ����  (6)
u g (t )
������ iD1 (t ) =
 2 ⋅ R ⋅ RL 
���� ����  (
 + 2 ⋅ Rg )
 R + (4 ⋅ RL ) (7)
�� ��� ��
The total current flowing in the diode
D1 in forward direction, iFD1(t), can be
Figure 3. Analog switch—equivalent circuit for the input signal.
expressed by:
iFD1 (t ) = I D1 − iD1 (t ) (8)
D1 D2
 
 
U ctrl − (2 ⋅ U F )  u g (t ) 
iFD1 (t ) =  − 
2⋅ R    2 ⋅ R ⋅ RL  + 2 ⋅ R

  ( )

  R + (4 ⋅ RL )
g


IN OUT
L (9)
Similarly, currents flowing in other diodes
can be analyzed.
The condition of being forward biased for
D4 D3 diode D1 will cease (and the diode will turn
off) when the instant value of current due to
signal source becomes equal (and opposite
in direction) to the value of dc “bias” cur-
Figure 4. Basic configuration of an odd-order multiplier.
rent forced by the control voltage (Uctrl)—in
other words, when the input signal reaches the
D1 D2 threshold value. When the input voltage ug (t)
is higher then the threshold value Ug threshold,
output current flowing in the load RL reaches
its limit and symmetrical clipping of the output
L1 current waveform occurs.
IN OUT
Lower values of the control voltage
(Uctrl) correspond to lower levels of the input
threshold voltage Ug threshold. Thus, to cause
L2 limiting of the output current at very low input
thresholds, condition Uctrl close to 2UF must
D4 D3 be reinforced. For that condition, clipping of
the output current occurs at instances close to
the zero crossing instances of the input signal,
which in turn, assures that AM-PM conversion
Figure 5. Odd-order multiplier—circuit symmetry. is kept minimal.
Going forward the same way, you may
line as shown in Figure 3. Current flowing in where: ug (t) — voltage of the signal want to dc-short control voltage terminals.
the diode D1 is a sum of currents flowing in source Dc-shorting of the control voltage terminals,
the resistor R/2 and in the branch consisting Rg — internal resistance of the signal with an inductor, aid operation of the analog
of diode D2 and resistor 2RL in series. For an source switch as an odd-order multiplier with low
ac current, the diode is modeled as a closed   additive noise due to the optimal alignment of
switch (internal resistance of the diode is   the input and output zero crossings. Inductance
again considered small as compared to R,  u g (t ) −  2 ⋅ Rg ⋅ (iD1 (t ) )  value should be chosen to be sufficiently large
iD1 (t ) =  
Rg and RL).   2 ⋅ R ⋅ RL   in order to present a high impedance at the
Current iD1(t) can be estimated as follows:   input signal frequency.
 R + (4 ⋅ RL )
 
  (4) Figure 4 shows basic configuration of such
 
  an odd-order multiplier.
  To better understand the principle of opera-
 
 u g (t ) −  2 ⋅ Rg ⋅ (iD1 (t ) )  tion, the inductor is split into two halves, L1 =
iD1 (t ) =  
   R  ⋅ 2 ⋅ R   L2, as shown in Figure 5, along the symmetry
 2 ⋅ R ⋅ RL 
   2
( )
L 

iD1 (t ) ⋅   = u g (t ) −  2 ⋅ Rg ⋅ (iD1 (t ) ) line (dotted line in Figure 5) and the virtual
  R  
    + (2 ⋅ RL )   R + (4 ⋅ RL ) ground point, between two halves of the induc-
   2   
(3) (5) tor, is connected to the signal ground.

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 During negative half-wave of the input
signal UIN, diode D1 is polarized forward,
D1 thus allowing current iL1 to flow in the induc-
tor L1. Energy stored in the magnetic field of
inductor L1 (during negative half-wave of the
i L1 input signal cycle) causes that the current of
the inductor does not cease immediately after
UIN L1 UL1 the polarity of the input signal has changed
(when positive half-wave of the cycle starts)
but continues to flow opposing the change
(Lenz’s law) until the input voltage UIN has
finally reached the level high enough to back-
ward polarize the diode D1 and shut-off the
current (Figure 6).
Figure 6. Rectifier/shifting circuit—building block of odd-order multiplier. As a result, dc level of the voltage UL1 is
shifted with respect to zero voltage reference
level. Value of the inductance L1 has to be
relatively large to provide sufficient energy
storage capacity. At microwave frequencies
self-resonance will have to be taken into
consideration, thus imposing an upper limit
�� �� on the inductance value.
Similarly, the circuit consisting of D4
and L2 could be analyzed. Figure 7 depicts
waveforms produced by two rectifier/shifting
��
�� ��� circuits. Remaining diodes of the quad (diodes
D2 and D3) perform the commutation of those
�� two waveforms to the output (OUT terminal
in Figure 7) to produce a square-wave (rich
�� �� in odd-order harmonics).

Inexpensive practical
implementation
Inexpensive 3 GHz to 9 GHz frequency
tripler was built to verify the noise perfor-
mance. Two pairs of series-connected diodes
from M/A-COM (MA4E2054B-287T and
Figure 7. Odd-order multiplier—waveforms.
MA4E2054D-287T) were used. Phase noise
plot of the tripler’s output signal at 9 GHz
as compared to phase noise plot of the input
signal at 3 GHz is shown in Figure 8.
-20
The noise degradation (due to the pres-
-30 ence of additive noise of the multiplier)
Input Phase Noise is significant only for offsets smaller then
-40 Theoretical Limit approximately 2 kHz. RFD
Output Phase Noise
-50 References
1. Richard A. Baugh, “Low Noise Fre-
-60 quency Multiplication,” Proc. 26th Annual
(dBc / Hz)

Symposium, Frequency Control, Atlantic

-70 City, 1972.
2. Charles Wenzel, “New Topology Multi-
-80 plier Generates Odd Harmonics,” RF Design
Awards, RF Design magazine.
-90
ABOUT THE AUTHOR
-100
Bogdan Sadowski is a senior RF engineer
-110 with Harris Stratex Networks (formerly
Microwave Communications Division of
-120 Harris Corp.) in Research Triangle Park,
100 10k 100k NC. His interests include frequency syn-
Offset (Hz) thesis and non-linear circuits. He can be
Figure 8.Input vs. output phase noise of 3 GHz to 9 GHz frequency tripler.
reached at bogdan.sadowski@ieee.org.

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