1. a) Design and implement Full Adder using logic gates and verify the Truth Table.

b) Design De-multiplexer using Verilog Hardware Description Language.

2. a) Design and implement Full Subtractor using logic gates and verify the Truth Table. b) Design Multiplexer using Verilog Hardware Description Language.

4. a) Design and implement BCD to excess-3 code converters using logic gates and verify the Truth able. b) Design Half Adder using Verilog Hardware Description Language.

5.a) Design and implement excess-3 to BCD code converters using logic gates and verify the Truth Table. b) Design Half Adder using Verilog Hardware Description Language.

6. a) Design and implement Binary to gray code converters using logic gates and verify the Truth Table. b) Design Full Adder using Verilog Hardware Description Language. 7. a) Design and implement gray to Binary code converters using logic gates and verify the Truth Table. b) Design Full Adder using Verilog Hardware Description Language.

8. a) Design and implement 4 bit binary Adder/ subtractor using IC 7483 and verify the Truth Table. b) Design Full Adder using Verilog Hardware Description Language.

9. a) Design and implement 4 bit binary BCD adder using IC 7483 and verify the Truth Table. b) Design Half Adder using Verilog Hardware Description Language.

10. a) Design and implement 2 bit Magnitude Comparator using logic gates and verify the Truth Table. b) Design Half Subtractor and Verilog Hardware Description Language.

11. a) Design and implement 8 Bit Magnitude Comparator using IC 7485 and verify the Truth Table. b) Design Full Adder using Verilog Hardware Description Language.

12. a) Design and implement 16 bit odd/even parity checker using IC74180 and verify the Truth Table. b) Design Half Adder using Verilog Hardware Description Language. 13. a) Design and implement 16 bit odd/even parity generator using IC74180 and verify the Truth Table. b) Design Full Adder using Verilog Hardware Description Language.

14. a) Design and implement of Multiplexer using logic gates and verify the Truth Table. b) Design Half Subtractor and Verilog Hardware Description Language.

15. a) Design and implement of De-multiplexer using logic gates and verify the Truth Table. b) Design Full Subtractor using Verilog Hardware Description Language.

16. a) Design and implement encoder using logic gates and verify the Truth Table. b) Design Multiplexer using Verilog Hardware Description Language.

17. a) Design and implement decoder using logic gates and verify the Truth Table. b) Design De-multiplexer using Verilog Hardware Description Language.

18. a) Construct and verify the Truth Table of 4 bit ripple counter. b) Design Multiplexer using Verilog Hardware Description Language.

19. a) Construct and verify the Truth Table of Mod-10/Mod-12 Ripple counters b) Design De-multiplexer using Verilog Hardware Description Language.

20. a) Construct and verify the Truth Table SISO shift registers using Flip- flops. b) Design Full Subtractor using Verilog Hardware Description Language.

21. a) Construct and verify the Truth Table SIPO shift registers using Flip- flops. b) Design Half Subtractor and Verilog Hardware Description Language.

22. a) Construct and verify the Truth Table PISO shift registers using Flip- flops. b) Design Full Adder using Verilog Hardware Description Language.

23. a) Construct and verify the Truth Table PIPO shift registers using Flip- flops. b) Design Full Subtractor using Verilog Hardware Description Language.

Anna University of Technology, Coimbatore University Practical Examinations, oct-2011 DIGITAL ELECTRONICS LAB (EC 2207) QUESTION PAPER 1. Design, implement and verify the truth table of Adder and Subtractor using logic gates. 2. Design, implement and verify the truth table of code converters using logic gates (i) BCD to excess-3 code and excess-3 to BCD (ii) Binary to gray and vice-versa 3. Design, implement and verify the truth table of 4 bit binary Adder/ subtractor and BCD adder using IC 7483 4. Design, implement and verify the truth table of 2 bit Magnitude Comparator using logic gates 8 Bit Magnitude comparator using IC 7485 5. Design, implement and verify the truth table of 16 bit odd/even parity checker/generator using IC74180. 6. Design, implement and verify the truth table of Multiplexer and De-multiplexer using logic gates 7. Design, implement and verify the truth table of encoder and decoder using logic gates 8. Construct and verify the truth table of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 9 Design, implement and verify the truth table of 3-bit synchronous up/down counter 10. Design, implement and verify the truth table of SISO, SIPO, PISO and PIPO shift registers using Flipflops 11. Design the following circuits using VHDL a) Half Adder and Full Adder. b) Half Subtractor and Full Subtractor. c) Multiplexer. d) De-multiplexer. e) Ripple counter. f) SISO shift registers. g) SIPO shift registers. h) PISO shift registers. i) PIPO shift registers.

Internal Examiner

External Examiner