Recent Advancements in FPGA-based controllers for AC Drives Applications

E. MONMASSON
1
, I.BAHRI
1
, L. IDKHAJINE
1
,

A. MAALOUF
2
, W. M. NAOUAR
3

1
SATIE-IUP GEII, rue dEragny, 95031 Cergy-Pontoise, France, Phone: +33 (0)1 34 25 68 90, Fax: +33 (0)1 34 25 69 01
Email: eric.monmasson@u-cergy.fr, imen.bahri@u-cergy.fr, lahoucine.idkhajine@u-cergy.fr
2
Thales-AES, 41 Boulevard de la rpublique, 78400 Chatou, France, Email: amira.maalouf@fr.thalesgroup.com
3
L.S.E-ENIT BP 37-1002 Tunis le Belvdre, Tunisia, email: wissem_naouar@enit.rnu.tn


Abstract The aim of this paper is to present recent
advancements in the field of Field Programmable Gate Array
(FPGA) based controllers for AC drives applications. Firstly,
the benefits of using FPGA components for this kind of
applications will be reminded. It will be shown that these
benefits can be general to all types of drive applications or
more specific to niches like aircraft applications. Then, several
practical examples will be given which have demonstrated the
high level of performances that can be reached with FPGA-
based controllers. All these controllers were designed for
synchronous motor drive applications but their extension to
other types of machines is a quite straightforward process. The
proposed examples are current and well reflect the ever
increasing complexity of the control algorithms to be
implemented. These examples are respectively a predictive
current controller, a sensorless drive based on an Extended
Kalman Filter (EKF) and another sensorless drive based on a
high frequency voltage component injection technique. This
last application has been designed for an industrial aircraft
Brushless Synchronous Starter/Generator (BSSG) of 40kVA.
The last part of the paper is devoted to the latest developments
in terms of System-on-Chip (SoC) architecture. A special focus
is made on a methodology which aims to optimize the Hw/Sw
partitioning of the tasks to be executed. Finally, conclusions are
drawn and perspectives given.
Index terms FPGA, System-on-Chip, AC Drive, sensorless
motor controller, Extended Kalman Filter, rotating high
frequency signal injection, Hw/Sw partitioning.
I- INTRODUCTION
It is now well-admitted that Field Programmable Gate
Array (FPGA) components are of prime interest for
implementing digital industrial control systems [1]-[3].
These devices consist of pre-designed elementary cells and
interconnections that are fully programmable by the end
user to build specific hardware architectures that match the
requirements of the final targeted application.
The range of the designed FPGA-based architectures is
quite large, going from efficient 32-bit RISC processors
along with their dedicated peripherals and computing
hardware accelerators to pure specific hardware
architectures for stringent applications. From this
perspective, and due to their ever increasing density, modern
FPGAs can be seen as true System-on-Chip (SoC)
platforms. Thus, the design and real-time implementation of
control loops with sampling frequency above one MHz is
now feasible, as well as the implementation of massive
parallel computations. Like microcontrollers and Digital
Signal Processors (DSPs), FPGAs were born in the eighties
and are now considered as a mature technology. FPGA
development tools are also very powerful now and easy to
use. FPGAs are well-suited for high speed demanding
applications. Indeed, designers can develop a fully hardware
architecture which is dedicated to the control algorithm to
implement. Hence, by preserving the potential parallelism of
the algorithm, the resulting hardware architecture allows
matching the expected processing speed specifications.
The main limitation of this technology with regards to its
main competitors (DSPs and microcontrollers) is the cost.
However, this claim has to be relativized since a FPGA
component may be more expensive than a microcontroller
but not necessary its cost per implemented function. Another
drawback concerns the difficulty to integrate within current
FPGAs mixed Analog/Digital peripherals like A/D and D/A
converters. Once again, this limitation is vanishing with the
recent introduction on the market of FPGAs that integrate
A/D converters [4], [5]. Finally, FPGAs are consuming
more energy, which is an important issue for low power
embedded applications.
As presented in Fig. 1, the basic structure of an FPGA
consists of a sea of thousand hundred Logic Blocks (LBs),
an interconnection network and configurable I/O blocks.
Because of their very high level of integration, current
FPGAs also include memory blocks, hardwired DSP units,
clock manager blocks, communication blocks and 32-bits
RISC microprocessor cores, more details about these
different blocks can be found in [2].

Fig. 1. Generic Architecture of a FPGA
The current power converter and AC drive control trends
are perfectly matching the potentiality of FPGAs. Indeed,
having in mind the embedded transport applications, which
are probably some of the most challenging ones in terms of
technical specifications, four major trends can be observed
that confirm this claim:
- A high level of integration is required in order to reduce
weight and volume of the embedded systems. The direct
consequence of the increase of integration rate is a reduction
of the passive filters and the increase of the switching
frequency of the corresponding power converters (above
100kHz). As a results, more processing speed is required
that FPGAs can achieve [6].
- A high level of performances & accuracy is expected
which leads to implement in real-time complex control
and/or signal processing algorithms. Good illustrations of
this trend are the sensorless AC drive controllers [7] and
diagnosis functions [8].
8 978-1-4673-1653-8/12/$31.00 '2012 IEEE
- Enhanced reliability is required due to rough environments
(high ambient temperature, vibrations or Single Event Upset
(SEU) radiations). Needs for specific and robust FPGA
technologies and packages are mandatory [9].
- An increase of the level of power and a reduction of the
stress of the power components are leading to a
segmentation of the power (multi-level converter, multi-
phase machines, interleaved power converters). The latter
requires always more parallelism [10].
As can be seen, FPGAs are well-adapted to all these new
requirements because of their high processing speed and
their parallelism capabilities.
However, designing with FPGAs requires an efficient
methodology in order to capitalize design efforts along the
different projects. An adapted design methodology is
summarized in Fig. 2. It is a balanced solution between two
opposite needs, namely: a friendly method that is perfectly
adapted to a control engineer who is not an expert in digital
electronics and the consideration of good control
performance requirements that necessarily leads to
substantial efforts during the design phase of the hardware
architecture.


Fig. 2. Design methodology

The main steps of this design methodology are now
recalled. The first three steps (on the top of Fig. 2) are
independent of the target:
- The modular partitioning step consists in partitioning the
algorithm in reusable blocks that make sense from a
functional point of view (like PI regulators). Doing so, the
designer is able to capitalize his work along the different
projects he has to manage.
- The functional simulation step where the synthesis of the
controller is most of the time validated in time-continuous
mode via the Matlab-Simulink environment.
- The digital redesign step that is crucial since it includes
the realization of the digital filter, the choice of the sampling
period and the choice of the fixed-point formats for
coefficients and variables [11].
The last four steps are dependent on the used technology. In
the case of an FPGA-based implementation, they consist in:
- The data flow graph optimization where the designer is
modeling the data flow graph of the algorithm in order to get
the best balance in terms of time/area performances [12].
The written HDL code is the direct transcription of the
resulting data flow graph.
- The following step is the FPGA implementation in itself.
This is an automatic procedure to map, place and route the
design and analyze its static timing performances.
- Then, experimental validation is made either on the final
system or by using an Hardware-In-the-Loop (HIL)
procedure [13].
Finally, mention that an HDL automatic code generation
is also possible directly from Simulink when a rapid
prototyping procedure is desired [14]. It corresponds to the
blue arrow in Fig. 2.
The resulting library of IP modules can be classified in
several layers depending the complexity of the blocks. In
figure 3 is presented a library of IP modules dedicated to AC
drive applications.

Fig. 3. IP cores library for AC drive applications
The rest of the paper aims to illustrate the interest of
FPGA-based controllers for AC drive applications by
presenting several practical examples. All the proposed
controllers were designed for synchronous motor drives
applications but their extension to other types of machines is
a quite straightforward process. The proposed examples are
current and well reflect the ever increasing complexity and
the computational intensive feature of the control algorithms
to be implemented. These examples are respectively a
predictive current controller, a EKF-based sensorless drive
and another sensorless drive based on a high frequency
voltage component injection technique. This last application
has been designed for an industrial aircraft Brushless
Synchronous Starter/Generator (BSSG) of 40kVA. The last
part of the paper is devoted to the latest developments in
terms of System-on-Chip (SoC) architecture. A special
focus is made on a methodology which aims to optimize the
Hw/Sw partitioning of the tasks to be executed. Finally,
conclusions are drawn and perspectives given.
II-PREDICTIVE CURRENT CONTROLLER IMPLEMENTATION
FPGA-based current controllers are on prime interest for
AC drive applications. Indeed, their very fast processing
speed allows comparing them as analog controllers. Thus,
they are cumulating the benefits of the both worlds: a high
bandwidth (analog) with a great flexibility (digital). These
features are of prime importance when a direct control of the
power converter is used (hysteretic control, sliding mode
control,) [15]. Another, good example of the benefits of
using FPGA-based current controllers can be found in
predictive control.
A. Predictive current control principle
For the development of the digital predictive current
controller, the state model of a wound rotor synchronous
machine in the dq rotor reference frame (The d axis is linked
to the rotor winding) can be simplified by considering that
the used sampling period T
s
is very small with regard to the
electrical time constants T
sd
and T
sq
of the used machine
.

9
Consequently, the rotation speed value is constant during the
whole sampling period. This leads to the digital prediction
equations given by relation (1). They are based on the
forward Euler approximation method. The synchronous
machine rating and parameters are presented in the
appendix.

+ =
=

+ = +
+ = +
] [ ] [ ] [ ] [ ] [
] [ ] [ ] [
] [ ) 1 ( ]) [ ] [ ( ] 1 [
] [ ) 1 ( ]) [ ] [ ( ] 1 [
k i k M k i k L k e
k i k L k e
where
k i
T
T
k e k V
L
T
k i
k i
T
T
k e k V
L
T
k i
rd sr sd sd sq
sq sq sd
sq
sq
s
sq
j
sq
sq
s j
sq
sd
sd
s
sd
j
sd
sd
s j
sd


(1)
Relation (1) shows that the evolution of the dq stator
current components depends on the applied dq stator voltage
components V
sd
and V
sq
. The different stator voltage vectors
t
j
j
sq
j
j
sd
j
j
sdq
V V V ] [ ) 7 .. 0 ( ) 7 .. 0 ( ) 7 .. 0 ( = = = =

expressed in the dq
rotor reference frame are directly derived from the seven
possibilities offered by a 2 level VSI. Thus, thanks to (1) it
is possible to predict the current error vector ] 1 [ + A k i
j
sdq

which is defined by the difference between the reference
current vector at the k
th
sampling period
t
sq sd sdq
k i k i k i ] ] [ ] [ [ ] [
* * *
=

and the predicted stator current

vector
t j
sq
j
sd
j
sdq
k i k i k i ] ] 1 [ ] 1 [ [ ] 1 [ + + = +

for each of the

voltage vector
j
sdq
V

. Finally, the voltage vector that

minimizes the following criterion is chosen.
) ( min
2
) 7 .. 0 (
j
sdq
j
i A
=

(2)
Fig.4 presents the principle of the proposed predictive
current controller. The rotor speed
dq
is derived from the
measured position
dq
. The i
sd
, i
sq
, e
sd
and e
sq
values are
computed using the measured stator currents i
s1
and i
s2
, the
measured position
dq
and the estimated speed rotation
dq
.
A prediction module based on (1) allows the prediction of
the different error vectors ) 7 .. 0 ( = A j
j
sdq
i

. Finally, an
optimisation procedure based on (2) allows selecting the
switching states combination that leads to the minimum
square module error.

Fig. 4. Predictive current controller
B. FPGA implementation of a predictive controller
Fig.5 shows the developed hardware architecture that
corresponds to the considered predictive controller. A global
controller is activated via a start signal every sampling
period T
s
. The global controller first activates the AD
interface module. Then, it waits for the end of the AD
conversion process. After that, the module of the predictive
controller is activated and it computes the switching states.


Fig. 5. Predictive current controller architecture

This predictive controller was implemented on a low
cost Spartan 3 FPGA. The computing time is only of 2.2s
even if all the 7 voltage combinations were evaluated.
Knowing that the execution time is by far less than the
sampling period, this digital predictive controller behaves as
an anolog one. As a consequence, the corresponding
dynamic performances are excellent, only limited by the DC
link voltage value, the line inductance of the motor and the
chosen sampling period, see Fig. 6.


Fig. 6. Speed reversal test (step from I
n
to +I
n
)
III-EXTENDED KALMAN FILTER IMPLEMENTATION
The Extended Kalman Filter (EKF) is often considered
as one of the most demanding control algorithm in terms of
computation in the field of AC drives. The study presented
in this section demonstrates that FPGA can be an interesting
alternative to DSP when implementing such observer.
A. EKF-based sensorless synchronous motor drive
In Fig. 7 is shown the studied EKF-based sensorless
control scheme. The EKF algorithm leans on the stochastic
d-q model of a synchronous machine. To reduce the
complexity of the motor model, the infinite inertia
hypothesis is applied to the mechanical equation (3)-(5)
[16]. The following relation gives the chosen per unit model
(the nomenclature is given at the end of this paper).
v x H y
w u x f x
n n
n n n
+ =
+ = ) , (

With
T
B
sq
B
sd
n
T
B
sq
B
sd
n
T
B
e
B
e
B
sq
B
sd
n
I
i
I
i
y
V
v
V
v
u
I
i
I
i
x
(

=
(

=
(

= ; ;

T
n
sq B
B
sd B
B
en
B
B
en B
sq
rnd sr
snd
sq
sd
snq
sq
s
snq en B
sd
sq
snd
sd
s
n n
H u
L I
V
L I
V
L
I M
i
L
L
i
L
R
i
L
L
i
L
R
u x f
(
(
(
(

=
(
(
(
(
(
(
(

+
(
(
(
(
(
(
(
(

=
0 0
0 0
1 0
0 1
;
0 0
0 0
0
0
0
) (
) , (

SM
Vrd
dq
Optimisation
E
isd
*

is1
is2
isd
isq
esd esq
dq
(isdq
j
)(j=0..7)
C1
C2
C3
Prediction
dq
123
EMF
d/dt
isq
*

p
m
AD
Interface
is1AD
is2AD
AD Control
C1
C2
C3
Global controller
Algorithm controller
Start
End
Clk
Clk
Predictive current controller
Start_CC End_CC
End_AD Start_AD
EAD
123-to-dq
Clk
EMF
Clk
Prediction
&
optimisation
Clk
isd
*

isq
*

E
isd
isq
esd
esq
Clk
Speed
Estimato
r
Clk
p offset
dq
+ + m
is1
is2
wait
Start_AD=1
wait
End=1
Start=1
Reset
Start_CC=1
wait
End_AD=1
End_CC=1
Global Controller FSM
(3)
(4)
(5)
10

Fig. 7. EKF-based sensorless control scheme

This model includes zero-mean Gaussian w and v white
noise terms that represent modeling and measurement
disturbances. These disturbances are respectively
characterized by covariance matrices Q and R.
Table I: EKF Algorithm
Prediction Step
) ,

( .

1 1 / 1 1 / 1 1 /
+ =
nk k nk s k nk k nk
u X f T X X

EKF Compensator
Jacobian matrix :
( )
1 / 1

1 1 1
) , ( .

=

c
+ c
=
k nk n
x x n
nk nk s nk
nk
x
u x f T x
Fd

Covariance matrix
prediction :
Q Fd P Fd P
t
nk k nk nk k nk
+ =

. .
1 / 1 1 /

Initial condition P0
Kalman gain
calculation :
( )
1
1 / 1 /
. .


+ = R H P H H P K
t
k nk
t
k nk nk

Updating covariance
matrix :
1 / 1 / /
=
k nk nk k nk k nk
P H K P P

Innovation step
( )
1 / 1 / /


+ =
k nk nk nk k nk k nk
X H y K X X


Table I lists the equations that are being processed by the
EKF. The prediction step is based on the system model
(discrete-time Euler approximation). T
s
is the sampling
period. The Kalman gain K
nk
is computed within the EKF
compensator module. This gain is used in the innovation
step to adjust the estimated state space vector X
nk/k
.
The evaluation of the complexity of the whole EKF
module (EKF + abc-dq transformations), with a 4
th
-order
model shows that the total number of arithmetic operations
is equal to 648 (352 multiplications, 271 additions, 24
subtractions and 1 inversion). As far as the data
quantification is concerned, a fixed-point data format for
coefficients and variables was chosen. It consists in a signed
format of [22/Q20], where the total size is 22 bits and the
length of the fractional part is equal to 20 bits. The
developed EKF-based sensorless controller was first
validated by simulation in Matlab/Simulink environment.
B. Fully Hardware FPGA-based implementation
In this subsection we are discussing the full hardware
FPGA implementation of the EKF module.A Virtex II pro
Xilinx FPGA was chosen as device target. The development
of the FPGA architecture must consider the complexity of
the EKF so as to optimize the use of the FPGA resources.
To this aim, the A
3
(Algorithm Architecture Adequation)
methodology has been adopted [12]. This approach consists
in factorizing the heavier operators (especially the
multipliers). This leads to locally serialize the treatment.
Fig. 8 presents the FPGA architecture of the EKF module.
This architecture is divided into a data path and a simple
control unit. This last leans on a finite state machine that
controls the treatment.
The obtained time/area performances for the whole
sensorless controller are given in Table II. They are obtained
after having synthesized the developed design for different
types of FPGAs. This synthesis indicates the consumed
FPGA resources and the maximum achievable frequency of
the system clock.

Table II: Synthesis results for the FPGA-based sensorless controller

Low cost FPGAs High performance FPGAs
Spartan 3E
xc3s1600E
Spartan 6
xc6slx150
Virtex 2P
xc2vp30
Virtex 6
Xc6vsx475
Max. clk
Frequency
44 MHz 82 MHz 120 MHz 226 MHz
Global
resources
use
- 63% (3688
CLB)
- 100% hw 18-
bit multipliers
(over 36)
- 11% (11519
CLB)
- 38 % hw 18-
bit DSP blocks
(over 180)
- 49% (3424
CLB)
- 50% hw 18-
bit multipliers
(over 136)
- 3.4%
(37200 CLB)
- 3.4% hw 18-
bit DSP
blocks (over
2016)
tex_min 6,82 s 3,65 s 2.98 s 2,71 s
C. Experimental results
Fig. 9 presents some experimental results. It corresponds
to a step of 500 rpm on the speed. The corresponding
waveforms of the measured and the estimated rotor
positions are shown. It can be concluded to the good
matching between these two quantities. The designed EKF
is operating correctly down to 8% of the based speed.
Beyond this limit, another strategy based on high frequency
carrier injection is necessary.
Finally, in Fig. 10 is shown the positive impact of a fast
FPGA-based estimation of the position over the speed
regulation. As can be seen in Fig. 10, the speed bandwidth is
abc-dq
Prediction
module
EKF compensator
Innovation
module
abc-dq
en1
en1
en1
en1

Start_abc_dq_i
End_abc_dq_i
Start_abc_dq_i
End_abc_dq_i
Start_pred End_pred
Start_EKF_comp End_EKF_comp
Start_innov End_innov
en0
Start signals End signals
Start_EKF
Reset
Clk
Wait
Reset
2 3 4
5
6 7 8
en0
Start_abc_dq_i
End_abc_dq_i ?
1
Start_pred
Start_EKF_comp
End_EKF_comp ?
Start_innov
en1
end_EKF
end_EKF
Fig.8. FPGA architecture of the EKF module
(7)
(6)
(8)
(9)
(10)
(11)
11
significantly increased compared to a standard DSP
implementation. This is all the more effective than the motor
has a high rated speed like for aircraft applications [17].


Fig. 9: Experimental results: speed and position waveforms

Fig. 10. Speed loop bandwidth for an FPGA-based controller and
for a DSP-based controller Case of the aircraft BSSG. Frequency
response (magnitude)
IV-SENSORLESS CONTROL BASED ON HIGH FREQUENCY
INJECTION
At standstill and very low speed operating conditions,
the rotating high frequency injection method is prefered to
estimate the rotor position of the machine. This technique
exploits the saliency of the machine and consists in
superimposing a high frequency signal to the fundamental
(current or voltage), see Fig. 11. In this paper, voltage
injection scheme is preferred to the current injection scheme
since it is easier to design. The injected high frequency
voltage causes phase and amplitude modulation in the phase
current that can be used to estimate the rotor position.


Fig. 11. High frequency injection based estimator
A. Principle
Relation (12) expresses the injected rotating high
frequency voltage.
( )
( )
(

=
(

t
t
V
V
V
h
h
h
h
h
. sin
. cos
.

(12)

The obtained current in the (, ) fixed reference frame
can then be written as
( )
( )
( )
( )
( )
( )
(
(
(

+
+
+
(
(
(

+
(
(
(

=
(
(
(

n h n
n h n
p h p
p h p
h
h
t I
t I
t I
t I
t I
t I
i
i

. 2 sin
. 2 cos .
.
. sin
. cos .
.
. sin
. cos .
.
1
1


Therefore, injecting a high frequency signal in the
machine superimposes to the fundamental i
1
two HF
components that are respectively the positive i
p
sequence
and the negative i
n
sequence. The HF positive sequence
component does not contain any information about the rotor
position. However, the HF negative sequence component
contains the rotor position information. Besides, the HF
negative sequence component amplitude depends on the
saliency level of the machine, on the amplitude of the
injected HF signal and on the chosen frequency [18]-[19].
B. Synchronous frame filtering
The synchronous frame filtering, achieved by 2 rotations
and 2 high-pass filters, aims to filter off the carrier signal
current components. Thus, the current regulation is not
disturbed by the HF signal. On the other hand, the position
information is extracted by using a low pass filter applied in
a reference frame h
n2
(see Fig. 13) [20].


Fig. 12: Synchronous frame filtering
C. Hardware FPGA-based implementation
Fig. 13 presents the hardware FPGA architecture of the
designed position estimator. The signal injection based
sensorless controller has been implemented in a ProASIC3
A3P1000 FPGA device from Microsemi. This component is
well adapted to the rough environment encountered in
aircraft applications. The device is driven by a 40 MHz
clock. Based on this clock frequency, the global execution
time, including the analog to digital conversion time, is only
equal to 2.925s. Hence, the proposed HF injection based
sensorless controller has high performances without any
need for delay compensation nor additional modifications
due to high computation time.
D. Experimental results
The experimental tests were performed using a 40kVA
BSSG. This kind of machine is widely used in the aircraft
domain for starter/generator purposes. Fig. 14 shows the
actual and estimated positions along with the stator current
I
sa
during the start-up of the motor. The injected signal has a
frequency of 2 kHz. It can be seen that good position
a

b

HP1
PLL


Ia
Ib
Ic
Control unit of position estimation based on HF injection
HF injection estimation controller
Rotation
2



2.h.t
Clk_40 MHz
Clk_synchro
Start End
HP1
Rotation
1
Gen_clk
LP1
LP1
-h.t
Fig.13. Architecture of the HF injection based estimator
(13)
Position estimator

12
estimation accuracy is obtained. However, the resulting
architecture consumes 99% of the available logic tiles due to
the fact that this kind of FPGA does not integrate Hw
multipliers.

Fig. 14: Actual position, estimated position and I
sa
during start-up
V-HARDWARE-SOFTWARE PARTITIONING
As seen in the previous sections, algorithmic complexity
for the control of AC drives has now reached a critical level.
In order to cope with this complexity and in order to
integrate always more functionalities, designers can rely on
new powerful System-on-Chip platforms. These platforms
include both 32-b RISC processor cores and dedicated Hw
modules. However, in order to have a relevant use of these
powerful resources, designers need to use an efficient
methodology of Hw/Sw partitioning between the different
tasks to be executed.
In this section, authors propose a space exploration
method aiming to guide designer towards an optimized
controller implementation based on a SoC platform. It
consists on a Hw/Sw partitioning method of control modules
under constraints (time/area). To illustrate the interest of this
partitioning method, the EKF-based sensorless speed
controller was taken as a benchmark. The chosen level of
granularity for partitioning purpose has been fixed to the
level of functional modules (PI, abc-dq and dq-abc
transformations). This allows keeping active the
modularity principle.
The features of each functional module are given by a set
of metrics presented in Fig. 15. Profiling work is done for
each module and the corresponding data are stored
respectively in Sw and Hw libraries. So, for each module, a
set of metrics has been defined as explained below:

Where
- A
i
represents the consumed resources of the i
th
module,
in the case of an Hw implementation.
- H
i
represents the number of memory cells used by the i
th

module, in the case of a Sw implementation.
- T
hi
represents the execution time taken by the i
th
module
when executed in Hw.
- T
si
represents the execution time taken by the i
th
module
when executed in Sw.
- T
COMi
represents the communication time between the i
th

module and its neighbors.
- DSP
i
represents the consumed hardware Digital Signal
Processing (DSP) blocks of the i
th
module, in the case of
Hw implementation.
- I
i
/O
i
represents the number of Inputs and Outputs of the
i
th
module.

A. Formalization of the partitioning problem
As can be seen in Fig. 16, the control algorithm is
organized as a set of n functional modules, denoted as M =
(M1,M2,). The number associated to each functional
module is related to its scheduling order. The
implementation of each module can be made in hardware or
in software. However, the implementation of the ADC
interface module and the PWM module is fixed in Hw.
Indeed, the resolution and the functional performance
required by these modules cannot be provided in Sw. Thus
they are not considered in the partitioning procedure. In
addition, the EKF compensator that includes many matrix
operations is divided into five more manageable sub-
modules.


Fig.16. Hw-Sw partitioning of the architecture of EKF-based
sensorless controller

The formulation of the optimization problem of the
resources allocation is given in (14). The objective is to find
the best trade-off in terms of resource allocation taking into
account constraints of time and space. It is assumed that (x
1
,
x
2
,x
n
) is a possible solution of the Hw/Sw partitioning
problem, where x
i
= 1 denotes a hardware implementation of
the i
th
module, and x
i
= 0 denotes a software
implementation. A
i
is the total Hw resources consumed by
the i
th
module. The use of a soft processor core requires the
consideration of the whole resources taken by the processor.
These resources include the area taken by the soft processor
P-PI
regulator
q-PI
regulator
d-PI
regulator
DQ
To
ABC
ABC
To
ABC
ADC
current
Interface
EKF Estimator
SVM
Prediction
ABC
To
DQ
ABC
To
DQ
EKF
compensator
Innovation
Compensator
P1
delay
Compensator
P2
Compensator
P3
Compensator
P4
HW Modules SW-HW Modules
2'
3
9
2
10
4'
8 7 6 5
15
16
14
13 11
12
S
a
S
b
S
c

*
I
q
*
Vq*
Vd*

I
sa
I
sb
V
dc

I
q
I
sd

V
sa
*
V
sb
*
V
sc
*
V
sna k-1
V
snb k-1
I
snak
I
snak
Voltage
Interface
Sensorless
control
V
sna
, V
snb
I
sna
, I
snb
V
snd k-1
V
snq k-1
I
snq
I
snd
X
k-1
K
nk
X
k
X
k-1
K
nk
Jacobian
matrix
1
4
0
Q(20,18) Q(20,18)
Q(13,12) Q(13,12)
Q(20,18)
Q(13,12)
Q(13,12)
Q(13,12)
Q(22,20)
Q(22,20)
Q(22,20)
Q(13,12)
Q(13,12)
Q(22,20) Q(22,20) Q(22,20) Q(22,20) Q(22,20)
I
q
*
=0
SW features

HW features
T
si
, T
COMi
, H
i
, DSP
i

T
hi
, T
COMi
, A
i
, DSP
i

I
i
O
i

Fig. 15. Functional module

400 ms
180
50A
400 ms
13
core itself along with its auxiliary cores (timer core,
interrupt core, communication buses). The whole consumed
resources are expressed by Area
p
. Thus, the execution of
only one module in software requires the inclusion of the
whole internal resources associated to the processor core.
The consumption of hardware DSP blocks is also evaluated
in the same way. Configuring hardware multipliers and
dividers within the processor results to the use of some DSP
blocks expressed as DSP
p
. The whole execution time T
ex

is also calculated in a similar way.
( )
( )

+ =
=
+ =
+ =

= =
=
+
=
+
=
si
n
i
i hi
n
i
i ex
i
n
i
i
p i i i
n
i
i block
p i i i
n
i
i
t x t x T
H x Memory
DSP x or x DSP x DSP
A x or x A x Area
Minimize
. 1 .
. 1
)... 1 ( ) 1 ( .
)... 1 ( ) 1 ( .
1 1
1
1
1
1
1

s
s
s
max
T T
M Memory
S Area
to Subject
ex
i

S and M are respectively the maximum area and memory
space allowed to the EKF-based sensorless controller. T
max

is the maximum allowed execution time in order to respect a
given level of control performances (overshoot, settling
time...)
B. Heuristic algorithm: NSGA-II
In the present work, the Non-dominated Sorting Genetic
Algorithm (NSGA-II) is chosen for solving the Hw/Sw
partitioning under multiple heterogeneous objectives and
constraints. It aims to find out the optimal Pareto front of the
studied problem. The NSGA-II classifies the candidate
solutions considering all the objectives, using ranking
options to eliminate all the non-dominated solutions. The
performance metrics of control modules are introduced in
the optimization algorithm. Individuals constitute a
population. Each individual corresponds to the set of the
control modules. In our case, there are 15 modules.
Algorithm configuration was done considering the following
parameters value: Generations 100, population size 100,
P_Crossover 1%, P_Mutation 90%.
The tests are performed on a Xilinx Virtex V FPGA,
including a 32-b Microblaze processor soft core. This target
includes also up to 32640 Flip-Flop, 32640 6-Bit Look-up-
table and 288 (25x18) DSP blocks. Because of the extensive
combinational nature of the EKF-based sensorless controller
the number of 6-Bit LUTs is taken as the basic metric for
area. Fig.17 presents the partitioning results and the
corresponding speedup factor with respect to a full software
solution (=1). It presents all the possible final architectures
that can be realized. The NSGA-II algorithm provides a
space exploration covering a good number of feasible
solutions. Thus, designer can choose the appropriate
allocation and the corresponding scheduling which fit the
best his application.

Fig. 17. Hw/Sw partitioning results.
In this case, a limitation in area of 7000 LUTs and a
maximum execution time of 7000 system CLK cycles have
been chosen. The results of the space exploration are
presented in Fig.17. From these results, it can be seen that
hardware accelerators can provide a significant speedup
with respect to the software baseline. Table III and Fig.18
present some candidate solutions and the scheduling
diagram of fastest one. It is 2.5 time faster that the pure
software solution while still respecting the imposed
constraints.
Table III: Optimization candidate solutions


Fig.18. Scheduling diagram of the solution S4m.

VI-CONCLUSIONS
In this paper authors have presented the advantages and
the drawbacks of FPGA-based controllers for AC drive
applications. Several practical examples have been given in
order to illustrate the gain in terms of performances that the
designer can expect from the rapidity of this type of
controller: True direct control of the power converter,
increase of the bandwidths of the current and speed loops,
possibilities of implementing predictive strategies, high
level of synchronization of the PWM modulator with the
rest of the control The proposed examples are also
representative of the important level of complexity of the
current control algorithms. The first example was a
predictive current controller for synchronous motor drive,
the second example was an EKF-based sensorless controller
for synchronous motor drive and finally, the last example
was a rotating high frequency injection based position
estimator for a 40kVA BSSG intended for aircraft
application. The last part of the paper addressed the issue of
Hw/Sw partitioning for current and next generation of
System-on-Chip controllers. To this purpose, a rigorous
(8)
14
Hw/Sw partitioning method was presented. It is based on an
NSGA-II optimization algorithm (Non-dominated Sorting
Genetic Algorithm). It has been used to find the optimal
Hw/Sw partitioning solution of an EKF-based sensorless
speed controller, under time and area constraints.
In the near future, the complexity of the digital control
algorithms will continue to grow. Predictive control and
adaptive control will be more and used, leading to a
significant increase of the embedded computing power.
Besides, the tasks devoted to the control algorithms will no
longer be limited to regulation but will also include the
management of EMI, communications, health monitoring,
diagnosis and fault-adaptive on-line control. All these new
functionalities will require more signal processing functions
and of course more parallelism. The demand in terms of
reliability for stringent applications like transportation will
probably bring new interesting technological challenges like
FPGA-based controllers able to work safely on a wide range
of temperature. Finally, the new FPGA-based controller
architectures will have to be adapted to all these new
requirements by including floating-point units, mixed
analog/digital integration and multiple programmable
system-on-chip (MPSoC) features.
APPENDIX
SYNCHRONOUS ACTUATOR PARAMETERS 0.8 KVA, 220V, 1.5A, 50
Hz, 3 Phases, Y connection, 2 pole pairs
Stator resistance Rs = 10.5 Rotor resistance Rr = 62.5
d axis stator inductance
Lsd = 0.245 H
Mutual inductance
Msr = 0.86 H
q axis stator inductance
Lsq = 0.229 H
Nominal stator current
Isn = 2.12 A
Base quantities for normalization
VB = 936V; IB = 20A; B = 419 rd/s ; B = 2
MAIN STARTER GENERATOR PARAMETERS
40 KVA, 55V, 400 Hz, 3 Phases, Y connection, 2 pole pairs
Stator resistance
Rs = 12 m
Rotor resistance
Rr = 0.34
d axis stator inductance
Ld = 0.6 H
Mutual inductance
Msf = 13.151 mH
q axis stator inductance
Lq = 0.3 H
Nominal stator current
Isn = 290 A
NOMENCLATURE
s, r : Stator and rotor index
d,q : Synchronous reference frame index
*, ^ : Reference quantity, Estimated quantity
B, n : Base quantity for normalization, Normalization index
a, b, c : 3-phase reference frame index
isna, isnb, Irnd : Stator and rotor currents
isnd, isnq : d-q stator currents
VDCn, VZSSn : DC link voltage, Zero Sequence voltage
Vsna, Vsnb, Vsnc : 3-phase stator voltages
vsnd, vsnq : d-q stator voltages
dsan, dsbn, dscn : 3-phase duty cycles
dsan, dsbn, dscn : 3-phase duty cycles
en, en : Electrical position and speed
xn, un, yn : State space vector, System input and output vectors
f(xn,un), H : State space matrix, System output matrix
w, v : System disturbances
k/k-1, k/k : Predicted quantity, Estimated optimal quantity
Kn, Fdn : Kalman gain matrix, Jacobian matrix for linearization
Pn, P0 : State error covariance matrix, Initial covariance matrix
Q, R : Model noise and measurement noise covariance matrices
REFERENCES

[1] E. Monmasson, M. Cirstea, FPGA design methodology for
industrial control systems A review, IEEE Trans. On Ind.
Electron., vol. 54, no. 4, pp. 18241842, August 2007.
[2] J. J. Rodriguez-Andina, M. J. Moure, M. D. Valdes, Features,
design tools, and application domains of FPGAs, IEEE Trans. On
Ind. Electron., vol. 54, no. 4, pp. 18101823, August 2007.
[3] E. Monmasson, L. Idkhajine, M. N. Cirstea, I. Bahri, A. Tisan, and
M. W. Naouar , FPGAs in Industrial Control Applications, IEEE
Transactions on industrial informatics Vol 7, n 2, pp. 224-243
May 2011.
[4] Microsemi Smart Fusion literature, available online at
http://www.microsemi.com/
[5] Xilinx Virtex 7 literature, available online at http://xilinx.com
[6] M. Hartmann, S.D. Round, H. Ertl, J. W. Kolar, Digital Current
Controller for a 1 MHz, 10 kW Three-Phase VIENNA Rectifier,
IEEE Trans. on Power Electronics, vol. 24, n11, pp. 2496 2508,
Nov. 2009.
[7] A. Maalouf, L. Idkhajine, S. Le Ballois, E. Monmasson, FPGA-
based Sensorless Control of Brushless Synchronous Starter
Generator for Aircraft Application, IET Electric Power
Applications Journal, Electric Power Applications, IET, vol. 5,
n1, pp. 181-192, Janvier 2011.
[8] A. Ordaz-Moreno, R. De Jesus Romero-Troncoso, J.A. Vite-Frias,
J.R. Rivera-Gillen, A. Garcia-Perez, Automatic Online Diagnosis
Algorithm for Broken-Bar Detection on Induction Motors Based
on Discret Wavelet Transform for FPGA Implementation, IEEE
Trans. Ind. Electron., vol. 55, n5, pp. 2193-2202, May 2008
[9] L. Idkhajine, E. Monmasson, M-W. Naouar, A.Prata, K.Bouallaga,
Fully integrated FPGA-based controller for synchronous motor
drives, IEEE Trans. on Ind. Electron., vol. 56, n. 10, pp. 4006-
4017, October 2009.
[10] O. Lopez,, J. Alvarez, J. Doval-Gandoy, F.D. Freijedo, Multilevel
Multiphase Space Vector PWM Algorithm IEEE Trans. Ind.
Electron., vol. 55, no 5, pp 1933 1942, May 2008.
[11] F. Zhengwei, J. E. Carletta, and R. J. Veillette, A methodology for
FPGA-based control implementation, IEEE Trans. Control Syst.
Technol., vol. 13, no. 6, pp. 977987, Nov. 2005.
[12] T. Grandpierre, C Lavrenne and Y. Sorel, Optimized rapid
prototyping for real-time embedded heterogeneous
multiprocessor, in Proc. CODES99 7
th
International Workshop
on Hardware/ Software Co-Design Conf., 1999, CD-ROM.
[13] A. Myaing, V. Dinavahi, FPGA-Based Real-Time Emulation of
Power Electronic Systems With Detailed Representation of Device
Characteristics, IEEE Trans. Ind. Electron., vol. 58, n 1, pp. 358-
368, Jan. 2011.
[14] F. Ricci, H. Le-Huy, An FPGA-based rapid prototyping platform
for variable-speed drives, in Proc. IEEE IECON02 Conf., 2002,
pp. 1156-1161
[15] M.-W. Naouar, E. Monmasson, A. A. Naassani, I. Slama-
Belkhodja and N. Patin, FPGA-based current controllers for AC
machine drivesA review, IEEE Trans. Ind. Electron., vol. 54,
no. 4, pp. 19071925, Aug. 2007
[16] S. Bolognani, L. Tubiana, M. Zigliotto, Extended Kalman Filter
uning in Sensorless PMSM Drives, IEEE Trans. on Ind. Electron,
vol. 39, no. 6, pp. 276 281, November 2003.
[17] L. Idkhajine, E. Monmasson, A. Maalouf, Fully FPGA-Based
Sensorless Control for Synchronous AC Drive Using an Extended
Kalman Filter, IEEE Trans. on Ind. Electron, vol. 59, n10, Oct.
2012
[18] J.-I. Ha, S.-K. Sul, "Physical understanding of high frequency
injection method to sensorless drives of an induction machine", In
Proc. IEEE-IAS.Conf. 2000, Vol.3 pp. 1802 - 1808, 2000
[19] D. Raca, P. Garcia, D.D.Reigosa, F. Briz, R. D. Lorenz, "a
comparative analysis of pulsating vs. rotating vector carrier signal
injection-based sensorless control", In Proc. IEEE-APEC.Conf, pp.
879 - 885, 2008.
[20] A. Maalouf, S. Le Ballois, E. Monmasson, J.-Y. Midy, and C.
Bruzy, FPGA-based sensorless control of brushless synchronous
starter generator at standstill and low speed using high frequency
signal injection for an aircraft application, in IECON 2011 - 37th
Annual Conference of the IEEE Industrial Electronics Society,
2011, pp. 4003-4008.

15