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Average Inductor Current Sensor for Digitally Controlled Switched-Mode Power Supplies
Miguel Rodrguez, Student Member, IEEE, Victor Manuel L pez, Student Member, IEEE, o Francisco J. Azcondo, Senior Member, IEEE, Javier Sebasti n, Senior Member, IEEE, a and Dragan Maksimovi , Senior Member, IEEE c

AbstractCurrent-mode control in digitally controlled switched-mode power supplies typically requires analog-to-digital (A/D) conversion of at least two signals, voltage, and current. The complexity of voltage A/D converters can be reduced using window A/D techniques. In conventional current A/D conversion, however, relatively high resolution is required over a wide range of signals, which results in increased complexity, power consumption, and cost of the controller. This paper proposes a very simple feedback sensor capable of high-resolution average inductor current sensing using two analog comparators and an analog low-pass lter. The approach requires very few external components and employs minimal digital hardware resources. A dynamic model and performance of the average inductor current sensor are experimentally veried on a 12-V input, 19-V output, 50-W boost converter prototype. The applicability of the proposed sensor is demonstrated in a digitally controlled 400-W, 400-V output Boost power factor preregulator. Index TermsAnalog-digital conversion, current control, digital control, switched-mode power supplies.
Fig. 1. Digitally controlled boost converter with current-mode control.

I. INTRODUCTION

N the area of digital control of high-frequency switchedmode power supplies (SMPS), numerous advances have been made in terms of reduced controller complexity or improved performance, together with enhanced programmability and exibility features. Practical digital voltage-mode control, requiring relatively small hardware resources, has been demonstrated in a number of applications [1]. Techniques such as window-ash analog-to-digital (A/D) conversion have been applied to reduce the controller complexity [2]. Digital currentmode control, however, requires two A/D conversions, as shown

Manuscript received September 19, 2011; revised December 1, 2011 and January 5, 2012; accepted January 6, 2012. Date of current version April 20, 2012. This work was supported by the Spanish Ministry of Science and Education under Project Consolider RUE CSD2009-00046, FEDER Founds and Projects MICINN10-DPI2010-21110-C02-01 and CICYT-TEC2011-23612. Recommended for publication by Associate Editor J. A. Pomilio. M. Rodrguez and D. Maksimovi are with the Colorado Power Elec c tronics Center, Department of Electrical, Computer and Energy Engineering, University of Colorado, Boulder, CO 80309-425 USA (e-mail: miguel.rodriguez@colorado.edu; maksimov@colorado.edu). V. M. L pez and F. J. Azcondo are with the Department of Electronics Techo nology, Systems and Automation Engineering, University of Cantabria, 39005 Santander, Spain (e-mail: lopezvm@unican.es; azcondof@unican.es). J. Sebasti n is with the Power Supply Systems Group, Department of Eleca trical and Electronic Engineering, University of Oviedo, 33204 Gij n, Spain o (e-mail: sebas@uniovi.es). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2183893

in the boost converter example of Fig. 1. Furthermore, relatively high-resolution current A/D conversion is required over a wide range of sensed currents, which increases complexity, power consumption, and cost of the controller implementation. This problem severely affects widespread applications such as power factor correction (PFC) rectiers, where an additional A/D converter is required for input voltage sensing [3]. Several alternatives to address these issues have been proposed: for instance, specic A/D structures for current sensing are used in [4] to implement average current mode control. The use of an external comparator and a digital-to-analog (D/A) converter that can easily be implemented in a digital system has recently been proposed: the authors in [5] use such a scheme, embedded in a feedback loop, to estimate the instantaneous inductance current, while the authors in [6] propose a simpler system suitable to implement peak current mode control. Current estimation techniques based on voltage measurements have also been investigated [7], [8], especially in the context of multiphase converter current equalization [9]. Numerous approaches to eliminate the need for some of the required A/D have also been proposed in PFC applications [10][15]. This paper proposes a simple and inexpensive high-resolution average inductor current sensor for digitally controlled SMPS. It is inspired by [5], and by the A/D concepts proposed in [16] and [17], where the output voltage ripple was used to indirectly measure the output voltage using a single analog comparator. The proposed sensor takes advantage of the inductor current waveform to measure its average value using very few external components: two comparators and a simple analog low-pass lter,

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Fig. 2.

Proposed current sensor.

in addition to a sense resistor and any conditioning circuitry that would be required in conventional analog current-mode control implementations. It can be easily implemented in digital logic [eld-programmable gate array (FPGA) or custom chip] using few hardware resources, and it provides accurate sensing of the average inductor current in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Therefore, the proposed approach can be applied to reduce the number of components, size, and cost of digitally controlled power supplies with FPGA or custom-chip-based controllers. This paper is organized as follows. Operation of the sensor is described in Section II. A dynamic model is derived in Section III. Section IV presents results of simulation of the proposed sensor when the converter operates in open- and closed-loop conditions. Section V shows open-loop experimental results obtained with a 12-V input, 19-V output, 50-W dcdc boost converter, as well as closed-loop operation of a 400-W, 400-V output boost power factor preregulator (PFP). Finally, conclusions are stated in Section VI. II. OPERATION OF THE AVERAGE INDUCTOR CURRENT SENSOR Fig. 2 shows the proposed sensor architecture. The voltage that represents the instantaneous inductor current, v+ = Rs iL , is compared with the signal v by the comparator Cm ain and with 0 V by the comparator Cdcm . Note that v is the result of a D/A conversion of isensed [n], which is the digital output of the current sensor. The output signal of Cm ain is a pulse of duration tp , and has a period equal to the converter switching period, Tsw . Therefore, its duty cycle dp can be dened as dp = tp /Tsw . The feedback operation of the sensor forces dp to equal dref ; if dref is adequately chosen (for instance, if the converter operates in CCM then dref = 0.5, as indicated in Fig. 2), then isensed [n] is a scaled version of the average inductor current. The lower comparator Cdcm detects Rs iL = 0, providing the information to set dref to the appropriate value when the converter operates in DCM. Fig. 3 shows the main operating waveforms at the inputs of the comparator Cm ain . From the latter gure and using simple geometrical considerations, the following equation can be obtained: tp = dref + gcom p ( v+ v ) (1) dp = Tsw

Fig. 3.

Operating waveforms of the proposed current sensor.

dp being the duty cycle of the pulse obtained at the output of the comparator Cm ain , gcom p the equivalent gain of the comparator, and dref a constant value that depends on the conduction mode of the inductor. Note from (1) that dref equals the value of dp when v+ = v : this fact will be used to deduce dref in Sections II-A and II-B. The notation indicates the averaging operation over one switching cycle. gcom p can be easily deduced taking into account that the operation of the comparator is similar to that of a conventional pulse-width modulator gcom p Gcom p = 1 V+,p eaktop eak (2)

with Gcom p being the value of gcom p when the inherent onecycle delay of the comparator operation is neglected, and V+,p eak -top eak the amplitude of the triangular waveform input (as shown in Fig. 3), which in turn depends on the inductor current ripple. The pulse-width measurement block turns the output pulse duty cycle dp into the digital signal dp [n]. After that, the quantity dref is subtracted from dp [n], thus generating an error signal de [n] which is the input to the sensor loop compensator C (z). The output of the compensator isensed [n] is turned back to the analog domain by the D/A converter formed by a second-order modulator and a simple, rst-order low-pass lter. The modulator, driven by the FPGA high-frequency clock, generates a bit pattern that contains a signicant amount of high-frequency noise but whose average

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Fig. 4.

Block diagram of the system. Fig. 5. Operating waveforms of the proposed current sensor in DCM.

value equals its input signal [18]. The pattern is directly output by the FPGA, a logic 1, thus, corresponding to the FPGA supply voltage and a logic 0 corresponding to 0 V, and ltered using a low-passRC network. The lter eliminates the high-frequency noise and recovers the average current information. Therefore, the voltage at the negative input of Cm ain is an scaled analog version of isensed [n] and the modulator-lter set acts as a D/A converter. Taking into account (1) and Fig. 2, the block diagram shown in Fig. 4 can be obtained, where gD/A is the transfer function of the D/A conversion stage. From this diagram, the transfer function between isensed and iL is isensed Tsensor = Rs iL 1 + Tsensor gD/A Tsensor being dened as Tsensor = gcom p C (z) . If the loop gain Tsensor gD/A fullls Tsensor gD/A (3) becomes isensed = Rs iL . gD/A (4) 1, then (3)

Fig. 6.

Dynamic model of the proposed sensor.

B. Discontinuous Conduction Mode Operation Fig. 5 shows the operating waveforms when the inductor is operating in DCM. Once again, geometrical considerations on Fig. 5 lead to the following expression for dref : dref = (D + ) 1 D+ 2 . (8)

(5)

Neglecting delays, gD/A can be approximated by GD/A , and thus, (5) can be written as follows: isensed Rs iL . GD/A (6)

Equation (8) can easily be extended to CCM operation by substituting = 1 D. Measurement of the quantity D + requires detection of the zero-crossing instant of the inductor current, which is the function of the DCM comparator Cdcm shown in Fig. 2. This analysis demonstrates that an adjustment of the reference signal of the sensor feedback loop allows an appropriate measurement of the average inductor current regardless of the conduction mode. III. DYNAMIC MODEL As the proposed sensor operates in closed loop, a dynamic analysis is required to ensure its stability and dynamic performance during transients. Fig. 6 shows a dynamic model of the proposed sensor, which can be obtained from Fig. 4. The perturbed variables are indicated with hats. The dynamic analysis performed in this section is valid only for CCM operation, as additional effects caused by the variation of dref that takes place in DCM operation have been neglected to simplify the analysis. However, the same methodology can be applied to DCM operation in a straightforward manner. Note that the sampling period of the Z-domain transfer functions is equal to the switching period. The complete transfer function for the comparator stage can be expressed as follows: gcom p (z) = Gcom p z 1 (9)

Therefore, the internal signal isensed is a digital representation of the average inductor current. The following sections establish the appropriate values for the reference pulse width dref to ensure that the average inductor current can be measured accurately in both CCM and DCM. A. Continuous Conduction Mode Operation The waveforms in Fig. 3 correspond to CCM operation. Simple geometrical considerations imply that dref = 0.5, i.e., when v+ = v the width of the output pulse of the main comparator equals 0.5. Thereby, in CCM operation (1) can be expressed as follows: tp = 0.5 + gcom p ( v+ v ) (7) dp = Tsw and a pulse width equal to 0.5 has to be used as the reference in the sensor feedback loop to achieve the desired operation.

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with Gcom p being the value used in Section II for gcom p when the delay was neglected. As Gcom p depends on the current slope, its value changes with the converter topology. For instance, in the case of the boost converter, (9) becomes gcom p (z) = L z 1 Rs DTsw Vin (10)

D being the steady-state duty cycle, Vin the converter input voltage, L the inductance value, and Rs the sensor gain (in volts per ampere). In the case of the buck converter, (9) becomes gcom p (z) = L z 1 Rs (1 D) Tsw Vout (11)

Vout being the output voltage. Note that in both cases Gcom p is expressed in V 1 , as expected from (2). In general the comparator gain can be expressed as follows: gcom p (z) = 1 z 1 . RsiL (12)
Fig. 7. Bode diagram of the most representative transfer functions in the buck converter design: G i L , d and H se n so r are shown, the latter for different values of K .

As the modulator inside the D/A operates at a much higher frequency than the rest of the loop, the dynamic behavior of the low-pass lter can be neglected. Thereby, a simple zeroorder hold (ZOH) model with gain can be used for the D/A gD/A (z) = GD/A z 1 . (13)

The constant GD/A depends on the D/A implementation, i.e., on the amplitude of the digital signal at the output of the modulator. The simplest C (z) that guarantees zero steady-state error is an integrator K . 1 z 1 Substituting (10), (13), and (14) into (3) C(z) = Hsensor (z) = isensed iL = (14)

certain inductor current ripple, the dynamic performance achievable is independent of the switching frequency, duty cycle, or input or output voltage. A. Design Example A: Buck Converter In this section, the proposed current sensor is designed to measure the inductor current of a buck converter with the following parameters: Vin = 12 V, Vout = 3.3 V, fsw = 250 kHz, L = 5.6 H, C = 15 F. The rated load is Rload = 0.33 . The rest of the parameters are GD/A = 3.3 V/A and Rs = 0.2 . It was assumed that the nal goal was to design an inner current loop: to do so, the loop gain, comprised as usual by the power stage plant and the transfer function of the sensor, was analyzed. The small-signal transfer function from the duty cycle to the inductance current, GiL ,d , and the transfer function of the sensor, Hsensor , given by (15), are plotted in Fig. 7. It can be appreciated that the cutoff frequency of Hsensor is beyond 10 kHz, and therefore, a relatively high bandwidth can be achieved in the current loop. However, compared to a conventional analog average-current control design (in which Hsensor can be considered constant), it can be seen that the proposed sensor adds high frequency poles to the loop gain. The additional phase lag, which should be taken into account in the compensator design, effectively reduces the achievable bandwidth compared to traditional analog average current-mode control. B. Design Example B: Boost Converter The proposed current sensor was designed to measure the input current in a dcdc boost converter with the following parameters: Vin = 12 V, Vout = 19 V, fsw = 100 kHz, L = 35 H, C = 60 F. The rated load was Rload = 8 . The rest of the parameters were GD/A = 3.3 and Rs = 0.605 . The smallsignal transfer function from the duty cycle to the inductance current GiL ,d and the transfer function of the sensor given by

Rs zGcom p K . (15) z 2 z + Gcom p GD/A K

The closed-loop poles of (15) can be used to derive stability conditions and to analyze the theoretical dynamic performance of the proposed sensor. For instance, in the case of the boost converter, stability is guaranteed if K < Klim it,b o ost = 1 Rs DTsw Vin = Gcom p GD/A LGD/A (16)

while in the case of the buck converter the maximum K value is 1 Rs (1 D) Tsw Vout K < Klim it,buck = = . Gcom p GD/A LGD/A (17) Once again, in general the stability condition can be expressed as Rs iL . (18) K < Klim it = GD/A Equation (18) relates the dynamic performance of the sensor with the design of the power stage; the inductor current ripple is the only power stage design parameter that determines the achievable bandwidth of the proposed sensor. Therefore, for a

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TABLE I MAIN PARAMETERS USED IN THE SIMULATION OF THE DCDC BOOST

Fig. 8. Bode diagram of the most representative transfer functions in the boost converter design: G i L , d and H se n so r are shown, the latter for different values of K .

(15) are plotted in Fig. 8. Once again, the sensor achieves a relatively high bandwidth but, as in the case of the buck converter, the additional high-frequency poles add extra phase lag. Again, it should be noted that compared to a traditional analog average current-mode control [19], the sensor modies the openloop transfer function of the system. The compensator should be designed including the effects of Hsensor , which implies the following. 1) The bandwidth of the control loop will be limited at least by the bandwidth of the sensor (BWclosedlo op < BWsensor ). 2) For a given desired crossover frequency, additional phase lead needs to be provided to compensate for the phase lag introduced by Hsensor . The simulation and experimental results in the following sections show that the proposed sensor is able to provide precise and accurate measurements of the average inductor current and that it can be successfully used in dcdc converters as well as in acdc PFC applications. IV. SIMULATION RESULTS A. DCDC Boost Converter A dcdc boost converter operating in open-loop and the proposed sensor were simulated in Simulink. The power stage reactive components were: L = 35 H, C = 60 F and the switching frequency was fsw = 100 kHz. The input and output voltages were Vin = 12 V and Vout = 19 V, respectively, while the rated load was R = 8 . Table I shows the remaining design parameters. The D/A was simulated using a second-order operating at 100 MHz, along with a rst-order low-pass lter with a cutoff frequency close to 200 kHz. The current sensor compensator C (z) was chosen as in (14), and after that Sisotool was used to nd a value of K that yielded an appropriate phase margin and closed-loop bandwidth. A de-

sign with K = 0.1 was chosen, yielding a phase margin of 52 and bandwidth close to 10 kHz. Fig. 9(a) and (b) shows the sensor in steady state. Fig. 9(a) shows the estimated digital current isensed once scaled, along with the actual inductor current iL and the average inductor current iL obtained by low-pass ltering iL using a second-order lter. It can be seen that the scaled version of isensed precisely matches the average inductor current. Fig. 9(b) shows the same waveforms depicted in Fig. 9(a) but when the inductor operates in DCM, it can be seen that the sensor still provides the actual current, therefore, conrming the validity of the approach described in Section II-B. As already mentioned, the required value of dref given by (8) was obtained by measuring the inductor conduction period: according to Fig. 5, the duration of such interval directly provides the quantity (D + ) Tsw . Fig. 9(c) and (d) shows the sensor response under a load step. In spite of the noticeably underdamped response, the sensor keeps track of the average current. Fig. 9(d) shows the response in detail, where it can be observed the delay that takes place in the current measurement process. B. ACDC Boost Power Factor Preregulator A boost PFP and the current sensor were also simulated using ModelSim. Fig. 10 shows an schematic diagram of the system. Due to the discrete-time nature of ModelSim simulations, appropriate models were written in VHDL for the sensor low-pass lter and the power stage, following the approach described in [20]. The power stage reactive components were: L = 3 mH, C = 220 F and the switching frequency was fsw = 100 kHz. The input voltage was vac = 220 Vrm s , f = 50 Hz, and the output voltage was around Vout = 400 V. As the goal of the simulation was to show the use of the sensor in a conventional PFC application, only the inductor current loop was closed, whereas the output voltage was left unregulated. Therefore, the input voltage was scaled through Gin to obtain the inductor current reference, thus establishing the power delivered by the PFP. The load was R = 450 . Table II shows the remaining design parameters. Note that in this application the selection of the sensor gain has to take into account the varying input voltage; theoretically, at the input voltage zero crossings, the inductor current ripple would be zero, causing instability in the current sensor according to (18). However, in practice the maximum duty cycle is usually limited (and the input voltage never reaches zero due to the presence of additional input capacitance), thus establishing a lower limit for the minimum inductor current ripple. Fig. 11 shows the sensor transfer function for the minimum and maximum calculated inductor current ripple (minimum and

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Fig. 9. Simulation results: (a) CCM steady-state operation; (b) DCM steady-state operation; (c) 100 % to 50 % load step; and (d) detailed view of the waveform in Fig. 9(c).

Fig. 10.

Schematic diagram of the acdc boost PFP. Fig. 11. Transfer function of the current sensor for the minimum and maximum values of K lim .

TABLE II MAIN PARAMETERS USED IN THE SIMULATION OF THE ACDC BOOST PFP

maximum values of Klim , respectively). Thus, a conservative design with K = 0.025 was selected, providing an useful bandwidth of the sensor of around 1 kHz. Therefore, to ensure an

appropriate operation of the system, the bandwidth of the inner current-loop controller was selected to be around 1 kHz. The current loop compensator was designed following [21]. A different approach based on adjusting K as a function of the input voltage can easily be implemented in a digital system, and might be able to maximize the sensor bandwidth. However, this paper

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Fig. 12. Boost PFP simulation results obtained using ModelSim: (a) input voltage, V in ; (b) input (inductor) current, iL ; (c) sensed digital current, ise n se d [n]; and (d) negative input of the main comparator, v .

focused on the simplest possible implementation, and therefore, a xed value of K was used. Once again, the D/A was simulated using a second-order operating at 100 MHz, along with a rst-order low-pass lter with a cutoff frequency of 200 kHz. Fig. 12 shows the most representative operating waveforms. Fig. 12(a) and (b) shows the input voltage Vin and inductor current iL , respectively. It can be seen that the sensor enables PFC, achieving an almost sinusoidal input current. A slight distortion is observed after the zero crossing of the input voltage. This distortion arises due to the limit established in the duty cycle, which causes the current compensator to saturate near the zero crossings. Fig. 12(c) shows the digital version of the average inductor current isensed . The negative input of the main comparator, v , i.e., the analog scaled version of the sensed current, is shown in Fig. 12(d).

A. Current Sense Circuitry Fig. 13 shows a simplied diagram of the inductor current sense circuitry, which was built in a separate board and attached to each corresponding power stage. A shunt resistor in series with the inductance was used as a current to voltage converter. A dual OPA2727 was then used to amplify the signal in two stages. After that, two low cost, precision comparators (TL3016 from Texas Instruments) were required to implement the comparators Cm ain and Cdcm in Fig. 2: Cm ain compares Rs iL with v , while Cdcm detects the zero crossing of the inductor current to allow DCM operation. Finally, the board included the rst-order lowpass lter of the D/A converter. A 2 k-220 pFRC lter was used, yielding around 750-kHz cutoff frequency, low enough to eliminate the high-frequency noise produced by the modulator. Note that these values can be adjusted depending on the FPGA clock frequency, the allowable ripple at the negative input of Cm ain (which in turn depends on the current ripple), and the dynamic requirements of the current sensor. B. Pulse Width Measurement and Reference Generator Implementations of the pulse-width measurement block and the reference generator are shown in Fig. 14(a) and (b), respectively. The pulse-width measurement block is a simple counter that uses a high-frequency clock clk for improved resolution. It

V. EXPERIMENTAL RESULTS In this section, two scenarios that mimic Section IV are described: Section V-C shows a dcdc boost converter and the sensor operating in open loop, whereas Section V-D shows an acdc boost PFP. Section V-A describes the current sense circuitry, common to both scenarios.

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TABLE III LOGIC RESOURCES USED BY THE REFERENCE GENERATOR AND THE PULSE WIDTH MEASUREMENT BLOCKS

Fig. 13.

Simplied diagram of the current sense circuitry.

Fig. 15.

Experimental dcdc boost converter setup.

Table III shows a summary of the amount of logic resources required by each block. The results have been obtained using Quartus II software, v. 10, and a Cyclone II EP2C35F672 FPGA. For the sake of comparison, the overall logic element usage represents around 0.2 % of the available logic in the aforementioned FPGA.
Fig. 14. (a) Implementation of the pulse width measurement system and (b) implementation of the reference generator.

C. DCDC Boost Converter A boost converter with the same parameters described in Section IV-A was built in the laboratory. This 12-V input, 19-V output, 50-W converter, designed to supply laptop computers from a 12-V battery, was used to test the proposed current sensor. Fig. 15 shows the experimental setup, where the additional hardware board with the analog current sense circuitry is highlighted. A 5-m sense resistor was used, and a gain of 11 was set in each of the amplication stages, thus providing an overall sense gain Rs equal to 0.605 V/A. The MOSFET and diode used to build the power stage were a STP60N from STMicroelectronics and a 8TQ100 from Vishay Semiconductor, respectively. A commercial off-the-shelf inductor from Coilcraft was also used. An Altera DE2 development board that includes a Cyclone II FPGA was used to implement all the digital hardware. All the required blocks were programmed in VHDL, and especial care was taken with the synchronization of the different parts of the system to avoid additional delays in the sensor loop, which might compromise the dynamic performance of the system. The value of K was set close to 0.1, to match as much as possible the simulation scenario described in Section IV. The remaining required hardware, as the digital pulse-width modulator used to control the power MOSFET, and/or other auxiliary blocks, were also implemented in the FPGA. Fig. 16 shows steadystate measurements that were obtained to test the accuracy of

is enabled by the input pulse and reset in every switching period. The reference generator is also based on a simple counter enabled at the beginning of the switching period and stopped by the output of Cdcm . This counter is also reset in every switching period. Note that Fig. 2 includes a multiplexer to select between a xed dref equal to 0.5 (for CCM operation) and the reference generator output (for DCM operation). The actual implementation shown in 14(b) is slightly simpler, taking advantage of the fact that (8) is valid for both CCM and DCM operation. Given that both counters use the internal high-frequency clock of the digital system, the time resolution of both blocks is Tclk = 1/fclk , which can be expressed in terms of the equivalent number of bits, nb,eq , of dp and dref as nb,eq = log2 fclk . fsw (19)

As an example, in the experiments presented in this section the clock frequency was 100 MHz, whereas the switching frequency was set to a value slightly below 100 kHz, thus allowing exactly 10 bits of resolution in both dp and dref . Note that the number of bits of dp and dref determines the effective resolution of the sensor, i.e., the number of bits in isensed [n].

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Fig. 16. Steady-state measured average input current, iL , and v (the analog scaled version of ise n se d ).

Fig. 18. Experimental results in DCM operation: (a) dre f is kept constant and equal to 0.5; (b) dre f is modied according to (8).

Fig. 17. Experimental results: (a) steady-state operation (14- load); and (b) steady-state operation (10- load).

the sensor. The average input current was measured using a precision multimeter, along with an HP current shunt, model 34330A. The internal resolution of the sensor, i.e., the resolution chosen for isensed , was set to 10 bits. The worst-case error measured was less than 2 %. Thus, Fig. 16 demonstrates that the sensor is capable of accurately measuring the average inductor current. Fig. 17(a) and (b) shows both inputs of the comparator, signals v+ = Rs iL and v , the analog scaled version of isensed , when the converter is in steady state and for two different load values. It can be seen that the average value of both signals is the same, as was predicted by (6), and that the sensor performs as expected in steady state.

If the sensor is prepared to operate only in CCM then an error arises when the converter enters in DCM. The boost converter used in this section, operating at 100 kHz, enters in DCM at very low inductor current. Therefore, the error in the current measurement is small compared with the rated current. In order to better observe the error caused by the DCM operation, the switching frequency was decreased to 50 kHz, thus allowing DCM operation to occur with relatively high inductor current and increasing the relative error of the current measurement. Fig. 18(a) shows the main waveforms when the converter operates in DCM and dref = 0.5, i.e., only CCM operation of the sensor was allowed. The actual average input current was close to 1.48 A, while the current measured by the sensor was 1.1 A, i.e., the relative error was close to 25 %. Fig. 18(b) shows the operation of the system when dref was appropriately modied according to (8). The actual input current was then 1.49 A, and the measured current was 1.514 A, i.e., the error dropped to 1.6 %, a value consistent with the results shown in Fig. 16. Finally, several load steps were carried out to test the dynamic performance of the sensor. Fig. 19 shows the positive input of the comparator, v+ = iL Rs , and the scaled version of the sensed current, v = isensed GD/A , under 814 and 148 load steps, respectively. It can be seen that the sensor tracks the average inductor current, as expected. Furthermore, the results are in good agreement with those obtained in the simulations shown in Section IV. Slightly higher damping and smaller settling time can be appreciated, probably caused by nonidealities that were not appropriately accounted for in the simulations, e.g., the actual MOSFET and inductor parasitic resistances,

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Fig. 21.

Experimental results obtained with the boost PFP.

Fig. 19.

iL and v under various load steps: (a) 814 ; (b) 148 .

Fig. 20.

Boost PFP prototype (130 mm 100 mm).

and also by a slightly smaller inductance value that was nally used. D. ACDC Boost Power Factor Preregulator A boost PFP with the same parameters described in Section IV-B, which is shown in Fig. 20, was built in the laboratory. The current sensor circuitry was the same described in Section V-A. In this case a 0.5- sense resistor was used and the overall gain of the amplication stage was set to 2, thus providing an overall sense gain Rs equal to 1 V/A. The MOSFET and diode used to build the power stage were a IRFP27N60K from Vishay and a RHRP860 from Fairchild Semiconductor, respectively. A custom inductor of the required value was built using a soft-saturation core, Kool- 77071. It is interesting to note that, in an effort to minimize the amount of hardware required, the input voltage is acquired using

Fig. 22. current.

Experimental results: (a) sensed input voltage and (b) sensed inductor

a sigma-delta A/D converter, as described in [22]. This approach requires only an additional comparator and a low-pass lter, and can be easily extended to measure the output voltage. Therefore, the PFP presented here does not require conventional A/D chips; furthermore, it uses very few external components in addition to the power stage, as the complete control and a major part of the

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sensing are carried out by digital means. The same Altera DE2 development board was used to implement the digital hardware, including among other things the digital current control loop for the converter, the pulse-width modulator and the modulator used to measure the input voltage. Fig. 21 shows an example of the results obtained for an output power of 240 W. The analog scaled version of isensed , v , is shown along with the line current and voltage. It can be seen that sinusoidal input current was achieved, and that the results closely matched the simulations presented in Section IV-B. The measured power factor was 0.999. Fig. 22(a) shows the sampled input voltage, whereas Fig. 22(b) shows the digital current. It can be seen that the input voltage was correctly sampled through the A/D, and that the current sensor provided the correct sinusoidal waveform.

VI. CONCLUSION An average inductor current sensor for digitally controlled SMPS has been presented in this paper. The proposed sensor allows the average inductor current to be precisely measured without an expensive A/D converter. As it operates in a closedloop manner, its dynamic performance and stability conditions were analyzed in this paper, showing that it was capable of reaching relatively high bandwidths. Its inuence over the loop gain of the converter, by means of additional high-frequency poles that add additional phase lag compared to conventional analog designs, was also highlighted. Thorough simulations were presented to demonstrate the feasibility of the sensor concept, and experimental results were obtained by means of a dcdc boost converter prototype operating in open loop, as well as using a boost PFP in closed-loop operation. The proposed sensor can help to simplify the hardware implementation of digitally controlled current-mode SMPS, and it has been demonstrated in this paper that it is especially suitable for digitally controlled PFC applications, as it enables a very simple and hardware-effective realization.

[7] P. Midya, P. Klein, and M. F. Greuel, Sensorless current mode controlan observer-based technique for DC-DC converters, IEEE Trans. Power Electron., vol. 16, no. 4, pp. 522526, Jul. 2001. [8] Y. Qiu, X. Chen, and H. Liu, Digital average current digital average current-mode control using current estimation and capacitor charge balance principle for DC-DC converters operating in DCM, IEEE Trans. Power Electron., vol. 25, no. 6, pp. 15371545, Jun. 2010. [9] Z. Lukic, Z. Zhenyu, S. M. Ahsanuzzaman, and A. Prodic, Self-tuning digital current estimator for low-power switching converters, in Proc. Appl. Power Electron. Conf., Feb. 2008, pp. 529534. [10] W. Stefanutti, P. Mattavelli, G. Spiazzi, and P. Tenti, Digital control of single-phase power factor preregulators based on current and voltage sensing at switch terminals, IEEE Trans. Power Electron., vol. 21, no. 5, pp. 13561363, Sep. 2006. [11] J. Sun and M. Chen, Nonlinear average current control using partial current measurement, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 16411648, Jul. 2008. [12] B. Mather and D. Maksimovi , A simple digital power-factor correction c rectier controller, IEEE Trans. Power Electron., vol. 26, no. 1, pp. 919, Jan. 2011. [13] F. J. Azcondo, A. de Castro, V. L pez, and O. Garca, Power factor o correction without current sensor based on digital current rebuilding, IEEE Trans. Power Electron., vol. 25, no. 6, pp. 15271536, Jun. 2010. [14] H.-C. Chen, Single-loop current sensorless control for single-phase boost-type SMR, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 163 171, Jan. 2009. [15] H.-C. Chen, C.-C. Lin, and J.-Y. Liao, Modied single-loop current sensorless control for single-phase boost-type SMR with distorted input voltage, IEEE Trans. Power Electron., vol. 26, no. 5, pp. 13221328, May 2011. [16] B. Mather and D. Maksimovi , Single comparator based A/D converter c for output voltage sensing in power factor correction rectiers, in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2009, pp. 13311338. [17] K. I. Hwu and Y. T. Yau, Applying a counter-based PFM control strategy to an FPGA-based SR forward converter, in Proc. IEEE Region 10 Trends Developments Converg. Technol. Conf., 2006, pp. 14. [18] R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press, ch. 3, pp. 6389. [19] L. Dixon, Average current mode control of switching power supplies, Unitrode Design Seminars, no. 700, topic 5, 1990. [20] F. J. Azcondo, A. de Castro, and C. Bra as, Course on digital electronics n oriented to describing systems in VHDL, IEEE Trans. Ind. Electron., vol. 57, no. 10, pp. 33083316, Oct. 2010. [21] R. W. Erickson and D. Maksimovi , Fundamentals of Power Electronics. c Norwell, MA: Kluwer, 2001. [22] V. M. L pez, F. J. Azcondo, F. J. Daz, and A. de Castro, Autotuning o digital controller for current sensorless power factor corrector stage in continuous conduction mode, in Proc. IEEE Workshop Control Model. Power Electron., 2010, pp. 18.

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[1] D. Maksimovi , R. Zane, and R. Erickson, Impact of digital control in c power electronics, in Proc. 16th Power Semicond. Devices ICs, May 2004, pp. 1322, 2012. [2] A. Peterchev, X. Jinwen, and S. Sanders, Architecture and IC implementation of a digital VRM controller, IEEE Trans. Power Electron., vol. 18, no. 1, part 2, pp. 356364, Jan. 2003. [3] A. de Castro, P. Z mel, O. Garca, T. Riesgo, and J. Uceda, Concurrent u and simple digital controller of an AC/DC converter with power factor correction based on an FPGA, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 334343, Jan. 2003. [4] H. Peng and D. Maksimovi , Digital current-mode controller for DC-DC c converters, in Proc. IEEE Appl. Power Electron. Conf. Expo., Mar. 2005, vol. 2, pp. 899905. [5] W. Stefanutti, E. Della Monica, E. Tedeschi, P. Mattavelli, and S. Saggini, Reduction of quantization effects in digitally controlled dc-dc converters using inductor current estimation, in Proc. IEEE Power Electron. Spec. Conf., Jun. 2006, pp. 17. [6] O. Trescases, Z. Lukic, W. Tung, and A. Prodic, A low-power mixedsignal current-mode DC-DC converter using a one-bit DAC, in Proc. IEEE Appl. Power Electron. Conf. Expo., 2006, p. 5.

Miguel Rodrguez (S06) was born in Gij n, Spain, o in 1982. He received the M.S. and Ph.D. degrees in telecommunication engineering both from the University of Oviedo, Oviedo, Spain, in 2006 and 2011, respectively. Since January 2011, he has been a Research Associate in the Colorado Power Electronics Center, University of Colorado, Boulder. His research interests include dc/dc conversion, digital control of switched converters, and power-supply systems for RF ampliers.

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Victor Manuel L pez (S10) was born in o Torrelavega, Cantabria, Spain, in 1985. He received the Electronics and Control Engineering degree from the University of Cantabria, Santander, Spain, in 2009, where since then he has been working toward the Ph.D. degree in the Department of Electronics Technology, Systems and Automation Engineering. His research interests include design, modeling, and digital control of topologies for power factor correction applications. Mr. L pez received the IEEE/IEL Electronic o Library Award in 2009.

Javier Sebasti n (M87SM11) was born in a Madrid, Spain, in 1958. He received the M.Sc. degree from the Polytechnic University of Madrid, Madrid, Spain, in 1981, and the Ph.D. degree from the University of Oviedo, Gij n, Spain, in 1985. o He was an Assistant Professor and an Associate Professor with both the Polytechnic University of Madrid and the University of Oviedo. Since 1992, he has been with the University of Oviedo, where he is currently a Professor. His research interests include switching-mode power supplies, modeling of dc-todc converters, low-output-voltage dc-to-dc converters, and high-power-factor rectiers.

Francisco J. Azcondo (S90M92SM00) received the Electrical Engineering degree from the Universidad Polit cnica de Madrid, Madrid, Spain, in e 1989, and the Ph.D. from the University of Cantabria, Santander, in 1993. From 1990 to 1995, he was involved in the designing of highly stable quartz crystal oscillators. Since 1995, he has been an Associate Professor in the Department of Electronics Technology, Systems and Automation Engineering, University of Cantabria. From February 2004 to August 2010, he was a Special Member of the Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, and in the summer of 2006, he was a Visiting Researcher in the Department of Electrical and Computer Engineering, University of Toronto, ON, Canada. His research interests include switch-mode power converters and their control for discharge lamps, electrical discharge machining, arc welding, and power factor correction applications. Dr. Azcondo was the Chair of the IEEE Industrial Electronic Society and Power ELectronics Society Spanish Joint Chapter, from September 2008 to June 2011. Since 2005, he has been an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS in the eld of Power Electronics.

Dragan Maksimovic (M89SM04) received the B.S. and M.S. degrees in electrical engineering from the University of Belgrade, Belgrade, Yugoslavia, in 1984 and 1986, respectively, and the Ph.D. degree from the California Institute of Technology, Pasadena, in 1989. From 1989 to 1992, he was with the University of Belgrade. Since 1992, he has been with the Department of Electrical, Computer and Energy Engineering, University of Colorado, Boulder, where he is currently a Professor and the Director of the Colorado Power Electronics Center (CoPEC). His current research interests include mixed-signal integrated circuit design for control of power electronics, digital control techniques, as well as energy efciency and renewable energy applications of power electronics. Dr. Maksimovic received the 1997 National Science Foundation CAREER Award, the IEEE Power Electronics Society Transactions Prize Paper Award in 1997, the IEEE Power Electronics Society Prize Letter Awards in 2009 and 2010, the Holland Excellence in Teaching Awards in 2004 and 2011, and the University of Colorado Inventor of the Year Award in 2006.