Storage cache Memor y

Computer storage is structured into a structure. At the biggest stage (closest to the processor) are the processer signs up. Next comes one or more stages of cache. When several stages are used, they are denoted L1, L2, etc Next comes main memor y, which is usually created out of a powerful random-access memor y (DRAM). All of these are regarded inner to the pc. The hierarchy carries on with exterior storage, with the next stage generally being a fixed difficult drive, and one or more stages below that created up of detachable media such as ZIP capsules, visual drives, and record. As one goes down the storage structure, one discovers reducing cost/bit, increasing capacity, and more slowly accessibility time. It would be awesome to use only the quickest storage,but because that is the most costly storage, we business off accessibility some time to cost by using more of the more slowly storage. The key is to arrange the information and programs in storage so that the storage terms needed are usually in the fastest memor y. In common, it is likely that most upcoming accesses to primar y storage by the processor will be to places lately accesses. So the cache instantly maintains a duplicate of some of the lately used terms from the DRAM. If the cache is designed properly, then most of enough time the processer will ask for storage terms that are already in the cache.
Computer Memor y Program Over view Characteristics of Memor y Systems Location Processor Internal primar y memory External additional memor y Capacity Term dimension organic device or organization Variety of terms variety of bytes Unit of Transfer Internal o Usually controlled by bus width External o Usually a prevent which is much bigger than a word

 Addressable unit o Tiniest place which can be exclusively addressed o Group on exterior disk Access Methods Successive tape o Begin at the starting and study through in order o Access time relies on place of information and past location Immediate disk o Personal prevents have exclusive address o Access is by getting to area plus sequential search o Access time relies on place of information and past location Unique - RAM o Personal details recognize place exactly o Access time is separate of information place and past location Associative cache o Information is situated by a evaluation with material of a part of the store o Access time is separate of information place and past location Performance Access time (latency) o The time between introducing an deal with and getting entry to legitimate data Memor y Pattern time mainly random-access memor y o Time may be needed for the storage to recover before the next access o Access time plus restoration time Exchange rate o The amount at which information can be moved into or out of a storage unit Physical Types Semiconductor RAM Attractive drive and tape Optical CD and DVD Magneto-optical Physical Characteristics Volatile/non-volatile Erasable/non-erasable Energy requirements Organization The actual agreement of pieces to type words The apparent agreement is not always used The Memor y Hierarchy How much? o If the potential is there, applications will be developed to use it. How fast?

o To accomplish performance, the storage must be able to keep up with the processor. How expensive? o For a realistic system, the price of storage must be affordable in relationship to other components There is a trade-off among the three key features of memor y: price, potential, and accessibility time. Quicker accessibility time higher price per bit Greater potential small price per bit Greater potential more slowly accessibility time The way out of this situation is not to depend on only one storage element or technology. Implement a storage structure.

As one goes down the hierarchy: (a) decreasing cost per bit; (b) increasing capacity; (c) increasing access time; (d) decreasing frequency of access of the memor y by the processor. Thus smaller, more expensive, faster memories are supplemented by larger, cheaper, slower memories. The key to the success of this organization is item (d). Locality of Reference principle Memor y references by the processor, for both data and instructions, cluster Programs contain iterative loops and subroutines - once a loop or subroutine is entered, there are repeated references to a small set of instructions

 Operations on tables and arrays involve access to a clustered set of data word Cache Memor y Principles Cache memor y Small amount of fast memor y Placed between the processor and main memor y Located either on the processor chip or on a separate module

Storage cache Function Over view Processer demands the material of some storage location The cache is examined for the asked for data o If discovered, the asked for term is sent to the processor o If not discovered, a prevent of primar y storage is first study into the cache, then the requested term is sent to the processor When a prevent of information is fetched into the cache to fulfill only one memor y reference, it is likely that there will be upcoming sources to that same memor y location or to other terms in the prevent area or referrals concept. Each block has a tag included to recognize it.

example of a typical cache organization is shown below:

Elements of Cache Design Cache Size Small enough so overall cost/bit is close to that of main memor y Large enough so overall average access time is close to that of the cache alone o Access time = main memory access time plus cache access time Large caches tend to be slightly slower than small caches Mapping Function An algorithm is needed to map main memory blocks into cache lines. A method is needed to determine which main memor y block occupies a cache line. Three techniques used: direct, associative, and set associative. Assume the following: Cache of 64 K bytes Transfers between main memor y and cache are in blocks of 4 bytes each cache organized as 16K = 2^14 lines of 4 bytes each Main memory of 16 M bytes, directly addressable by a 24-bit address (where 2^24 = 16M) main memor y consists of 4M blocks of 4 bytes each Direct Mapping Each block of main memor y maps to only one cache line * cache line # = main memor y block # % number of lines in cache * Main memor y addresses are viewed as three fields * Least significant w bits identify a unique word or byte within a block * Most significant s bits specify one of the 2^s blocks of main memor y * Tag field of s-r bits (most significant)

Line field of r bits identifies one of the m = 2^r lines of the cache

Tag (s-r)

Word (w)

Line or Slot (r) 14 bits

8 bits

14 bits

14 bits 24 bit address 2 bit word identifier 22 bit block identifier 8 bit tag (22-14) 14 bit slot or line No two blocks in the same line have the same Tag field Check contents of cache by finding and checking Tag

Direct Mapping Cache Organization

Direct Mapping Summar y Address length = (s+w) bits Number of addressable units = 2^(s+w) words or bytes Block size = line size = 2^w words or bytes Number of blocks in main memory = 2^(s+w)/2^w = 2^s

 Number of lines in cache = m = 2^r Size of tag = (s-r) bits Direct Mapping Pros and Cons Simple Inexpensive Fixed location for a given block o If a program accesses two blocks that map to the same line repeatedly, then cache misses are ver y high Associative Mapping A main memor y block can be loaded into any line of the cache A memory address is interpreted as a tag and a word field The tag field uniquely identifies a block of main memor y Each cache lines tag is examined simultaneously to determine if a block is in cache Associative Mapping Cache Organization:

Example of Associative Mapping

Pentium 4 and PowerPC Cache Organizations Pentium 4 Cache Organization 80386 no on chip cache 80486 8k bytes using 16 bytes/lines and 4-way set associative organization Pentium (all versions) two on chip L1 caches o Data and instructions Pentium 4 o L1 caches 8k bytes 64 bytes/line 4-way set associative o L2 cache Feeds both L1 caches 256k bytes 128 bytes/line 8-way set associative

Pentium 4 Block Diagram