Scaling of MOSFETs

Siva Theja M Department of Electrical Engineering IIT Madras Advisor: Prof Amitava Das Gupta

Indo German Winter Academy 2006 11th December 2006, Digha

Overview
MOS Capacitor and MOSFET Mobility Models Subthreshold Conduction Scaling Problems arising during Scaling

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MOS Capacitor
Accumulation Depletion Inversion Strong inversion

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MOS Capacitor
Threshold voltage

Qi Qd VT = ms + 2F C i Ci
Substrate bias effect or body effect

Vth = ( 2 B VBS 2 B )

2 s qN A = Cox

Gamma is called body effect parameter.

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MOSFET

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MOSFET
Gradual channel approximation

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Mobility and Electric Fields

Dependence of mobility on gate voltage, Transverse electric field Universal mobility Degradation curve

o = 1 + (VG VT )

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Mobility and Electric Fields

Dependence of mobility on drain voltage or longitudinal electric field Saturation of velocity ID would be linearly dependent on VG and not quadratically for short channel MOSFETs

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Subthreshold Characteristics
Z kT ID = (Cd + Cit ) L q
Ci is gate capacitance Cd is depletion capacitance in the channel Cit is the interface state capacitance
2

1 e

qVD kT

q (VGkTVT ) cr e

Cd + Cit cr = 1 + Ci

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Subthreshold Characteristics
S: Subthreshold slope Small S, better switch

kT S = 2.3 q
S depends on

Cd + Cit 1 + Ci

Gate thickness Channel doping No. of interface states Trade off in choosing Vth
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Scaling
Introduction to scaling Scaling in MOSFETS Why scaling? Moores Law

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Why Scaling?

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Lets Start

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Types of Scaling
Constant voltage scaling Purely geometrical Only lateral dimensions are reduced Longitudinal electric field increases Can cause break down

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Consequences of Constant Voltage Scaling

Drain current ID is unchanged Transconductance is unaffected Capacitance CG decreases as k2 Charging time decreases as k2 So, higher clock speeds can be obtained

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Consequences of Constant Voltage Scaling

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Short Channel Effects No longer resembles planar capacitor

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Short Channel Effects

Change in threshold voltage Clear pinch-off of channel Increased output impedance Increased leakage current (why and its consequences)

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Channel Length Modulation

ID = IDo (1 + VDS) : Channel length modulation factor

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Solution?
Scale all dimensions (lateral dimensions also) so that initial field is recreated

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Constant Field Scaling

All the lengths (LG, Z, dOX) and voltages (VDS, VGS, Vth) are scaled by same factor k Electric field unchanged Punch through effect Sol: Increase doping of acceptor by same factor, k (Scaling of Depletion widths)

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Short Channel Effect

VT decreases with length for very small geometries Charge sharing between source/drain and gate Roll off Change junction depth

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Short Channel Effect

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Narrow width Effect

VT goes up as width is reduced Effective depletion charge increased rather than decreased

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Narrow width Effect

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Consequences of Constant Field Scaling

Assuming VGS = 0

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Consequences of Constant Field Scaling

ID decreases by the factor k Transconductance is unchanged Static power dissipation of one transistor (IV) is scaled by k2 Dynamic power consumption (P f) is scaled by k2 Power per unit area is unchanged Dynamic power per transistor area, is unchanged Delay (CG / ID) is unchanged PDP is scaled by k2

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But
We want newer generation of scaled down transistors to work faster So, supply voltage is scaled by and k not k Higher electric fields, Currents and so, lower delay times This increases dynamic power consumption per unit area

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Yet another problem

Power per device is actually less than k2 Consequently, power per unit area increases Circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes

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Saturated Velocity Model

Saturated velocity model for current Same results

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Hot Electron Effects

High electric field High kinetic energy Hot electrons Gate current, input impedance Oxide charges, interface states Increase of VT Substrate current, impact ionization, output impedance Lightly Doped Drain (LDD)
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Hot Electron Effects

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Drain-Induced Barrier Lowering

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Drain-Induced Barrier Lowering

DIBL and punch-through Reverse-bias to substrate High channel doping Anti-punch through implant through out the channel Halo or pocket implants

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Gate- Induced Drain Leakage

Increase of subthreshold currents for negative gate bias Narrow depletion regions Tunneling Drain doping should be ~1018 cm-3

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Other factors
Interconnect capacitance Process variations The transistor characteristics become less deterministic, but more statistical. This statistical variation increases design difficulty

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Other factors

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Acknowledgements and References

Solid State Electronic Devices Ben G. Streetman Semiconductor Devices Amitava Das Gupta and Nandita Das Gupta The Omniscient Google Wikipedia Presentation by E.F.Schubert, Rensselaer Polytechnic Institute Special thanks to my advicer, Prof. A Das Gupta

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Thank You

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Questions ?

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