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TABLE OF CONTENTS
Summary Specification ........................................................................................................................................................... 5
Description .................................................................................................................................................................................. 5
Features ....................................................................................................................................................................................... 5
Applications ................................................................................................................................................................................. 5
Ordering Information .............................................................................................................................................................. 6
Device Description .................................................................................................................................................................. 7
Architecture ................................................................................................................................................................................. 7
Dark Reference Pixels ............................................................................................................................................................. 8
Dark Dummy Pixels ................................................................................................................................................................. 8
Dummy Pixels .......................................................................................................................................................................... 8
Virtual Dummy Columns ......................................................................................................................................................... 8
Active Buffer Pixels ................................................................................................................................................................. 8
Blue Pixel Buffer ..................................................................................................................................................................... 8
CTE Monitor Pixels .................................................................................................................................................................. 8
Image Acquisition ........................................................................................................................................................................ 9
Charge Transport ........................................................................................................................................................................ 9
Horizontal Register ................................................................................................................................................................... 10
Output Structure .................................................................................................................................................................... 10
Output Load ........................................................................................................................................................................... 11
Physical Description .................................................................................................................................................................. 12
Pin Description and Device Orientation ................................................................................................................................ 12
Imaging Performance ........................................................................................................................................................... 13
Typical Operational Conditions ................................................................................................................................................. 13
Specifications ............................................................................................................................................................................ 13
Monochrome and Color Versions ......................................................................................................................................... 13
Monochrome and Color Versions (Continued) ..................................................................................................................... 14
Color Version Only ................................................................................................................................................................. 14
Color Version Only (Continued) ............................................................................................................................................. 15
Monochrome Versions Only .................................................................................................................................................. 15
Typical Performance Curves ................................................................................................................................................. 17
Defect Definitions .................................................................................................................................................................. 19
Operational Conditions .............................................................................................................................................................. 19
Specifications ............................................................................................................................................................................ 19
Monochrome and Color Versions ......................................................................................................................................... 19
Color Version Only ................................................................................................................................................................. 19
Operation .............................................................................................................................................................................. 21
Absolute Maximum Ratings ...................................................................................................................................................... 21
Power-up Sequence .................................................................................................................................................................. 21
DC Bias Operating Conditions .................................................................................................................................................. 22
AC Operating Conditions ........................................................................................................................................................... 22
Clock Levels ........................................................................................................................................................................... 22
Clock Voltage Detail Characteristics .................................................................................................................................... 23
Capacitance Equivalent Circuit ................................................................................................................................................. 24
Timing ................................................................................................................................................................................... 25
Requirements and Characteristics .......................................................................................................................................... 25
Clock Switching Characteristics ........................................................................................................................................... 26
Edge Alignment ......................................................................................................................................................................... 27
Frame Timing ............................................................................................................................................................................ 28
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TABLE OF FIGURES
Figure 1: Block Diagram ................................................................................................................................................................. 7
Figure 2: Output Architecture (Left or Right) ............................................................................................................................... 10
Figure 3: Recommended Output Structure Load Diagram ......................................................................................................... 11
Figure 4: Pinout Diagram ............................................................................................................................................................. 12
Figure 5: Typical Quantum Efficiency, Color version ................................................................................................................... 17
Figure 6: Typical Quantum Efficiency, all Monochrome versions ............................................................................................... 17
Figure 7: Typical Angular Response, Color version .................................................................................................................... 18
Figure 8: Typical Angular Response, Monochrome with microlens ........................................................................................... 18
Figure 9: Equivalent Circuit Model ............................................................................................................................................... 24
Figure 10: H1 and H2 Edge Alignment ......................................................................................................................................... 27
Figure 11: H1L and H2 Edge Alignment ....................................................................................................................................... 27
Figure 12: Frame Timing (minimum) ........................................................................................................................................... 28
Figure 13: Frame Timing Edge Alignment ................................................................................................................................... 28
Figure 14: Line Timing .................................................................................................................................................................. 29
Figure 15: Pixel Timing ................................................................................................................................................................. 30
Figure 16: Pixel Timing Detail ...................................................................................................................................................... 31
Figure 17: Power-up Flush Cycle ................................................................................................................................................. 32
Figure 18: Completed Assembly (1 of 2) ...................................................................................................................................... 36
Figure 19: Completed Assembly (2 of 2) ...................................................................................................................................... 37
Figure 20: Clear Cover Glass Transmission, Typical ................................................................................................................... 38
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SUMMARY SPECIFICATION
KODAK KAF-8300 IMAGE SENSOR
3326 (H) X 2504 (V) FULL FRAME CCD IMAGE SENSOR
DESCRIPTION
The KODAK KAF-8300 Image Sensor is a 22.5mm
diagonal (Four Thirds Format) high performance color or
monochrome full frame CCD (charge-coupled device)
image sensor designed for a wide range of image
sensing applications including digital imaging. Each pixel
contains blooming protection by means of a lateral
overflow drain thereby preventing image corruption
during high light level conditions. For the color version,
each of the 5.4m square pixels are patterned with an
RGB mosaic color filter with overlying microlenses for
improved color response and reproduction. Several
versions of monochrome devices are available with or
without microlenses.
FEATURES
High Resolution
APPLICATIONS
Photography
Industrial Imaging
Medical Imaging
Parameter
Typical Value
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Aspect Ratio
Horizontal Outputs
Saturation Signal
Output Sensitivity
Quantum Efficiency, color
33%, 40 %, 33%
R(600nm), G(540nm), B(480nm)
Quantum Efficiency, monochrome
Microlens, clear glass (540nm)
54%
Microlens, no glass (540nm)
60%
Microlens, AR glass (540nm)
56%
No Microlens, clear glass (560nm) 37%
Total Sensor Noise
16 eDark Signal
< 200 e-/s
Dark Current Doubling
5.8 C
Temperature
Linear Dynamic Range
64.4 dB
Linearity Error at 12C
+/- 10%
Charge Transfer Efficiency
0.999995
Blooming Protection
1000x saturation exposure
(1ms integration time)
Maximum Data Rate
28 MHz
Package
32-pin CERDIP, 0.070 pin spacing
Cover Glass
Clear or AR coated, 2sides
Parameters above are specified at T = 60 C and a data rate of 28 MHz
unless otherwise noted
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ORDERING INFORMATION
Catalog
Number
Product Name
4H0827
KAF- 8300-AAB-CB-AA
4H0828
KAF- 8300-AAB-CB-AE
4H0927
KAF- 8300-AXC-CB-AA
4H0928
KAF- 8300-AXC-CB-AE
4H0929
KAF- 8300-AXC-CP-AA
4H0930
4H0944
KAF- 8300-AXC-CD-AA
4H0945
4H0469
KAF- 8300-CXB-CB-AA-Offset
4H0468
KAF- 8300-CXB-CB-AE-Offset
4H0471
KEK-4H0471-KAF- 8300-12-28
Description
Marking
Code
KAF-8300XE
[Serial Number]
KAF-8300-AXC
[Serial Number]
KAF-8300-AXC
[Serial Number]
KAF-8300-AXC
[Serial Number]
KAF-8300CE
[Serial Number]
N/A
Please see ISS Application Note Product Naming Convention (MTD/PS-0892) for a full description of naming convention
used for KODAK image sensors.
For all reference documentation, please visit our Web Site at www.kodak.com/go/imagers.
Address all inquiries and purchase orders to:
Image Sensor Solutions
Eastman Kodak Company
Rochester, New York 14650-2010
Phone: (585) 722-4385
Fax:
(585) 477-4947
E-mail: imagers@kodak.com
Kodak reserves the right to change any information contained herein without notice. All information furnished by Kodak is
believed to be accurate.
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DEVICE DESCRIPTION
ARCHITECTURE
GBr
GRr
GRr
GRr
KAF-8300CE
Active Image Area
Effective Image Area
V2
248 pixels
1162 pixels
H1L
RD
LODT
LODB
16 Active Buffer
4 Blue Pixel Buffer
8 Dark Dummy
12 Dark
6 Dark Dummy
RG
Last Hccd Phase: H1
VDD
VOUT
VSS
16 Active Buffer
4 Blue Pixel Buffer
5 Dark Dummy
5 Dummy
1 Active (CTE Monitor)
8 Dummy
SUB
OG
1163 pixels
GRr
8 Dark Dummy
39 Dark
6 Dark Dummy
H1
H2
16 Active Buffer
4 Blue Pixel Buffer
3 Dummy
1 Active (CTE Monitor)
2 Dummy
(showing the color filter pattern. Monochrome version will not have any color pattern.)
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IMAGE ACQUISITION
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the device. These photoninduced electrons are collected locally by the formation
of potential wells at each photogate or pixel site. The
number of electrons collected is linearly dependent on
light level and exposure time and non-linearly dependent
on wavelength. When the pixel's capacity is reached,
excess electrons are discharged into the lateral overflow
drain to prevent crosstalk or blooming. During the
integration period, the V1 and V2 register clocks are held
at a constant (low) level.
CHARGE TRANSPORT
The integrated charge from each photogate is
transported to the output using a two-step process.
Each line (row) of charge is first transported from the
vertical CCDs to a horizontal CCD register using the V1
and V2 register clocks. The horizontal CCD is presented
a new line on the falling edge of V2 while H1 is held high.
The horizontal CCDs then transport each line, pixel by
pixel, to the output structure by alternately clocking the
H1 and H2 pins in a complementary fashion. A separate
connection to the last H1 phase (H1L) is provided to
improve the transfer speed of charge to the floating
diffusion. On each falling edge of H1 a new charge packet
is dumped onto a floating diffusion and sensed by the
output amplifier.
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HORIZONTAL REGISTER
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
H1L
OG
RG
RD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
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Output Load
VDD = +15V
Iout = 5.4mA
0.1uF
VOUT
2N3904
or Equiv.
130 Ohms
680 Ohms
Buffered
Video
Output
Component values may be revised based on operating conditions and other design considerations.
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PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Pin 1 Indicator
SUB 1
OG
RG
RD
RD
VSS
VOUT
VDD
SUB
H1L
N/C
SUB
H1
H1
H2
H2
16
32
N/C
LODT
V1
V1
V2
V2
SUB
N/C
V2
V2
V1
V1
SUB
N/C
N/C
17 LODB
Pin
Name
Description
Pin
Name
Description
SUB
Substrate
32
N/C
No Connection
OG
Output Gate
31
LODT
RG
Reset Gate
30
V1
Vertical Phase 1
RD
29
V1
Vertical Phase 1
RD
28
V2
Vertical Phase 2
VSS
27
V2
Vertical Phase 2
VOUT
Output
26
SUB
Substrate
VDD
25
N/C
No Connection
SUB
Substrate
24
V2
Vertical Phase 2
10
H1L
23
V2
Vertical Phase 2
11
N/C
No Connection
22
V1
Vertical Phase 1
12
SUB
Substrate
21
V1
Vertical Phase 1
13
H1
Horizontal Phase 1
20
SUB
Substrate
14
H1
Horizontal Phase 1
19
N/C
No Connection
15
H2
Horizontal Phase 2
18
N/C
No Connection
16
H2
Horizontal Phase 2
17
LODB
Note: Wherever possible, all N/C pins (11, 18, 19, 25, 32) should be connected to GND (0V).
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IMAGING PERFORMANCE
TYPICAL OPERATIONAL CONDITIONS
Description
370.36 msec
33 msec
28 MHz
Red, green, blue, orange
Flush integrate readout cycle
Notes
Includes tVoverclock & tHoverclock
SPECIFICATIONS
Monochrome and Color Versions
Description
Symbol
Minimum Column
MinColumn
Ne-sat
Q-V
22.5
Linearity Error
LeLow10
LeLow33
LeHigh
-10
-10
-10
Min.
Notes
Verification Plan
575
Nom.
Max
Units
mV
die18
25.5K
e-
1,3
design19
V/e-
23
2,5,6
2,5,6
2,5
die18
die18
die18
e-/s
die18
200
e-/s
die18
15
mV/s
die18
die18
10
10
10
%
%
%
AA_DarkSig
200
DR_DarkSig
Dark_Read
Dark_Flush
43
90
mV/s
DSNU
DSNU_Step
DSNU_H
1.30
0.14
0.4
3
0.5
1.0
mVp-p
mV pp
mVp-p
5.8
DarkStep
-3.5
0.15
Dfld_noi
design19
9
9
9
die18
die18
die18
design19
3.5
mV
die18
1.08
mV
10
die18
16
e- rms
19
design19
DR
64.4
dB
11
design19
13, 21
die18
21
die18
x Esat
14
design19
HCTE
0.999990
0.999995
VCTE
0.99997
0.999999
X_b
1000
VBloomF
-20
20
mV
die18
Horizontal Crosstalk
H_Xtalk
-20
20
mV
die18
Hoclk_noi
1.08
mV
die18
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Symbol
Max
Units
f-3dB
Min.
88
159
Mhz
ROUT
100
180
Ohms
Hclk Feedthru
Vhft
70
mV
Reset Feedthru
Vrft
710
1000
mV
Nom.
Max
Units
420
638
420
mV
mV
mV
die18
die18
die18
design19
630
130
260
430
120
45
420
40
120
mV
mV
mV
mV
mV
mV
mV
mV
mV
die18
die18
die18
die18
die18
die18
die18
die18
die18
14
8
15
15
15
2
2
2
2
%
%
%p-p
%p-p
%p-p
%rms
%rms
%rms
%rms
2, 6
2, 6
7
7
7
die18
die18
die18
die18
die18
die18
die18
die18
die18
500
Nom.
Notes
Verification Plan
6,16
die18
die18
17
die18
design19
Symbol
Min.
Notes
Verification Plan
Sensitivity
red,
green,
blue
Rresp
Gresp
Bresp
260
442
230
QE
R(600nm)
G(540nm)
B(480nm)
Off-band Response
Green inband,
Red response
Blue response
Red inband,
Green response
Blue response
Blue inband,
Red response
Green response
Linearity Balance
Photo Response NonUniformity
High Frequency Noise
QE, red
QE green
QE, blue
33
40
33
Gr_Gresp
Gr_Rresp
Gr_Bresp
Rd_Rresp
Rd_Gresp
Rd_Bresp
Bl_Bresp
Bl_Rresp
Bl_Gresp
362
0
0
180
0
0
90
0
0
Red_Bal
Blu_Bal
R_PRNU
G_PRNU
B_PRNU
R_Nois
GRr_Nois
GBr_Nois
B_Nois
-14
-8
6.4
0.2
RGHueUnif
10
12
die18
BGHueUnif
12
12
die18
GrGbHueUnf
12
die18
Gr_GHueUnf
die18
RGLoHueUnf
BGLoHueUnf
GrnStreak
RedStreak
BluStreak
12
10
40
20
20
%
%
%
%
%
die18
die18
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Symbol
Min.
Nom.
Max
Units
4
6
4
4
65
65
40
40
%
%
%
%
%
%
%
%
die18
die18
die18
die18
die18
die18
die18
die18
7
7
7
7
%
%
%
%
die18
die18
die18
die18
6
6
6
6
6
6
%
%
%
%
%
%
die18
die18
die18
die18
die18
die18
Max
Units
655
mV
die18
design19
W_GNU_Min
W_GNU_Max
Gr_GNU_Min
Gr_GNU_Max
R_GNU_Min
R_GNU_Max
B_GNU_Min
B_GNU_Max
UL_Chroma
UR_Chroma
LL_Chroma
LR_Chroma
UL_UR_Hue
UL_LR_Hue
UL_LL_Hue
UR_LR_Hue
UR_LL_Hue
LR_LL_Hue
Hue Test
Notes
Verification Plan
Symbol
Sensitivity
Monochrome
Resp
Min.
Nom.
465
Notes
Verification Plan
QE
Microlens, clear glass (540nm)
Microlens, no glass (540nm)
Microlens, AR glass (540nm)
No Microlens, clear glass (560nm)
QE
54%
60%
56%
37%
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Notes:
13.
14.
15.
16.
17.
18.
19.
20.
21.
Process
optimization
has
eliminated vertical striations.
22.
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1.
2.
3.
4.
5.
6.
Tested at T=25C.
7.
8.
9.
10.
11.
20log(Vsat/N)
12.
effectively
GRr
GBr
35%
Absolute QE
30%
25%
20%
15%
10%
5%
0%
350
450
550
650
750
850
950
1050
1150
Wavelength (nm)
microlens, No Glass
Absolute QE
50%
40%
30%
20%
10%
0%
350
450
550
650
750
850
950
1050
1150
Wavelength (nm)
Figure 6: Typical Quantum Efficiency, all Monochrome versions
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Normalized Response
0.9
0.8
0.7
0.6
0.5
0.4
0.3
Horizontal - White Light
0.2
0.1
0.0
-25
-20
-15
-10
-5
10
15
20
25
Angle
Figure 7: Typical Angular Response, Color version
(Center location of die as shown. Effective optical shift is 6 center-to-edge, along diagonal.)
KAF-8300 Vertical Angle Response - Green Light
Normalized Response
1
0.8
0.6
0.4
Top
Center
0.2
Bottom
0
-30
-25
-20
-15
-10
-5
10
15
20
25
30
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DEFECT DEFINITIONS
OPERATIONAL CONDITIONS
The Defect Specifications are measured using the following conditions:
Description
Test Condition
Notes
33 msec
SPECIFICATIONS
Monochrome and Color Versions
Description
Symbol
Definition
Threshold
Point defect
Point defect
Point defect
Point defect
Point defect
Point defect
Point Defect
Cluster defect
BPnt33_7
Bfld_Pnt_D
Bfld_Pnt_B
BPnt33_100
BPnt33_500
BPnt333_13
DR_BPnts
Total_Clst
Cluster defect
Dfld_Vperp
Cluster Defect
Perpendicular Pattern
Defect
Column defect,
illuminated
Dfld_Perp
Bfld_Perp
Total_Perp
Bfld_Col_D
Bfld_Col_B
Row Defect
Streak Test, dark
Dfld_Col2
Dfld_Col4
Lo_Col_B
Lo_Col_D
Lo_Col_B1
Lo_Col_D1
Dfld_Row
DarkStreak
Dfld_LodCol
Symbol
Definition
7.5 mV
11%
7%
100 mV
500 mV
13 mV
7.5 mV
--3.04 mV
Maximum
Number Allowed
800 total
Points allowed for
this group of tests
0
32,5001
0
6 total
0
--0
1.5%
1.5%
1 mV
1 mV
1 mV
1 mV
1 mV
1 mV
1 mV
40%
0
0
1.5 mV
Threshold
Maximum
Number Allowed
GrnStreak
RedStreak
BluStreak
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40%
20%
20%
Notes:
1.
This parameter is only a quality metric and these points will not be considered for cluster and point criteria.
2.
For the color version of this device, the green pixels in a red row (GR) are considered a different color plane than
the green pixels in a blue row (GB). For monochrome version the entire active area is treated as a single color
plane.
3.
4.
As the gradient threshold is defined as 8.5 mV maximum across a 16 x 16 pixel region about each pixel. 5. As the
gradient threshold is defined as 6 mV maximum across a 50 x 50 pixel region about each pixel.
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OPERATION
ABSOLUTE MAXIMUM RATINGS
Description9
Symbol
Vdiode
Vgate1
V1-2
Vg-g
VVVL
Iout
VLODT
VLODB
TOP
TSP
Minimum
Maximum
Units
-17.5
-13.5
-13.5
-13.5
-13.5
+17.5
+13.5
+13.5
+13.5
+13.5
-30
+13.0
+18.0
70
60
V
V
V
V
V
mA
V
V
oC
C
-13.0
-18.0
-10
0
Notes
1,2
1,3
4
5
6
7
8
8
10
11
Notes:
1.
2.
3.
4.
5.
6.
7.
POWER-UP SEQUENCE
The sequence chosen to perform an initial power-up is not critical for device reliability. A coordinated sequence may
minimize noise and the following sequence is recommended:
1.
2.
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Symbol
Reset Drain
Output Amplifier Return
Maximum
DC Current
(mA)
Minimum
Nominal
Maximum
Units
RD
11.3
11.5
11.7
IRD = 0.01
VSS
1.05
1.25
1.45
ISS = -3.0
VDD
14.5
15.0
15.5
IOUT + ISS
Substrate
SUB
-0.01
Output Gate
OG
-3
-2.8
-2.6
0.1
Lateral Drain
LODT, LODB
9.5
9.75
10.0
0.2
IOUT
-3
-5
-8
mA
GND
Notes
2
1
Notes:
1.
2.
An output load sink must be applied to VOUT to activate output amplifier see Figure 3.
Maximum current expected up to saturation exposure (Esat).
AC OPERATING CONDITIONS
Clock Levels
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Effective
Capacitance
-9.5
-9.25
-9.0
76 nF
V1 Low Level
V1L
Low
V1 High Level
V1H
High
2.4
2.6
2.85
V2 Low Level
V2L
Low
-9.5
-9.25
-9.0
V2 High Level
V2H
High
2.4
2.6
2.8
RGamp
H1amp
H2amp
Amp
5.5
6.0
6.5
H1Lamp,
Amp
7.5
8.0
Notes
1
1
81 nF
1
1
RG = 7 pF
H1 = 224 pF
H2 = 168 pF
8.5
7 pF
H1 Low Level
H1low,
Low
-4.7
-4.5
-4.3
H1Llow
Low
-6.7
-6.5
-6.3
H2 Low Level
H2low
Low
-5.2
-5
-4.8
RG Low Level
RG low
Low
1.8
2.0
2.2
Note:
1.
All pins draw less than 10mA DC current. Capacitance values relative to SUB (substrate).
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Symbol
V1 High-level variation
V2 High-level variation
V2 Low-level variation
V1 Low-level variation
V1-V2 Cross-over
H1 High-level variation
H1 High-level variation
H1 Low-level variation
H1 Low-level variation
H2 High-level variation
H2 High-level variation
H2 Low-level variation
H2 Low-level variation
H1 H2 Cross-over
H1 H2 Cross-over
H1L High-level variation
H1L High-level variation
H1Llow-level variation
H1Llow-level variation
H1L H2 Cross-over
RG High-level variation
RG High-level variation
RG Low-level variation
RG Low-level variation
V1HH
V2HL
V2LH
V1LL
V1CR
H1HH
H1HL
H1LH
H1LL
H2HH
H2HL
H2LH
H2LL
H1CR1
H1CR2
H1LHH
H1LHL
H1LLH
H1LLL
H1LCR1
RGHH
RGHL
RGLH
RGLL
Min
Nom
Max
Units
-2
-3
-3
-1
-
0.50
0.28
0.46
0.14
-0.5
0.30
0.07
0.16
0.25
0.40
0.06
0.10
0.27
-1.23
-0.59
0.64
0.32
0.27
0.23
0.19
0.20
0.11
0.30
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
-3
1
1
1
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Notes
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Referenced to ground
Rising side of H1
Falling side of H1
Notes:
1.
H1, H2 clock frequency: 28MHz. The maximum and minimum values in this table are supplied for reference.
The actual clock levels were measured using the KAF-8300CE Evaluation Board. Testing against the device
performance specifications is performed using the nominal values.
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Value
Parameter
CV1
CV12
CV2
CH1
CH12
CH2
CH1L
RH1LH1
(typical)
Units
61
15
nF
nF
67
nF
153
pF
36
pF
97
pF
pF
52
Kohms
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TIMING
REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
RG VOUT Delay
Readout Time
Integration Time
Line Time
Flush Time
Minimum
Nominal
Maximum
Units
Notes
28
MHz
1, 2
125
kHz
35.7
ns
e
HS
HV
ns
RV
ns
340.2
ms
line
132.2
ms
flush
21.23
ms
readout
4, 5
3, 4
int
Notes:
1.
2.
3.
4.
5.
6.
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Symbol
tV1r
tV2r
tV1f
tV2f
tV1w
tV2w
tH1r
tH2r
tH1f
tH2f
tH1w, tH2w
tH1Lr
tH1Lf
tH1Lw
tRGr
tRGf
tRGw
Min
Nom
Max
Units
5.0
3.0
14
0.26
0.55
0.43
0.31
9.0
6.9
5.8
5.4
18
1.8
2.5
19.0
2.0
2.2
6.7
1
1
1
1
10
10
10
10
22
4
4
22
4
4
-
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
-
Notes
3
3
3
3
4, 5
4, 5
3
3
3
3
3
3
3
3
2
Notes:
1.
2.
3.
4.
5.
H1, H2 clock frequency: 28MHz. The maximum and minimum values in this table are supplied for reference. The
actual clock timing was measured using the KAF-8300CE Evaluation Board. Testing against the device
performance specifications is performed using the nominal values.
RG should be clocked continuously.
Relative to the pulse width (based on 50% of high/low levels).
CTE
Longer times will degrade noise performance.
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EDGE ALIGNMENT
t H2w
t H1w
H1HH
H2HH
H1HL
H1
H2HL
H2
100%
100%
90%
90%
H2
H2
H1CR2
H1CR1
50%
50%
H1
H1
10%
0%
10%
0%
H1LH
H1LL
t H1r
t H1f
H2LH
H2LL
tt H2r
tH2f
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FRAME TIMING
t readout
t int
V1
Line
2573
2574
V2
H2
H1, H1L
V1HH
tV1w
tV2w
100%
90%
V2HL
V1
V2
V1CR
(referenced to ground)
50%
10%
0%
tr
V2LH
V1LL
tf
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te
tHS
5
4
14
13
12
11
Quantity in grouping:
RG
H2
H1, H1L
V2
V1
t line
3398
3397
3396
3395
(39) Dark Pixels
3391
3390
3389
(8) Dark Dummy Pixels
3386
3385
(4) Blue Pixel Buffer
3370
3369
3368
3367
3366
3365
(16) Active Buffer Pixels
47
46
45
44
43
(3326) Active Pixels
28
27
(16) Active Buffer Pixels
24
23
22
(4) Blue Pixel Buffer
19
18
(5) Dark Dummy Pixels
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(6) Dark Dummy Pixels
For lines 1 thru 1163 are as shown above with the following exception:
For lines 1412 thru 2570 are as shown above with the following exception: pixel 13 are denoted as a dark
*** Lines 1 - 6, 19-26, and 2571 - 2574 are lines mostly composed of dark dummy pixels
and are not to be used for imaging purposes or as a dark reference.
** Lines 31 - 46 and 2555 - 2570 are lines mostly composed of photoactive buffer pixels.
test
3438
3437
3436
**** Lines 27 - 30 and 2551 - 2554 are lines mostly composed of blue photoactive buffer pixels.
3448
3447
3446
3445
3444
3443
3442
3441
LINE TIMING
Schematic reference regions that contain a blue filter represent the color version only; monochrome version is uncoated
for these pixels.
PIXEL TIMING
1
count
te
tRGw
RG
RGamp
RGlow
H1
H1amp
H1low
H2
H2amp
H2low
H1L
H1Lamp
H1Llow
tRV
tHV
VOUT
Vrft
Vdark+Vhft
Vodc
Vsat
GND
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RGHH
100%
90%
RG
50%
10%
0%
t RGr
t RGf
RG LH
RGLL
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MODE OF OPERATION
POWER-UP FLUSH CYCLE
t int
t Vflush
t readout
V2
2574+64 (min)
V1
H
2
te
3448 (min)
H1,H1L
Figure 17: Power-up Flush Cycle
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ESD
1.
2.
Description
Symbol
Minimum
Maximum
Units
Storage
Temperature
TST
-20
80
Notes
1
Humidity
RH
90
Notes:
1.
2.
Condition
1 to 5 years
20C to 40C
< 60%
SOLDERING RECOMMENDATIONS
Soldering procedure is defined as a partial heating
method as follows:
a.
b.
c.
d.
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ENVIRONMENTAL EXPOSURE
1.
1.
2.
2.
3.
4.
5.
6.
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MECHANICAL INFORMATION
VISUAL MECHANICAL SPECIFICATIONS
Laser Mark
Item
Description
Device Name
Lot Number,
(If applicable)
Serial
Number
All markings shall be readable, consistent in size with no unusual debris left on the package.
Assembly/Package Integrity
Criteria
Description
Cracks
Corner and edge
chip-outs
Chip-outs exposing
buried metal
traces
Chip-outs, other
Scratches
None allowed
None exceeding 0.020 (0.50mm)
Lead conditions
Internal
Appearance
AndDie Condition
None allowed
None allowed deeper than 50% of the ceramic layer thickness in which it resides
None that exceed 0.20 (0.50mm) in the major dimension and are deeper than 50% of the ceramic layer thickness in which it
resides.
No bent, missing, damaged, or short leads. No lead cut-off burrs exceeding 0.005 (0.13mm) in the dimension away from the lead.
Local Non-UniformityLocal Non-Uniformity region (LNU) is allowed whose size is not greater than 200 um2 within the effective
image area. Inspection equipment for these steps are performed using a microscope 7-50X and direct lighting (ring-light). LNU is
described as a spot or streak that tends to change from light to dark in appearance as the operator rotates the part under angled
lighting conditions. These non-uniformities are not visible or very hard to see under direct lighting. They tend to disappear or
become much less visible under higher magnification. Conditions Other than LNU:No scratches, digs, contamination, marks, or
blemishes that is attached to the die that touches 9 or more pixels in the effective image area. No loose contamination allowed
when viewed at 7X and 50X magnification. No scratches, digs, contamination, marks, or blemishes greater than 10um are allowed
on the bottom side of the cover glass region that is contained in or extends into the effective image area. Tools used to verify are 7X
and 50X magnification.
Glass
Criteria
Description
Tilt
The reject condition is when the glass is incorrectly seated on the package or is not parallel to glass seal area. (parallel is defined as
0.25mm maximum end to end).
Glass seal must be greater than 50% of the width of the epoxy bond line and must not extend over the ceramic package.
There are 4 + fiducials on the corners the die that must not be covered by the epoxy light shield. The 4 + marks must be in total view
when the lid is placed looking directly down on the device with a microscope. All 4 + alignment marks are required to be visible in
their entirety with a zero clearance tolerance.
None allowed.
No fogged cover allowed.
No immobile scratches, digs, contamination, marks, or blemishes are allowed on the cover glass region that is contained in or extends
into the effective image area. Within the effective image area, the limit for such conditions is 10um or less. This criterion pertains to
either the top or the bottom glass surface. Tools used to verify are 7X and 50X magnification.
Seal
Alignment
Chips
Appearance
Contamination
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COMPLETED ASSEMBLY
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COVER GLASS
Clear Cover Glass, AR Coated (both sides) - Specification
1.
2.
3.
Wavelength
Total Reflectance
420-450
450-630
630-680
2%
1%
2%
2.
Transmission (%)
1.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
300
350
400
450
500
550
600
650
700
750
800
850
900
Wavelength (nm )
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QUALITY STRATEGY
All image sensors will conform to the specifications
stated in this document. This will be accomplished
through a combination of statistical process control and
inspection at key points of the production process.
Typical specification limits are not guaranteed but
provided as a design target. For further information refer
to ISS Application Note MTD/PS-0292, Quality and
Reliability.
REPLACEMENT
RELIABILITY
Information concerning the quality assurance and
reliability testing procedures and results are available
from the Image Sensor Solutions and can be supplied
upon request.
MECHANICAL
Kodak reserves the right to change any information contained herein without notice. All information furnished by Kodak is
believed to be accurate.
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REVISION CHANGES
Revision Number
Description of Changes
1.0
Initial Release.
2.0
Add monochrome versions and the allowance of differentiating high volume packing.
3.0
Reference to Web Site noted on Ordering Information page. Added references to MTD/PS-1039 Image Sensor
Handling and Best Practices. Removed descriptions and drawings related to high level packing.
4.0
5.0
Changed Sample Plan to Verification Plan. Added new revision of completed assembly drawing
5.1
5.2
5.3
5.4
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Eastman Kodak Company, 2010. KODAK and TRUESENSE are trademarks of Eastman Kodak Company.