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Design Considerations for DSP-Controlled 400 Hz Shunt Active Power Filter in an Aircraft Power System
Haibing Hu, Member, IEEE, Wei Shi, Ying Lu, and Yan Xing, Member, IEEE
AbstractA multiresolution control strategy is proposed for a digital signal processor (DSP)-controlled 400 Hz active power lter (APF) to reduce the real-time computational requirements. By rearranging the computational elements into high- and lowfrequency control groups, the proposed control strategy takes best advantages of the DSP computation resources to increase the control frequency for the high computational group, which mainly determines the APF performance. Based on bandwidth features of different control plants in APF, detailed analysis is given to determine the control and sampling frequencies for these plants. Anti-aliasing lters are designed to avoid aliasing when downsampling scheme is used to further reduce computation resource. A 20 kVA prototype is set up to verify the validity of the proposed strategy and analysis. Experimental results show that the proposed control strategy meets the computational requirements for the control system using a DSP. The proposed control strategy achieves the total harmonic distortion as low as 5.7%, which meets the avionic DO-160F standard, and also exhibits good dynamic performance. Index TermsActive power lter (APF), aircraft power systems, digital signal processor (DSP), multiresolution.

I. I NTRODUCTION N TODAYs aircraft industry, the concepts of all-electric aircraft and more electric aircraft have been introduced to achieve better efciency, lower cost, and better performance [1][8]. As a result, the number of electrical loads equipped onboard is increasing, and the onboard power capacity is getting larger. Unfortunately, most of the dc loads in airborne systems are typically powered by the uncontrolled diode rectier converters due to their high reliability, relatively high efciency, and low cost, which in turn generate large amount of harmonic currents and poor power factor. The high harmonic current distortion and poor power factor would be a major concern when the percentage of total system power processed by uncontrolled rectiers is high. To address this problem, some standards such as DO-160F and ISO-1540 have been revised to keep strict limits on harmonic currents which user equipment can draw

Fig. 1. Potential solutions. (a) Multiphase transformer rectier. (b) Active power lter. (c) PWM rectier.

Manuscript received August 1, 2010; revised March 23, 2011 and May 30, 2011; accepted July 21, 2011. Date of publication August 18, 2011; date of current version April 13, 2012. The authors are with the College of Automation, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: huhaibing@ 163.com; huhaibingucf@gmail.com; luying@nuaa.edu.cn; xingyan@nuaa. edu.cn). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIE.2011.2165452

from the ac source [9]. The potential solutions to this power quality problem are to employ some techniques such as power factor correction, multiphase (12- or 18-pulse) transformerrectier, and active power lter (APF) [6], [7], [10][19] as shown in Fig. 1. Reference [6] has made detailed comparisons between PWM rectier and 12-pulse auto-transformer based on power density, losses, cost, and reliability. However, these two techniques have to deal with all the power ow supplied to the load, resulting in high volume and heavy weight. APF compensates only the harmonics for the load and thus much lower capacity and lighter weight can be achieved in comparison to the above two techniques. Furthermore, the other benet of the APF is that it does not change the existing power stage and degrade the reliability of the old ones as it can be switched off the grid when faults in APF occur. Extensive research has been conducted on APFs applied to the 50 Hz or 60 Hz commercial power systems [20][26]. Although the principle for APF applied to the commercial utility and to the aircraft power system is the same, there exists a great challenging in designing high performance 400 Hz APF

0278-0046/$26.00 2011 IEEE



Fig. 2.

Structure of APF.

due to its wider bandwidth and limited switching frequency. There have been few publications on 400 Hz APFs applied to the aircraft power systems [10][17]. In [10], analysis and simulation were given to illustrate the harmonic cancellation using APF, and a hysteresis current controller was used to fast track the current reference; however, the paper did not give any information about highest switching frequency and any control delay issues, which are the main issues for 400 Hz APFs performance. In [11], [12], a multilevel APF was proposed to reduce the switching frequency, which may lead to low reliability due to the complicated control and power stage. In [13], a unied power quality conditioner was applied to the 400 Hz single-phase microgrid based on modied PQ theory. In [14], [15], the detailed design procedures including control issues and key power stage parameters were given. Many researches have been conducted on fully digitalcontrolled APF for 50 Hz or 60 Hz applications [23][25]. However, fully digital-controlled APF for 400 Hz applications has never been applied before according to reported literatures as the control delay in a digital controller may lead to the great degradation of harmonics cancellation performance. To address this problem, a multiresolution control strategy is presented in this paper to achieve the high current control bandwidth with limited computation resources in DSP. High-frequency control group and low-frequency control group are partitioned based on their individual control plant bandwidth. Detailed analysis is given to determine the control and the sampling frequencies for different plants in APF. The paper is organized as follows. The principle of the 400 Hz shunt APF is given in Section II. Section III deals with the control delay effects on the current loop performance. A multiresolution control strategy is proposed to reduce the control delay in Section IV. Determining the sampling and control frequency for the lowfrequency control group is analyzed in Section V. Simulation results are presented in Section VI. Experimental results are given in Section VII with conclusions drawn in Section VIII.

II. P RINCIPLE OF S HUNT APF As seen in Fig. 2, the control system consists of four main functional blocks: 1) software phase-locked loop (PLL); 2) dc bus voltage regulator; 3) low-pass lter (LPF); and 4) current control loop. The measured load phase currents (iLa , iLb ) are transformed into the synchronous reference frame to obtain iLq and iLd . The synchronous reference frame phase angle can be obtained by processing the measured system voltages with software PLL algorithm. LPFs are employed to lter out the dc components in the synchronous reference frame, which represents the fundamental frequency components of the load currents. The harmonic components, (Lq , Ld ), are easily i i obtained by a simple subtraction of the ltered components (Lq , Ld ) and the transformed components (iLq , iLd ). Due to i i losses in power devices and other components, a small amount of real power is consumed, which would result in dc voltage decrease. To keep the dc voltage constant, dc voltage regulator is used by adding dc regulating value id to the d-axis lter current. All these computations are implemented in a digital signal processor (DSP). III. E FFECT OF C ONTROL D ELAY ON C URRENT L OOP In a balanced three-phase system, the inverter model in the synchronous reference frame can be described as L did R L dt diq = L R L dt C [ ed [ id [ ud eq iq uq dudc 3ed = id dt udc eo ]T = C32 [ ea io ]T = C32 [ ica uo ]T = C32 [ da eb icb db ec ] icc ] dc ]Udc id u e d + d iq uq eq (1a) (1b) (1c) (1d) (1e)




Fig. 3. Diagram of the current loop with pure delay time Td.

where L and R

are the equivalent inductance and resistance of the grid-tied inductor Lc ; C is the dc bus capacitance; is the angular frequency of the grid; are the corresponding currents in the synchro[id iq io ] nous reference frame; are the three-phase grid voltages; [ea eb ec ] are the voltages in the synchronous reference [ed eq eo ] frame; [ica icb icc ] are three-phase currents from APF; are control duty cycles of three phases; [da db dc ] is the dc bus voltage; Udc [ud uq uo ] are the voltages in synchronous reference frame. is the transformation matrix from the stationery C32 frame to the synchronous reference frame, which is given by sin t sin t 2 sin t 4 3 3 2 C32 = cos t cos t 2 cos t 4 . 3 3 3 3 3 3
2 2 2

Fig. 4.

Relationship between phase delay and delay time.

unit. In a delay system, the decrease in phase margin can be calculated by the pure delay time Td , which translates to a phase lag as: P haselag = Td = 2fc Td (4)

The inverter plant depicted in expression (1a) is a nonlinear and coupling system. With the feedforward and dc-coupling terms, the transfer functions of the current loop being controlled can be linearized as Gq_c = Gd_c (s) = 1 . R + Ls (2)

Due to the computational delay in digital control system, a pure control delay is unavoidably introduced to the system, which has a negative effect on the control bandwidth. The delay time Td depends on the current loop control strategy, whose transfer function can be expressed as Gdelay (s) = esTd . (3)

A P regulator, as shown in Fig. 3, is employed in the current loop control, where Kp and Kpwm are proportional coefcient in current loop and PWM gain of the three-phase inverter, respectively. The parameters of the APF are listed in Table I. The bandwidth of the current loop will decide the compensating effect of the APF. To achieve a better compensating effect, the current bandwidth should be designed as wide as possible within the region of system stability. For simplication, the controller was designed based on continuous linear system without introducing the pure delay unit. In this application case, the cutoff frequency fc of the current open loop is designed at 10 kHz, which is one-fth of the switching frequency 50 kHz, and the phase margin is designed at 90 to make sure the current loop has enough stability margin when introducing a pure delay

where, fc = 10 kHz is the cutoff frequency at which the phase lag can be calculated. Fig. 4 shows the relationship between delay time and phase margin decrease. It clearly shows that the current loop will fall in the unstable region when the delay time Td is greater than 25 us. As aforementioned, the delay time Td depends on the DSP computation time and the duty cycle updating scheme. Many multisampling methods have been proposed to reduce delay time in the digital controller for PWM converters [18]. However, all these methods are unavoidable to sample the switching ripples, resulting in a degradation of the expected dynamic response, and they also require more hardware resources and computational efforts. In this paper, two typical synchronous sampling methods, as shown in Fig. 5, were chosen to compare their effects on the harmonic compensation. Two schemes have Ts and Ts/2 delay time, respectively, where Ts is the switching period. The closed-current loop transfer function can be expressed as Gi_close = kp kpwm eTd s . R + Ls + kp kpwm eTd s (5)

According to the closed-loop transfer function, we can calculate the phase lag and amplitude for each harmonic as shown in Fig. 6. For an ideal closed-loop transfer function, the phase lag should be equal to 0 and the gain should be equal to unity within its control bandwidth. As seen in Fig. 6(a),




Fig. 5. Two synchronous sampling schemes and their delay time. (a) Scheme 1. (b) Scheme 2.

due to the current limited bandwidth (10 kHz), the phase lag increases as the harmonic order increases in all three cases (no delay, 10 us delay, and 20 us delay). Fig. 6(b) shows the gain changes as the harmonic order increases. The following should be noted. 1) In the 10 kHz bandwidth design, the phase lag performance of the case with no delay is better than that with 10 us delay; however, the gain performance of the case with 10 us delay is better than that of no delay. 2) Due to limited current bandwidth, the harmonic orders more than 15th will be impossible to achieve the good compensating effect; however, these high-order harmonics can be easily ltered out using small reactive lter installed at the source side. Based on above analysis, we choose synchronous sampling scheme 2 to implement the digital control. However, the computation amount in scheme 2 would be twice that in scheme 1, which results in high computation resources in DSP. In this paper, we adopted the multiresolution control strategy to reduce real-time computation requirements. IV. M ULTIRESOLUTION C ONTROL S TRATEGY In this paper, all the computations are executed in the DSP, TMS320F2812, whose maximal operating frequency is 150 MHz. The computational elements and their execution time are listed in Table II. As aforementioned in Section III, since the APF is designed to operate with 50 kHz switching frequency, the control frequency reaches up to 100 kHz when employing the synchronous sampling scheme 2. However, due to the computation limitation in the DSP, all these computational elements as seen in Table II, whose total execution time is 11.7 us, cannot be completed within a control period of 10 us. As well known, the bandwidth of the different plants decides their control frequencies. In the APF system, the bandwidth of the current loop is expected to be wide enough to achieve good current tracking performance, while the dc bus voltage with support of bulky capacitors can be well regulated even with slow control. The software PLL, which usually takes several fundamental cycles (400 Hz) to lock the phase, can be implemented in slow control. To address the computation limitation issue in the 400 Hz digital-controlled APF applications, the multiresolution control strategy partitions the APF

Fig. 6. Comparison of control effect with different delays. (a) Phase delay versus harmonic order. (b) Closed-current loop gain versus harmonics order.



Fig. 7. Diagram of control timing sequence for multiresolution strategy.

Fig. 8. Diagram of dc voltage control loop.

controller into high- and low-frequency control groups, respectively, based on their control bandwidth. The high-frequency control group, which executes twice in one switching period, has to complete its computations within a half switching cycle. The low-frequency control group, which executes once in n switching periods, is allocated to one switching period, during which the DSP completes all the computation elements for both groups. The timing sequence of the multiresolution control strategy is shown in Fig. 7. Computational elements, (3, 4, 6, 7, 8, and 9), in Table II, which are related to the current loop calculation, operate with 100 kHz control frequency, and have a total execution time of 6.56 us (less than 10 us). In this manner, the high-frequency group can reach up to 100 kHz control frequency, while other computational elements can be executed with much lower frequency. A problem arose when applying the multiresolution control strategy: How to determine the control and sampling frequencies for the low-frequency control group without the degradation of the APF system performance. V. D ETERMINATION OF S AMPLING AND C ONTROL F REQUENCY A. Control Frequency for DC Voltage Regulator DC bus voltage regulator is designed to maintain the dc capacitor voltage constant. During steady-state operations, the dc capacitor voltage will not vary much due to the fact that no real power is transferred across the APF. The only losses come from switching devices and other components. In this case, only a small amount of real power is needed to charge the dc capacitor. The dc voltage regulator could be designed to be a low cutoff frequency. The diagram of the dc voltage control loop is shown in Fig. 8, where Kvp and Kvi are the coefcients of PI controller and Gi_close is the closed-current loop transfer

Fig. 9.

Bode diagram of the open dc voltage loop.

function. In the proposed control strategy, one switching cycle delay (Ts) is supposed to be introduced in the voltage control loop. The bode diagram of the open dc voltage control loop without PI regulator is plotted as shown in Fig. 9. As seen from Fig. 9, the cutoff frequency of the dc voltage open loop is around 55 Hz, which will be fast enough to regulate the dc capacitor voltage when operating in steady state. In the steady state, a very low sampling frequency of the dc voltage could be applied to stabilize the dc voltage. However, during APF transient response, a great amount of real power will be transferred back and forth across the APF due to the fact that LPFs treat the transient currents caused by sudden load changes as harmonics, which are real power and will charge or discharge the dc capacitors, resulting in the great voltage uctuations across the dc capacitor. Fig. 10 shows the diagram of real power transfer during load step-down transient response. The output current drops rapidly when the load steps down. The d-axis current in the synchronous reference frame, which is fed to the LPF to lter out the dc components, will drop correspondingly. Since the LPFs are designated to extract the dc components from the load currents, the bandwidth of LPFs is designed to be low (in the next subsection, a detailed design for the bandwidth of LPFs will be given). Therefore, the transient currents will be ltered out and be treated as harmonics. Real power is needed to compensate these harmonics, and the dc capacitor will be charged or discharged during this real power



Fig. 12. Downsampling structure for LPFs.

B. Low-Pass Filter A LPF with a bandwidth of 300 Hz is designed to remove the harmonic components, whose s-domain transfer function is expressed as
Fig. 10. Real power transfer during load step down.

H(s) =

2189299295 . s3 + 1390.7s2 + 3631900s + 2189299295


Fig. 11. Bode diagram of open loop with PI controller.

transfer. If the bandwidth of the dc voltage loop is designed too low, the disturbance from load changes cannot be restrained to a low level, resulting in high voltage uctuations across the dc capacitor, and thus a higher voltage stress on switches and the dc capacitor. To lower the voltage uctuations, a higher bandwidth is desired to better track the disturbance. On the other hand, during the steady-state operation, the harmonics compensation will cause the dc voltage ripples. In this case, the bandwidth of the voltage loop should be less than the frequency of the dc voltage ripples; otherwise, the compensating performance could become worse as the harmonic currents will be offset by the currents charging or discharging to the dc bus capacitor. In a balanced three-phase system, the lowest harmonic order is fth, which causes 2 kHz frequency dc bus voltage ripples, while the bandwidth of the LPFs (explained in the next part) is designed at 300 Hz. Therefore, the bandwidth for the voltage loop is supposed to be somewhere between 300 Hz and 2000 Hz. In this design, we made a tradeoff decision on the bandwidth of the voltage loop as the wider bandwidth needs high sampling and control frequency. A 600 Hz bandwidth is selected for the voltage loop as shown in Fig. 11. The attenuation at 5 kHz is 50 dB, which will keep anti-aliasing effect to be a neglectable level. Therefore, the 10 kHz sampling and control frequency will be enough in accordance with the Shannon sampling theorem.

To achieve good compensating performance, load currents (iLa iLb ) are sampled at a frequency of 100 kHz, which in the conventional implementation will be transformed into the corresponding currents (iLd iLq ) in the synchronous reference frame and then be fed to the LPFs. In this case, LPF would require a signicant amount of computation resources, as seen in Table II. As known, a LPF with a cutoff frequency of 300 Hz can use a much lower sampling frequency, which will greatly reduce its computation efforts. Since the load currents contain high-order harmonics, to avoid the aliasing effect when downsampling at a low frequency, a digital anti-aliasing lter has to be inserted to lter out the high-order harmonics to satisfy the Shannon sampling theorem. The structure of extraction of the current fundamental component is modied as shown in Fig. 12, where fk1 is 100 kHz and fk2 will be determined later. The anti-aliasing lter operating at 100 kHz is designed to lter out the high-order harmonics. To reduce computational efforts of the anti-aliasing lter, the coefcients of the lter are deliberately designed for easy implementation in DSP. The difference equation of the anti-aliasing lter is expressed as y(n) = x(n) y(n 1) + y(n 1). 25 (7)

The cutoff frequency of the digital anti-aliasing lter is around 1 kHz, beyond which the signals will be attenuated. In the three-phase system, the typical harmonic components are (6n 1) orders. After C32 transformation, the harmonic components will be transformed into [(6n 1) 1], which means the 13th-order harmonic will be changed to 12th order after transformation. The 12th-order harmonic (4.8 kHz) will be attenuated around 20 dB through the anti-aliasing lter. According to the Shannon sampling theorem, if the downsampling frequency for the LPFs is set to 9.6 kHz (twice the frequency of the 12th harmonic order), the high-order harmonics above 12th order will have little aliasing effect on the LPFs due to a great attenuation of these high-order harmonics by the digital anti-aliasing lter. C. Phase-Locked Loop Fig. 13 shows the block diagram of three-phase PLL system. The phase tracking performance would be improved by designing a controller with a wide bandwidth. However, the



Fig. 13. Block diagram of the three-phase PLL system. Fig. 16. Voltage phase angle calculation within a PLL control cycle. TABLE III S UMMARY OF S AMPLING F REQUENCIES

Fig. 14. Structure of a two-order band pass lter. TABLE IV C ONTROL F REQUENCIES

D. Sampling and Control Frequencies

Fig. 15. Multisampling control strategy for PLL.

use of higher bandwidth does not provide better results in this application, due to limited power capacity and relatively high output impedance in the 400 Hz power system, which cause the distorted voltages when connected by nonlinear loads. In the 400 Hz power system, the fundamental frequency is xed at 400 Hz with small variation. To reduce sampling frequency of the distorted phase voltages, a two-order band pass lter with band pass [300 Hz 500 Hz], functioned as an anti-aliasing lter, is inserted before ADC sampling, whose structure is shown in Fig. 14. Based on the aforementioned considerations, the bandwidth of the PLL control loop is chosen to be 400 Hz. With two order band pass lter, sampling 20 points in one 400 Hz fundamental cycle would be enough to recongure the fundamental waveform. Therefore, the sampling frequency for phase voltages could be reduced to as low as 8 kHz. Although the sampling frequency for phase voltages fs1 is only 8 kHz, the accurate phase angle can still be obtained by employing the multisampling structure as shown in Fig. 15, where fs2 is 100 kHz. In this way, the phase angle will be updated at each highfrequency control cycle as shown in Fig. 16.

Based on above analysis and for the sake of the easy implementation, a sampling frequency of 12.5 kHz is selected for the low-frequency computation group. In this application, the sampling and control frequencies are summarized in Tables III and IV. VI. S IMULATION To verify the performance of the proposed multiresolution control strategy, a 20 kVA APF model was set up in Matlab Simulink. The control system is digitalized in the simulation, and pure delay units are taken into consideration, which fully emulates the digital implementation in DSP. To demonstrate the performance difference between the proposed one and the one with 100 kHz control frequency for all control plants, two control schemes were simulated. Fig. 17 shows the grid current and the compensating current both in phase A. The THD of the proposed control scheme is 5.6% at full load, while the THD of the control scheme with 100 kHz is 5.4%, which indicates that there is only very slight difference in the current compensating performance. Fig. 18 shows dynamic performance of dc bus voltage during load step down from 20 kW to 0 kW, which also indicates that the dynamic performance of the proposed scheme is almost as same as that



dc bus and same PWM signals as shown in Fig. 20. Apart from the key parameters of the inverter modules listed in Table I, some other key circuit parameters are listed as follows: Switches Q1A-Q6A Q1B-Q6B: IXGN60N60C2D1. Dead time: 400 ns. Current sensor: HNC-661/662 (bandwidth: 200 kHz). Voltage sensor: HNV500D (bandwidth:10 kHz).

Fig. 17. Grid current in Phase A and its compensating current.

Fig. 18. cases.

Comparison on the dc voltage dynamic performance of two control

Fig. 19. 20 kVA prototype.

of the case with 100 kHz control frequency. The comparisons on the performances of other control plants are also made in the simulation and only show very slight difference. VII. E XPERIMENTAL R ESULTS A 20 kVA APF prototype was set up in the laboratory as shown in Fig. 19. Considering current stress on the power devices, two inverter modules were paralleled with a common

Uncontrolled diode rectier with LC lter and R function as a nonlinear load, whose parameters are 0.1 mH, 330 uF, and 3.6 , respectively. To minimize the execution time, mixed C and assembly language were adopted. For the time-critical codes like PI controller, dq-transformation, software PLL, etc., assembly language is used, while for non-time-critical codes, C language is used for easy coding. Fig. 21 shows the phase A voltage and current waveform without operation of APF, whose current total harmonic distortion (THD) reaches up to 28.9%. To demonstrate the performance of two control schemes with 10 us and 20 us delay time mentioned in Fig. 5, a comparative experiment study is given. Fig. 22 shows the compensating performance when employing the 20 us control delay time. The current waveform still has some distortion around zero-crossing area, and its THD is only reduced to 12.3%, which still cannot comply with the DO-160F standard. Fig. 23 shows the phase A voltage and current waveform with the proposed control method. The current THD is lowered down to 5.7%. Meanwhile, the distortion of the voltage waveform is alleviated due to the load drawing nearly sinusoidal currents from the source. Fig. 23 also shows that two channel compensating currents are totally the same, which indicates that there are no circulating currents between these two inverter modules. Since in the three-balanced system there only exist (6n 1) harmonic orders, Table V only shows the 5th, 7th, 11th, and 13th harmonic components. The high-order components are not listed in Table V as they can be easily ltered out using small reactive lters to meet the standard. From Table V, we can see that without APF compensating the current harmonic components are far above those in DO-160F standard. When the APF control system has 20 us control delay time, the current harmonic components still cannot comply with the standard. However, when the proposed control strategy is employed to reduce the current loop control period to 10 us, harmonic components are lower than those specied in the standard. Due to wide bandwidth of the voltage loop control, the dc voltage is well controlled during load change from 20 kW to 3.5 kW as illustrated in Fig. 24, whose overshoot is only 30 V above the nominal dc bus voltage 400 V. Figs. 25 and 26 show the dynamic performances with load change between 3.5 kW and 20 kW. From Fig. 25, it can be inferred that during load change from 3.5 kW to 20 kW (the load change rate is set to 5 A/ms), the dc bus voltage is still maintained the same. This means that during the slow load change condition, the dc voltage regulator with its low control frequency has the capability to keep the dc bus voltage well regulated. As seen from Fig. 26, (the load change rate is set to 20 A/ms), APF current settling time is less than 11 ms, indicating good harmonics tracking performance.



Fig. 20. Overall APF structure with two paralleled inverters.

Fig. 21. Phase voltage and current before APF operation.

Fig. 23.


Fig. 22. Phase voltage and current with 20 us control delay.

VIII. C ONCLUSION The proposed multiresolution control strategy divides the computational elements in the APF into high- and lowfrequency control groups. The high-frequency control group executes twice every switching period. After high-frequency

control elements execute eight times, an entire switching period is allocated to all computation elements. The proposed method overcomes the limitation of the DSP computation resources in the 400 Hz APF control system by rearranging the computation elements based on their different requirements of control bandwidth. The detailed analysis is given to determine the control and sampling frequencies for different control plants in the APF. The experimental results veried the proposed control



This multiresolution control strategy and its analysis method can be easily extended to digital power conversion systems with high computation requirements. R EFERENCES
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Fig. 24. Transient response during load change from 20 kW to 3.5 kW.

Fig. 25. Phase voltage and current during load change from 3.5 kW to 20 kW.

Fig. 26. Phase voltage and current during load change from 20 kW to 3.5 kW.

strategy, indicating that the control system has good harmonic current compensating effect, in addition to exhibiting a good dynamic response.



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Wei Shi was born in Jiangsu Province, China, in 1987. He received the B.S. and M.S. degrees in electrical engineering from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2008 and 2011, respectively. His main research interests include dc-ac converter, high efciency dc-dc converters, and power quality control technology.

Ying Lu was born in Jiangsu Province, China, in 1984. He received the B.S. and M.S. degrees in electrical engineering from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2006 and 2009. In 2009, he joined the Ever-solar New Energy company, Shouzhou, China. His main research interests include dc-ac converter and power quality control technology.

Haibing Hu (M09) received the B.S. degree from Hunan University of Technology, Zhuzhou, China, in 1995, the M.S. and Ph.D. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 2003 and 2007, respectively. From 2007 to 2009, he was an Assistant Professor in the Department of Control Engineering, Nanjing University of Aeronautics and Astronautics, where he is currently an Associate Professor. In 2009, he joined the Department of Electrical Engineering, University of Central Florida as a Postdoctoral Research Fellow. He has authored and coauthored more than 40 technical papers published in journals and conference proceedings. His research interests cover digital control in power electronics, multilevel inverter, digital control system integration for power electronics and applying power electronics to distributed energy systems and power quality.

Yan Xing (M03) was born in Shandong Province, China, in 1964. She received the B.S. and M.S. degrees in automation and electrical engineering from Tsinghua University, Beijing, China, in 1985 and 1988, respectively, and the Ph.D. degree in electrical engineering from Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2000. Since 1988, she has been with the Faculty of Electrical Engineering, NUAA, and is currently a professor with the Aero-Power Sci-Tech Center, College of Automation Engineering, NUAA. She has authored more than 60 technical papers published in journals and conference proceedings and has also published three books. Her research interests include topology and control for dc-dc and dc-ac converters.