WARNING:HDLCompiler:1127 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 3653: A ssignment to uart1giden ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.

vhd" Line 3699: A ssignment to clk1mhz ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\SarjKorumaDesarj.vhd" Line 260: Assignment to hatakonazy ignored, since the identifier is never used WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\acitablo1.vhd" Line 189: <ramb16_s18> remains a black-box since it has no binding entity. WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\acitablo2.vhd" Line 189: <ramb16_s18> remains a black-box since it has no binding entity. WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\acitablo3.vhd" Line 189: <ramb16_s18> remains a black-box since it has no binding entity. WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\acitablo4.vhd" Line 189: <ramb16_s18> remains a black-box since it has no binding entity. WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\acitablo5.vhd" Line 189: <ramb16_s18> remains a black-box since it has no binding entity. WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\ortalama.vhd" Line 41: < ramb16_s18> remains a black-box since it has no binding entity. WARNING:HDLCompiler:1127 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\IGBTDurumSayici.vhd" L ine 40: Assignment to clk2 ignored, since the identifier is never used WARNING:HDLCompiler:89 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\okLibrary.vhd" Line 40: <fdre> remains a black-box since it has no binding entity. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1745: Ne t <uart1tx> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1836: Ne t <dac[11]> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1843: Ne t <igbtdrive> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1844: Ne t <igbtdrm> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1845: Ne t <igbtacktest> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1846: Ne t <testword1[11]> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1847: Ne t <testword2[11]> does not have a driver. WARNING:HDLCompiler:634 - "C:\KEAS_OBS_RGK\Tutor\cmis_v2\cmis.vhd" Line 1848: Ne t <testword3[11]> does not have a driver. WARNING:Xst:647 - Input <ss> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <extra> is never used. This port will be preserved and l eft unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <clk3ext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-bloc k and the hierarchy of this sub-block is preserved. WARNING:Xst:653 - Signal <dac> is used but never assigned. This sourceless signa l will be automatically connected to value GND. WARNING:Xst:653 - Signal <testword1<11:8>> is used but never assigned. This sour celess signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <testword2<11:8>> is used but never assigned. This sour celess signal will be automatically connected to value GND. INFOWARNING:Xst:653 - Signal <testword3<11:8>> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <uart1tx> is used but never assigned. This sourceless s ignal will be automatically connected to value GND. WARNING:Xst:653 - Signal <igbtdrive> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <igbtdrm> is used but never assigned. This sourceless s

ignal will be automatically connected to value GND. WARNING:Xst:653 - Signal <igbtacktest> is used but never assigned. This sourcele ss signal will be automatically connected to value GND. WARNING:Xst:2404 - FFs/Latches <xa1<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xa2<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xa4<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xa5<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xb1<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xb2<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xb3<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xb4<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xb5<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xc2<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xc3<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xc4<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xc5<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xc1<15:14>> (without init value) have a con stant value of 0 in block <cmis>. WARNING:Xst:2404 - FFs/Latches <xa3<15:14>> (without init value) have a con stant value o Summary: WARNING:Xst:2404 - FFs/Latches <hatakonaz<1:15>> (without init value) have a constant value of 0 in block <SarjKorumaDesarj>. WARNING:Xst:647 - Input <clk2> is never used. This port will be preserved and le ft unconnected if it belongs to a top-level block or it belongs to a sub-block a nd the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <ref<5:0>> is never used. This port will be preserved an d left unconnected if it belongs to a top-level block or it belongs to a sub-blo ck and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <measured<5:0>> is never used. This port will be preserv ed and left unconnected if it belongs to a top-level block or it belongs to a su b-block and the hierarchy of this sub-block is preserved. WARNING:Xst:2404 - FFs/Latches <addr<9:8>> (without init value) have a cons tant value of 0 in block <ortalama>. WARNING:Xst:647 - Input <clk1M> is never used. This port will be preserved and l eft unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and l eft unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1710 - FF/Latch <desarjkodu_1> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_3> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_4> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization

process. WARNING:Xst:1710 - FF/Latch <desarjkodu_6> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_8> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_9> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:2677 - Node <voltajtop_0> of sequential type is unconnected in block <SarjKorumaDesarj1>. WARNING:Xst:2677 - Node <voltajtop_1> of sequential type is unconnected in block <SarjKorumaDesarj1>. WARNING:Xst:2677 - Node <voltajtop_2> of sequential type is unconnected in block <SarjKorumaDesarj1>. WARNING:Xst:2677 - Node <voltajtop_3> of sequential type is unconnected in block <SarjKorumaDesarj1>. WARNING:Xst:2677 - Node <voltajtop_0> of sequential type is unconnected in block <SarjKorumaDesarj>. WARNING:Xst:2677 - Node <voltajtop_1> of sequential type is unconnected in block <SarjKorumaDesarj>. WARNING:Xst:2677 - Node <voltajtop_2> of sequential type is unconnected in block <SarjKorumaDesarj>. WARNING:Xst:2677 - Node <voltajtop_3> of sequential type is unconnected in block <SarjKorumaDesarj>. WARNING:Xst:1710 - FF/Latch <desarjkodu_1> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_3> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_4> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_6> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_8> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <desarjkodu_9> (without init value) has a constant v alue of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <a1duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the opti mization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a4duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a2duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a3duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b2duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a5duty_7> (without

init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b1duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b5duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b3duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b4duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c1duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c2duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c5duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c3duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <c4duty_7> (without init value) has a constant value of 0 in block <SarjKorumaDesarj>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <yc1_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wb5_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wc1_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wc2_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yc2_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yc3_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wc3_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yc4_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wc4_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yc5_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wc5_15> (without init value) has a constant value o

f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <hatano_9> (without init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pro cess. WARNING:Xst:1710 - FF/Latch <hatano_10> (without init value) has a constant valu e of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pr ocess. WARNING:Xst:1710 - FF/Latch <hatano_11> (without init value) has a constant valu e of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pr ocess. WARNING:Xst:1710 - FF/Latch <dacword_0> (without init value) has a constant valu e of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pr ocess. WARNING:Xst:1710 - FF/Latch <dacword_1> (without init value) has a constant valu e of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pr ocess. WARNING:Xst:1710 - FF/Latch <dacword_2> (without init value) has a constant valu e of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pr ocess. WARNING:Xst:1710 - FF/Latch <dacword_3> (without init value) has a constant valu e of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization pr ocess. WARNING:Xst:1710 - FF/Latch <ya1_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wa1_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wa2_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <ya2_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <ya3_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wa3_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <ya4_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wa4_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <ya5_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yb1_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wa5_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wb1_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wb2_15> (without init value) has a constant value o

f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yb2_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yb3_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wb3_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yb4_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <wb4_15> (without init value) has a constant value o f 1 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1710 - FF/Latch <yb5_15> (without init value) has a constant value o f 0 in block <cmis>. This FF/Latch will be trimmed during the optimization proce ss. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <hatanoilk_9> (witho ut init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <hatanoilk_10> (with out init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <hatanoilk_11> (with out init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <hatanokalici_9> (wi thout init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <hatanokalici_10> (w ithout init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <hatanokalici_11> (w ithout init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:2677 - Node <sci1hatasyc_12> of sequential type is unconnected in bl ock <cmis>. WARNING:Xst:2677 - Node <sci1hatasyc_13> of sequential type is unconnected in bl ock <cmis>. WARNING:Xst:2677 - Node <sci1hatasyc_14> of sequential type is unconnected in bl ock <cmis>. WARNING:Xst:2677 - Node <sci1hatasyc_15> of sequential type is unconnected in bl ock <cmis>. WARNING:Xst:2016 - Found a loop when searching source clock on port 'clk2_inv:O' WARNING:Xst:1293 - FF/Latch <_i000524_7> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_11> of sequential type is unconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_10> of sequential type is unconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_9> of sequential type is u nconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_8> of sequential type is u nconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_7> of sequential type is u nconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_6> of sequential type is u

nconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_5> of sequential type is u nconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/voltajortt_4> of sequential type is u nconnected in block <cmis>. WARNING:Xst:2677 - Node <SarjKorumaDesarj1/tehlike> of sequential type is unconn ected in block <cmis>. WARNING:Xst:2677 - Node <degistiricic/dbg2> of sequential type is unconnected in block <cmis>. WARNING:Xst:2677 - Node <degistiricib/dbg2> of sequential type is unconnected in block <cmis>. WARNING:Xst:2677 - Node <degistiricia/dbg2> of sequential type is unconnected in block <cmis>. WARNING:Xst:1293 - FF/Latch <degistiricia/_i000342_14> has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <degistiricia/_i000342_15> has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <degistiricib/_i000342_14> has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <degistiricib/_i000342_15> has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <degistiricic/_i000342_14> has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <degistiricic/_i000342_15> has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_15> has a constant value of 0 in block <cm is>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_14> has a constant value of 0 in block <cm is>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_13> has a constant value of 0 in block <cm is>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_12> has a constant value of 0 in block <cm is>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_11> has a constant value of 0 in block <cm is>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_10> has a constant value of 0 in block <cm is>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_9> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_8> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_7> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_6> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_5> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch <_i000469_4> has a constant value of 0 in block <cmi s>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sayacsync1_7> (with out init value) has a constant value of 0 in block <cmis>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SarjKorumaDesarj1/p eryod_7> (without init value) has a constant value of 0 in block <cmis>. This FF /Latch will be trimmed during the optimization process. WARNING:NgdBuild:443 - SFF primitive 'okHI/core0/core0/a0/pc0/read_strobe_flop' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'okHI/core0/core0/a0/pc0/k_write_strobe_flop' has unconnected output pin WARNING:NgdBuild:440 - FF primitive 'okHI/core0/core0/a0/pc0/interrupt_ack_flop'

has unconnected output pin WARNING:Security:42 - Your software subscription period has lapsed. Your current WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue Finished initial Timing Analysis. WARNING:Par:288 - The signal ss_IBUF has no l oad. PAR will not attempt to route this signal. WARNING:Par:288 - The signal clk3ext_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal extra_IBUF has no load. PAR will not attempt to ro ute this signal. WARNING:Par:288 - The signal okHI/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mr am_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal okHI/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mr am_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:PhysDesignRules:372 - Gated clock. Clock net a1alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a5alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b3alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c1alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b5alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c3alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a2alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a3alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a4alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a5alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b1alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a4alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b2alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b2alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net b3alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b4alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c1alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c2alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c4alici/yenivoltaj is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c4alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net clk3 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c5alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a1alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b4alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c2alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a2alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net clk1k is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net a3alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b1alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net c3alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net b5alici/UartRx1/tmpDRdy is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:367 - The signal <ss_IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal <clk3ext_IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal <extra_IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal <okHI/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal <okHI/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_O> is incomplete. The signal does not drive any load pins in the design.