Achieving DFT Closure The Next Step in Design For Test

2001 Synopsys, Inc.

Overview
EDA tools have dramatically improved the productivity of conventional ASIC design flows by enabling rapid, predictable and repeatable constraint closure. The industrys adoption of powerful design methodologies such as formal verification, static timing analysis and new technologies such as physical synthesis are speeding the implementation and verification of multi-million gate ASICs and Systems-on-Chip (SoCs). Relative to manufacturing test, the exponential growth in size and complexity of these devices, coupled with increasingly stringent quality mandates, demands new approaches in design-for-testability (DFT) that must go beyond todays stateof-the-art. While test synthesis is the most widely used DFT methodology in conventional ASIC design flows, it is quickly becoming evident that testability must be addressed throughout the entire design process. To successfully meet all the design goals of todays and tomorrows enormously complex devices, swift convergence of function, timing, area and power requirements must be simultaneously accompanied by new test tools that enable rapid, predictable and repeatable DFT closure. Achieving successful DFT closure requires that RTL designers and DFT engineers work in concert on a unified view of the design, using integrated tools and flows. It also requires that DFT tools have zero impact on critically important timing closure flows. The technologies necessary to support this wide-ranging view of testability are: EDA test tools that begin at the RT level and are integrally linked to synthesis Test synthesis cognizant of layout issues and well integrated with physical design tools Test synthesis capable of directly synthesizing all DFT architectures, with full constraint optimization Completely automated creation, verification and management of design data created and consumed by EDA test tools These are the next steps in DFT tools that will be necessary to achieve the new requirement of DFT closure.

What is DFT Closure? Why is it Important Now?

Simply put, DFT closure is the ability to rapidly and predictably meet all mandated DFT requirements through every phase of a SoC design flow, with no risk of design iterations caused by unanticipated test impact. As ICs get more sophisticated, not embracing a reliable DFT closure methodology may result in designs that both substantially miss market windows and still fail to meet required functionality, performance and manufacturability goals. DFT closure assumes a top-down hierarchical design approach that predictably proceeds from RT-level, presynthesis planning all the way to physical implementation. Traditional over-the-wall methodologies requiring design handoffs between discrete processes, such as between synthesis and scan insertion, are becoming intractable. In over-the-wall approaches, it is all too easy to lack knowledge and an understanding of integration issues between discrete design processes, which lead to schedule-killing iterations. Figure 1 depicts an over-the-wall gate-level DFT flow with many iteration loops due to the likelihood of finding problems later in the design flow.

2001 Synopsys, Inc.

RTL

Synthesis

Invalid Scan Chain Elements

Timing Violations Due to Scan

Scan Insertion

Reoptimization

Scan Ordering Problems Low Fault Coverage

Place

Scan Routing Problems Unbalanced Vector Sets

Setup/hold Problems
Route

Clock Domain Violations

ATPG

Simulation Mismatches
Resimulation

Figure 1

In this approach, there are numerous opportunities for the designer to unknowingly break DFT design rules, and thus incur unacceptably long iteration loops to fix these problems. To avoid this situation, each design process in a more-robust flow must follow two new rules: 1. Each design process must be self-containedit cannot rely on a subsequent process to completely satisfy its goals. 2. Each design process must perform its task with a full understanding of the requirements of the subsequent process, and transfer only valid information to it. For example, todays design tools and flows all strive to achieve timing closure. Advanced design flows using common timing engines that forward-annotate timing constraints from high-level design to physical synthesis, can eliminate design iterations and enable huge productivity gains for cutting-edge devices. Because these advanced designs must also be testable, complete DFT closure should be achieved in parallel. By applying these rules in a DFT context, Figure 2 illustrates the benefits of an up-to-date test synthesisbased design flow. The long iteration loops from the lack of DFT knowledge between synthesis and separate test activities are partially eliminated. Design flow closure is achievable when these requirements are met for all steps in the flow.

2001 Synopsys, Inc.

RTL

Invalid Scan Chain Elements

Scan Synthesis

Scan Ordering Problems Scan Routing Problems

Place

Unbalanced Vector Sets

Route

Clock Domain Violations

ATPG

Simulation Mismatches
Resimulation

Figure 2

Finally, a new design flow supporting complete DFT closure has two additional requirements: 3. Each design process is cognizant of all relevant DFT issues, and is able to meet all relevant design and DFT requirements simultaneously. 4. Each design process transfers only DFT design-rule correct databases to subsequent processes Figure 3 shows a state-of-the-art design flow that supports DFT closure. Smart partitioning of the design flow eliminates long iteration loops.

RTL+DFT

Scan Synthesis w/ Physical Integration

Route

ATPG Integrated w/Routing

Figure 3

2001 Synopsys, Inc.

The Road to DFT Closure

Achieving successful DFT closure is a process that will evolve and strengthen as new tools and EDA methodologies are presented to the market. With existing technology, there are currently two requirements: 1. Implementing a flow that satisfies all design requirements in a predictable manner. 2. Being able to do this very quickly, without excess design iterations and wasted designer effort. For complex ASICs and SoCs, both of these requirements must be met. So, in addition to the required, intelligent, up-front planning of design and test architectures and design flows, key design and test technologies must be deployed as well. These may include: Test-enabled RT-level code checking In-depth RT-level DFT design rule checking, analysis and verification integrated with design synthesis and consistent with downstream test synthesis and ATPG tools Comprehensive test synthesis capabilities within a timing closure flow DFT links to physical synthesis, placement and routing Synthesis- and gate-level manufacturing testability analysis Design tools sign-off to ATPG ATPG sign-off to vector validation and production test Each of these technologies contribute to DFT closure by enabling completion of all relevant design and test tasks within its single process, and transfer of complete and valid design data to the following process. By doing so, designers can eliminate the risk of long iteration loops between processes. The following figure shows the benefit of each of these technologies in enabling DFT closure in a design flow:

RTL+DFT

Test-friendly RTL coding, scan DRC checking

Scan Synthesis w/ Physical Integration

Constraint-optimized test synthesis Automatic test DRC fixing Physical synthesis integrationoptimized scan chain ordering 1149.1 synthesis and validation Fault coverage validation in synthesis

Route

ATPG Integrated w/Routing

Scan chain routing constraint communication between synthesis, route and ATPG

Figure 4

2001 Synopsys, Inc.

DFT Closure and Test Reuse

Test tools that enable DFT closure offer other benefits as well. Provided they are truly automatic and transparent to the user, scan synthesis tools make it easy for the designer to implement test without having to learn the intricacies of test engineering. Implementing scan during synthesis also means that designers on different teams, working on different blocks of a complex design, can individually be responsible for the testability of their subdesigns, and know the whole device will be testable when it is assembled at the top level. This is especially important for companies that have embraced design reuse, are using pre-designed intellectual property (IP) cores, and are following new core-based design flows. Truly automated scan synthesis tools are critical in these new IP-based design methodologies to enable DFT closure for the most complex systems-on-chip.

Beyond DFT Closure in The ASIC and SoC Design FlowFuture Possibilities
The ultimate goal of implementing strong DFT methodologies is to enable the very best results and productivity in the manufacturing test environment. Implementing DFT closure to eliminate iteration loops between the entire design activity and the test floor itself is the logical next step. However, with the existing over the wall relationships between the design world and the automatic test equipment (ATE) world, achieving effective DFT closure between these two worlds will be challenging. The catalyst for change will be the type of paradigm shift that now enables DFT closure in the RTL-to-GDSII flow: Knowledge of DFT must be built directly into ATE, and ATE requirements must be built directly into design and DFT tools. Design, DFT and ATE must conform to common standards, methodologies and/or pre-negotiated requirements. This will eliminate many of the inefficiencies incurred by the many design and data transfers that are now a requirement. Once this is accomplished, the industry will realize the full productivity, cost savings and designer impact benefits of DFT closure. In addition, comprehensive DFT closure can enable the development of a new class DFT-aware automatic test equipment, which can lead to dramatic reductions in the cost of test.

Conclusion
The Sematech Technology Roadmap clearly points to critical issues in manufacturing testability that will keep life interesting for both design engineers as well as test tool vendors. The relentless growth in ASIC and SoC size and complexity, fueled by corporate demands on manufacturability, make testability a mandate. Design teams and EDA tools must consider DFT an integral part of the entire RTL to GDSII flow, and achieve the goal of rapid and predictable DFT closure. This means that test must be considered on an equal footing with the other major design requirements: function, timing, area and power. EDA tools must simultaneously address all of these design requirements and include test-any possibility of testinduced iterations to the earliest stages of the design flow must be eliminated. Great progress has been made to provide DFT closure flows to the design community however, more work remains. As IC design flows are evolving to solve timing closure and verification bottlenecks, test tools must keep pace to ensure the design community is able to achieve rapid DFT closure. At the same time, testability must also cross over from the design world, and link to the ultimate environment for testabilitythe hardware tester.

2001 Synopsys, Inc.

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