Post-Processing Your OVM/UVM Simulation Results

Cadence Incisive Enterprise Simulator provides advanced debug capabilities through SimVision, which enables users to visualize the convergence of the SystemVerilog testbench and the design under test (DUT). SimVision offers SystemVerilog Universal Verification Methodology (UVM)/Open Verification Methodology (OVM) users the ability to post-process and provides a broad set of advanced features to this audience.

Introduction

Contents
Introduction ................................. 1 Preparing for Post-Process Debug ..................... 3 Using Saved Data for Post-Processing ............................ 4 Accessing Instance-Specific Data .................. 4 Accessing Class Objects in the Class Browser ..................... 6 Other Verification Methodologies ............................ 6 Learning More ............................. 7

Many users of SystemVerilog have relied upon $display statements for obtaining debug information for their verification testbenches. However, this approach takes debug back two decades. Starting in the 9.2 version of Cadence Incisive Enterprise Simulator, this is no longer required. You can take advantage of the advanced debug capabilities provided by SimVision to both interactively debug and post-process your verification environments. By using this new approach, you can visualize the convergence of your SystemVerilog testbench and the design under test (DUT), even if that DUT contains Verilog, VHDL, and SystemC code. This transaction level of abstraction allows the verification engineer and the design engineer to more easily discuss the design and testbench intent, which enables a more efficient path to Silicon Realization.1 SimVision supports the two most common use models for debug. The first use model is to perform interactive simulation with SimVision to display simulation results, set break points, and interact with the DUT while running the simulation. The other common use model is to run simulation in batch mode, record data to a waveform database, and then analyze the results after simulation is complete. This latter use model presents challenges when trying to post-process results when the DUT is being driven by a class-based verification environment, such as the Open Verification Methodology (OVM) or Universal Verification Methodology (UVM). In a traditional module-based testbench environment, the hierarchy of the design and verification testbench is known at time zero since the modulebased environment is elaborated into the simulation image. OVM/UVM, like other class-based verification environments, are quasi-static. This means that

For more information on Silicon Realization, please refer to the whitepaper on http://www.eda360.com.

Post-Processing Your OVM/UVM Simulation Results

the verification hierarchy does not exist until it is constructed during runtime simulation, and once constructed, the verification hierarchy does not change. Since it does not exist until constructed, the simulation image created during elaboration does not contain the verification environment hierarchy. SimVision takes advantage of the quasi-static nature of OVM/UVM to display the verification hierarchy along with the design hierarchy. This hierarchy is available after the build phase of the OVM/UVM environment. Figure 1 shows the verification hierarchy at time zero, before the UVM build phase is complete. You will notice that uvm _ top _ levels does not have any children.

Figure 1: UVM Hierarchy Prior to Construction

Figure 2 shows the hierarchy after the build phase. In this image, uvm _ top _ levels has children and displays the quasi-static verification hierarchy.

Figure 2: UVM Hierarchy After Construction

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Post-Processing Your OVM/UVM Simulation Results

Preparing for Post-Process Debug

Currently, objects cannot be probed until they are created. In order to probe the verification hierarchy to a waveform database, the build phase must be complete (as shown in Figure 2). Both OVM and UVM supply Tcl commands in simulation that allow you to stop at the end of the build phase. To reach this point, issue the following commands: For UVM: uvm _ phase stop _ at run run For OVM: ovm _ phase stop _ at run run The first command creates a breakpoint to stop at the beginning of the run phase. This is immediately after completing the end _ of _ elaboration phase of the OVM/UVM environment. The run command advances simulation to the breakpoint set in the first command. After the run command, the verification hierarchy is constructed. You can now access the quasi-static hierarchy and perform operations on the dynamically created data. There are two operations of importance for you. The first is to probe the verification hierarchy. The second is to create a snapshot (after the build phase) of the simulation image that contains the quasi-static verification hierarchy. To probe the hierarchy, issue the following command: For UVM: probe -create -shm worklib.uvm _ pkg::uvm _ top _ levels -depth all For OVM: probe -create -shm worklib.ovm _ pkg::ovm _ top _ levels -depth all This probes the entire verification hierarchy to a waveform database. If you have not already created a waveform database, a default database called ncsim.shm is created. Now you will want to save a simulation snapshot to use during post-processing. To do this, issue the following commands: run -clean save -simulation debug The run clean command makes sure that the simulation is in a state that can be saved to disk. The save simulation command creates a saved snapshot image called debug. Now you can run simulation to completion. All of these steps can be automated by using the input command script capability to irun. To do this for UVM, create the following command script: uvm _ phase -stop _ at run run probe -create -shm worklib.uvm _ pkg::uvm _ top _ levels -depth all run -clean save -simulation debug run If you save this into a Tcl script called debug.tcl, it can be added to the irun command line, as follows: irun <irun options> -input debug.tcl

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Post-Processing Your OVM/UVM Simulation Results

Upon completion of simulation, all of the data necessary for viewing the verification environment in a postprocessing mode is now ready. The necessary data is the debug.tcl file, the ncsim.shm database, and the postconstruction simulation snapshot. If additional probes are required for full debug, they can be added to the debug. tcl file. It should be noted that probing the scope containing the OVM/UVM top level will not include the dynamic hierarchy. In order for the dynamic hierarchy to be recorded to the database, you must explicitly probe it as in the above example.

Using Saved Data for Post-Processing

To get the post-processing debug environment with SimVision, the snapshot must be used along with the waveform database. To make sure you have the correct snapshot name, use the ncls utility with the -snapshot option to get a listing of your snapshots. If you ran simulation with irun and saved the snapshot as listed in the previous section, the snapshot name will be worklib.debug:sv. You then use this on the SimVision command line along with the waveform database, as follows: simvision snapshot worklib.debug:sv ncsim.shm This starts SimVision with the saved debug snapshot loaded and the waveform data recorded to the SHM database overlaid on the snapshot hierarchy. This allows you to view the design and testbench hierarchy, the class inheritance hierarchy, the recorded signal hierarchy including transactions recorded from OVM/UVM, and source with values annotated for instances of class objects.

Accessing Instance-Specific Data

Once the snapshot and database are loaded, you can see the OVM/UVM top level listed in the Design Browser window. Due to current limitations, the OVM/UVM instance hierarchy does not display in the scope tree, as it does in interactive simulation, but all of the data is available. To access this, simply select the OVM/UVM top level, and in the right-hand signal list, expand uvm_top_levels/ovm_top_levels to access the OVM/UVM components. Figure 3 shows the UVM component hierarchy expanded in the signal list portion of the Design Browser window.

Figure 3: UVM Hierarchy Expanded in Signal List in Post-Process Mode

You can now select a component and display the waveform for it, and send the instance to the Source Browser to view instance-specific source value annotation. You can also select data members from an object and display the data members in the source as well. This will show the instance in the source window with the declaration line of the data member highlighted. Figure 4 shows a component displayed in the waveform window with the object referenced by the bus monitor expanded to show the data members of the object.

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Post-Processing Your OVM/UVM Simulation Results

Figure 4: Bus Monitor Displayed in Waveforms with Object Expanded

When viewing an object in the source, you can enable source value annotation to display values for data members of that object instance. In Figure 5, the source for the bus monitor instance is displayed.

Figure 5: Bus Monitor Instance with Value Annotation

Notice that line 131 is highlighted. This is because the data member named data was selected in the waveform prior to sending it to the Source Browser.

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Post-Processing Your OVM/UVM Simulation Results

Accessing Class Objects in the Class Browser

You can view the class inheritance hierarchy by using the Class Browser sidebar. When viewing this in a postprocess mode, any instance of a selected class definition is displayed in the Objects column of the sidebar. Selecting an instance in this column displays that instance in the source window. You can also access the Class Browser sidebar in the Design Browser window. In Figure 6, the Class Browser sidebar is displayed with an instance of the bus monitor selected. This shows the instance in the source region with value annotation for data members of that instance.

Figure 6: Object from Class Browser Displayed in Source

Other Verification Methodologies

The steps described above are specific to the supported OVM/UVM. For other methodologies, a similar use model would apply. For this you would have to: Run simulation past the verification environment construction phase Save a simulation snapshot to create the debug snapshot Probe the verification hierarchy, as follows: probe create shm <path to verification hierarchy root> -depth all This would result in a waveform database that contains the objects created in the quasi-static verification hierarchy and data that it generates. When post-processing this data, SimVision should be invoked with both the snapshot saved after construction and the waveform database that was generated. You can then traverse the design hierarchy to find the root of the verification environment, and access the verification hierarchy components from this root in the Design Browser signal list. You can also view the inheritance hierarchy and select instances of classes for display in waveforms and source.

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Post-Processing Your OVM/UVM Simulation Results

Learning More
SimVision offers SystemVerilog OVM/UVM users a broad set of advanced features beyond the ability to postprocess. A great way to become familiar with these is to either schedule a lunch-and-learn session with your local account team or access the SimVision workshop in the Incisive Verification Kit. The Incisive Verification Kit is supplied with the Incisive Enterprise Simulator XL starting with the 9.2 release. When you access the Kit, you will find a reference design and verification environment that will allow you to explore SystemVerilog class debug, tracing of dynamic objects, OVM/UVM-specific features, key Tcl commands, instructions on how to access the automatic transaction recording, using the stripe charts, using the heap analysis, and TLM debug. For information on installing and using the Incisive Verification Kit, please refer to the Incisive Verification Kits Getting Started manual online or contact your local support engineer.

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