DSP56301ADM: User's Manual

DSP56301ADM
Users Manual
Motorola, Incorporated Semiconductor Products Sector Wireless Division 6501 William Cannon Drive West Austin, TX 78735-8598
Order this document by: DSP56301ADMUM/AD
Introduction
This document supports the DSP56301 Application Development Module (DSP56301ADM), including a description of its basic structure and operation, the equipment required to use it, the specifications of the key components, schematic diagrams, and a parts list. Section 1 is a Quick Start Guide. Section 2 provides detailed information about key components in the evaluation module. Appendix A has detailed schematics.Appendix B lists the Bill Of Materials (BOM) for the board. Detailed information is provided in the additional documents supplied with this kit.
OnCE and Mfax are trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:

USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447 Mfax: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC 6F Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 81-3-3521-8315
TABLE OF CONTENTS
SECTION 1 QUICK START GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . 1.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EQUIPMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 What You Get with the DSP56301ADM . . . . . . . . . . . . . . . . 1.2.2 What You Need to Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 INSTALLATION PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Preparing the DSP56301ADM. . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Connecting the DSP56301ADM to the PC and Power . . . . . 1.4 USING THE DSP56301ADM . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-3 1-3 1-3 1-4 1-4 1-5 1-8 1-8
SECTION 2 DSP56301ADM TECHNICAL SUMMARY. . . . . . . . . . 2-1 2.1 DSP56301ADM DESCRIPTION AND FEATURES . . . . . . . . . . 2-3 2.2 DSP56301 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.1 DRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2 SRAM Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.3 Flash PROM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 DSP56301 OPERATING MODE SELECTION. . . . . . . . . . . . . . 2-8 2.5 CLOCK SOURCE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5.1 On-Board Clock Generator Selection . . . . . . . . . . . . . . . . . 2-10 2.5.2 External Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.5.3 Crystal Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.5.4 DSP56301 PLL Enable/Disable On Reset. . . . . . . . . . . . . . 2-11 2.6 HOST PORT SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7 ISA DMA AND INTERRUPT CHANNELS . . . . . . . . . . . . . . . . 2-12 2.8 CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.8.1 Expansion And Logic Analyzer Connectors. . . . . . . . . . . . . 2-13 2.8.2 5 V Power Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.8.3 HI32 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.8.4 SSI Port Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.8.5 SCI Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.8.6 JTAG/OnCE Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
MOTOROLA
DSP56301ADMUM/AD, Preliminary
iii
APPENDIX A
DSP56301ADM SCHEMATICS . . . . . . . . . . . . . . . . . A-1
APPENDIX B DSP56301ADM BILL OF MATERIALS . . . . . . . . . . . B-1 B.1 DSP56301ADMELECTRICAL PARTS LIST REV. 2.13/15/95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2 DSP56301 ADMHARDWARE PARTS LIST REV. 2.13/15/95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
iv
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LIST OF FIGURES
Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 DSP56301ADM Key Component Layout. . . . . . . . . . . . . . . . . . . . . . 1-6 Application Development. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 DSP56301ADM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . 2-4 DSP56301ADM DRAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 SRAM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Flash PROM Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 DSP Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3.3 V Clock Generator Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 PLL Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Expansion Connector (P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Expansion Connector (P12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Expansion Connector (P5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Expansion Connector (P7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Dedicated SSI Connector (P3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 SSI - AIB Connector (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 SCI Dedicated Connector (P6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 JTAG/OnCE Connector (P4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
MOTOROLA
LIST OF TABLES
Table 1-1 Table 2-1 Table 2-2 Table 2-3 Table 2-4 DSP56301ADM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . 1-7 DSP56301ADM Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 DSP56301 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . 2-9 ISA Bus DMA Channel Configuration. . . . . . . . . . . . . . . . . . . . . . . . 2-12 ISA Bus Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
vi
MOTOROLA
SECTION 1 QUICK START GUIDE
MOTOROLA
1-1
Quick Start Guide
1.1 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.2 1.4
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 EQUIPMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 What You Get with the DSP56301ADM . . . . . . . . . . . . . . . . .1-3 What You Need to Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 INSTALLATION PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 Preparing the DSP56301ADM . . . . . . . . . . . . . . . . . . . . . . . .1-5 Connecting the DSP56301ADM to the PC and Power . . . . . .1-8 USING THE DSP56301ADM. . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1-2
MOTOROLA
Quick Start Guide Overview
1.1
OVERVIEW
The Motorola Application Development System (ADS) is a tool used to design and test complex software applications and hardware products using a specific Motorola DSP chip. The related Application Development Modules (ADMs) contain the DSP chip and related hardware used for bench development and test. Detailed information about the content and use of the ADS is provided in the ADS Users Manual (order # DSPADSUM/AD). This manual provides specific information about the DSP56301 Application Development Module (DSP56301ADM). This section provides a summary description of the DSP56301ADM, additional requirements, and quick installation information. Detailed information about the DSP56301ADM design and operation is provided in the remaining sections of this manual.
1.2
EQUIPMENT
The following section gives a brief summary of the equipment required to use the DSP56301 Application Development Module (DSP56301ADM), some of which will be supplied with the module, and some of which must be supplied by the user.
1.2.1
What You Get with the DSP56301ADM
The following materials are provided with the DSP56301ADM: DSP56301 Application Development Module board DSP56301ADM Product Information DSP56301ADM Users Manual (this document) Motorola Digital Signal Processor Registration Form
MOTOROLA
1-3
Quick Start Guide Installation Procedure
1.2.2
What You Need to Supply
Motorola Application Development System with appropriate host interface card Host Computer system: PC-compatible computer (486 class or higher) with: MS-DOS version 6.0 or later or Windows 3.1 or later or Windows 95 8 Mbytes RAM one open 16-bit ISA or a PCI expansion slot free I/O addresses ($100$102, $200202, or $300$303) CD-ROM drive hard drive with 4 Mbyte of free disk space mouse Sun Microsystems Sun 4 Workstation running Sun Operating System Release 4.1.1 or later (or Solaris Release 2.5 or later), one open SBus expansion slot, CD-ROM drive, and a mouse Hewlett Packard HP7xx Workstation running HPUX Version 9.x (Version 10.x is not supported), one open EISA expansion slot, CD-ROM drive, and a mouse
1.3
INSTALLATION PROCEDURE
Installation requires the following steps: 1. Using information provided in the Motorola ADS Users Manual, install the Motorola Application Development System in the host computer. 2. Prepare the DSP56301ADM board 3. Connect the board to the external Command Converter card
1-4
MOTOROLA
1.3.1
Preparing the DSP56301ADM
CAUTION
Because all electronic components are sensitive to the effects of electrostatic discharge (ESD) damage, correct procedures should be used when handling all components in this kit and inside the supporting personal computer. Use the following procedures to minimize the likelihood of damage due to ESD: Always handle all static-sensitive components only in a protected area, preferably a lab with conductive (anti-static) flooring and bench surfaces. Always use grounded wrist straps when handling sensitive components. Never remove components from anti-static packaging until required for installation. Always transport sensitive components in anti-static packaging.
Locate the fourteen jumper blocks JP1JP14 and switch block SW2 on the DSP56301ADM board, as shown in Figure 1-1 on page 1-6. Table 1-1 describes the default jumper and switch settings when shipped from the factory. Read the technical summary in Section 2 of this manual for additional information about the DSP56301ADM board and its components.
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1-5
Note: 5 V is on side closest to switch.
Figure 1-1 DSP56301ADM Key Component Layout
1-6
OFF
ON
MOTOROLA
Table 1-1 DSP56301ADM Default Jumper Options

Jumper/Switch Block JP1 JP2 JP3 JP4,JP5, JP6, JP7 JP8,JP10 JP9 JP11 JP12 JP13,JP14 SW2 Default Configuration as Shipped Jumpered Jumpered Jumpered Jumpered JP8No jumpers JP10Pins 36 and 45 jumpered Pins 12 jumpered Pins 45 jumpered Removed JP13 Removed JP14 Pins 25 jumpered SW21: Off SW22: On SW23: Off Comment Enable SRAM memory Enable DRAM memory Enable Flash memory Enable ISA host interface Set ISA DMA channel 5 Set ISA clamp protection Set ISA Interrupt channel 10 Enable DSP PLL operation Set clock source to clock generator. Bootstrap from HOST ISA
Note:
The factory default configuration selects ISA bus operation for the plug-in card feature. Refer to Section 2.6 Host Port Selection for other available port configurations.
MOTOROLA
1-7
Quick Start Guide Using the DSP56301ADM
1.3.2
Connecting the DSP56301ADM to the PC and Power
Figure 1-2 shows the interconnection diagram for connecting the PC and the external power supply to the DSP56301ADM board. Using the instructions in the ADS Users Manual, connect the Command Converter to the ADM board. Power for the ADM is supplied from the Command Converter module.
37-pin Interface Cable Host Computer 14-pin Ribbon Cable User Application Circuits
Motorola DSP Host-Bus Interface Card Command Converter Application Development Module (ADM)
Figure 1-2 Application Development
1.4
USING THE DSP56301ADM
Once the ADM is installed, it becomes a part of the Application Development System. Use information in the Application Development System Users Manual to develop your application design, debug it, and test it.
1-8
MOTOROLA
SECTION 2 DSP56301ADM TECHNICAL SUMMARY
MOTOROLA
2-1
DSP56301ADM Technical Summary
2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6
DSP56301ADM DESCRIPTION AND FEATURES . . . . . . . . . . .2-3 DSP56301 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 DRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 SRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 Flash PROM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 DSP56301 OPERATING MODE SELECTION . . . . . . . . . . . . . .2-8 CLOCK SOURCE SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . .2-9 On-Board Clock Generator Selection . . . . . . . . . . . . . . . . . .2-10 External Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 Crystal Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 DSP56301 PLL Enable/Disable On Reset . . . . . . . . . . . . . .2-11 HOST PORT SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 ISA DMA AND INTERRUPT CHANNELS . . . . . . . . . . . . . . . . .2-12 CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 Expansion And Logic Analyzer Connectors . . . . . . . . . . . . .2-13 5 V Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18 HI32 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18 SSI Port Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19 SCI Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20 JTAG/OnCE Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21
2-2
MOTOROLA
DSP56301ADM Technical Summary DSP56301ADM Description and Features
2.1
DSP56301ADM DESCRIPTION AND FEATURES
The DSP56301ADM is designed as a versatile card that can be used not only as a stand-alone board, but can also be plugged into other cards. Four 50-pin connectors allow access to all the DSP signals, including VDD and VSS. This plug-in feature permits special configurations, including, among others, connection to a customized wire-wrapped or other application board to permit enhanced functionality. An overview description of the DSP56301ADM is also provided in the DSP56301ADM Product Information document (order number DSP56301ADMP/D) included with this kit. The main features of the DSP56301ADM include the following: DSP56301 24-bit Digital Signal Processor 32 K Word FSRAM with 12 ns access (5 V) 64 K Byte Flash PROM Memory, 200 ns access on-board (3 V) programmable 512 K Word DRAM, 70 ns access. ISA bus compatible edge-connector (slave only operation). PCI bus compatible edge-connector (master & slave operation). Table mounted (stand-alone) operation, or computer plug-in card operation. Integrated Expansion and Logic-Analyzer Connectors. Dedicated SSI and SCI port connectors. JTAG/OnCE port connector for easy hookup to Motorola command converter 5 V operation, with on board 3.3 V voltage regulation. Power terminals and 8-pin clock socket for stand-alone operation. Note: Call your local Motorola sales office or distributor for additional information about the Motorola Application Development System (ADS) kit. The ADS kit includes two additional boards: a host interface card and an external universal command converter. The host interface card plugs in the host bus (on a PC-compatible, HP7xx workstation, or Sun/Sun-compatible system) inside the computer chassis. The external universal command converter card connects to the host card via a 37-pin ribbon cable. The command converter card connects to the JTAG connector on the DSP56301ADM via another short 14-pin ribbon cable. The ADS is only compatible with Motorola software tools.
MOTOROLA
2-3
DSP56301ADM Technical Summary DSP56301ADM Description and Features
Expansion & Logic Analyzer Connectors
Reset Clock Gen. & Mode sel.
64 K X 8 Flash PROM (3 V) AT29LV512 (ATMEL)
DSP56301 PORT A HI32 PORT SCI PORT SSI PORTS
3 V <-> 5 V Signals buffers
32 K 24 Static RAM MCM6706AJ12
512 K 24 DRAM MCM54800AJ70
ISA Edge Connector JTAG/OnCE PCI Edge Connector JTAG/OnCE Connector
SCI Port SSI0 and SSI1 Port & AIB I/F
5 V to 3 V voltage regulator
Figure 2-1 DSP56301ADM Functional Block Diagram
2-4
MOTOROLA
DSP56301ADM Technical Summary DSP56301 Description
2.2
DSP56301 DESCRIPTION
A full description of the DSP56301, including functionality and user information is provided in the following documents included as a part of this kit (either as printed copies or on the documentation CD-ROM): DSP56301 Technical DataProvides features list and specifications including signal descriptions, DC power requirements, AC timing requirements, and available packaging DSP56301 Users ManualProvides an overview description of the DSP and detailed information about the on-chip components including the memory and I/O maps, peripheral functionality, and control and status register descriptions for each subsystem DSP56300 Family ManualProvides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set Refer to these documents for detailed information about chip functionality and operation.
2.3
MEMORY
Table 2-1 lists the memory used in the DSP56301ADM. Table 2-1 DSP56301ADM Memories
TYPE DRAM SRAM Flash PROM SIZE 512 K Word 32 K Word 64 K Byte SPEED 70 ns 12 ns 200 ns AA line (used as chip select) AA3 AA0 AA1
MOTOROLA
2-5
DSP56301ADM Technical Summary Memory
2.3.1
DRAM Selection
The DSP56301ADM uses a single bank of three 512 K 8, 70 ns, 5 V-only DRAMs (Motorola MCM54800AJ70). The DRAM is accessed by the DSP56301 using 3 wait-cycles during Page mode (not including the RAS precharge time at a beginning of a new page) and 11 wait-cycles in a non-page access, when the DSP operates at 66MHz. Address bus load capacitance from this configuration is 5 pF 3, or 15 pF per address line. Data bus load capacitance is 7 pF. The AA3 (Address Attribute) signal is used as a Row Address Strobe (RAS) and Chip Enable (CE) line. The design uses the SOJ package to achieve greatest space reduction. DRAM refresh is provided by the DSP56301 DRAM controller. The DRAM connection is illustrated in Figure 2-2.
MCM54800AJ70 A0A9 AA3/RAS CAS WR RD A0A9 RAS CAS W G DQ0DQ7 D0D23 A0A9 RAS CAS W G DQ0DQ7 A0A9 RAS CAS W G DQ0DQ7 D0D7
D16D23
D8D15
Figure 2-2 DSP56301ADM DRAM Interface Note: The DRAM memory is enabled/disabled using jumper JP2. When JP2 is placed, the DRAM is enabled. When JP2 is removed, the DRAM is disabled, and the user may use AA3 for other purposes.
2.3.2
SRAM Selection
Three Motorola MCM6706AJ12 SRAMs are used to optimize performance. These SRAMs are 32 K 8, Bi CMOS, 5 V-only devices with an access time of 12 ns. Address bus load capacitance in this configuration is 5 pF 3, or 15 pF per address line. Data bus load capacitance is 6 pF. The SRAM is accessed by the DSP56301 with 1 wait-state when the DSP operates at 66MHz clock. The chip-select signal for the SRAM is generated using the DSP56301 AA0 line. The MCM6706AJ12 SRAM uses 5 V input power. Connection to the SRAM is shown in Figure 2-3 on page 2-7.
2-6
MOTOROLA
DSP56301ADM Technical Summary Memory
MCM6706AJ12 A0A14 A0A14 A0A14 A0A14
WR AA0 RD
W E G DQ0DQ7 D16D23
W E G DQ0DQ7 D8D15
W E G DQ0DQ7 D0D7
D0D23
Figure 2-3 SRAM Connection Note: The SRAM memory is enabled/disabled using jumper JP1.When JP1 is placed, the SRAM is enabled. When JP1 is removed, the SRAM is disabled, and the user may use AA0 for other purposes.
2.3.3
Flash PROM Selection
The DSP56301ADM includes a Flash PROM to facilitate stand-alone operation. The FPROM is on-board and programmable, making it ideal for programming updates. The DSP56031ADM uses a programmable, byte-wide, AT29LV512, 3 V-only (eliminating the need for additional supply or a DC-DC converter) FPROM with 200 ns access time. The load capacitance of this chip is 6 pF on the address lines and 12 pF max on the data lines. The Flash memory may tolerate up to 1000 program cycles per sector (each sector is 128 bytestotal of 512 sectors). The AT29LV512 has a low-power write-protect feature to guard against inadvertent writes during power transitions. The FPROM also permits data polling during programming to shorten programming cycles. Figure 2-4 on page 2-8 illustrates the DSP56301 hookup to a byte wide non-volatile memory. All actions to the device are controlled via a sequence of commands written to the device.
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2-7
DSP56301ADM Technical Summary DSP56301 Operating Mode Selection
29F010-12 A0A16 WR RD AA1 A0A16 WE OE CE DQ0DQ7 D0D7
Figure 2-4 Flash PROM Connection Note: The Flash memory is enabled/disabled using jumper JP3. When JP3 is placed, the Flash is enabled. When JP3 is removed, the Flash memory is disabled, and the user may use AA1 for other purposes.
2.4
DSP56301 OPERATING MODE SELECTION
Support is provided to enable the DSP56301 to enter one of six possible operating modes (two additional modes are reserved), via MODA/IRQAMODC/IRQC and NMI/PINIT lines.These lines are sampled by the DSP56301 on the rising edge of RESET line and the sampled combination is moved to the OMR (Operating Mode Reg.). Figure 2-5 illustrates the mode selection on the deassertion of the RESET signal. After reset, the mode selection lines are driven by pull-up resistors. JP12 is connected to the NMI/PINIT line.
RESET QS3244SO (2 to 1 MUX) INTERRUPT REQUESTS 1 INIT MODE SELECT TO DSP56301
Figure 2-5 DSP Mode Selection
2-8
MOTOROLA
DSP56301ADM Technical Summary Clock Source Selection
Table 2-2 DSP56301 Operating Mode Selection

MODE 0Expanded mode 1Bootstrap from byte-wide FLASH 2Bootstrap through SCI 3Reserved 4Host Bootstrap PCI mode (32-bit-wide) 5Host Bootstrap ISA Mode (16-bit-wide) 6Host Bootstrap UB Mode (8-bit-wide) 7 Reserved SW2(1) On Off On Off On Off On Off SW2(2) On On Off Off On On Off Off SW2(3) On On On On Off Off Off Off
After the RESET line is released (high) the MOD/IRQ signals are connected to IRQA, IRQB, and IRQC signals.
2.5
CLOCK SOURCE SELECTION
There are 3 clock sources to the DSP56301: On-board 33MHz clock generator, supplied from factory External BNC connector Crystal Oscillator Note: When either of the first two options are used, set bits XTLD and COD in the PLL Control Register (PCTL) to disable unnecessary clock signals and avoid unnecessary on-board radio frequency emissions.
MOTOROLA
2-9
DSP56301ADM Technical Summary Clock Source Selection
2.5.1
On-Board Clock Generator Selection
The clock generator is socketed to allow easy replacement with different frequency clock generators. The board is supplied with a 33 MHz clock generator. The PCB layout is designed so that either a 14-pin DIP packages or an 8-pin DIP packages may be accepted. The clock generator should be placed in the socket as shown in Figure 2-6. To select the on-board clock generator, JP13 should not be jumpered, and JP14 should be jumpered from pin 2 to pin 5. The DSP56301ADM comes with aDIP14 package 33 MHz clock generator.
14 13 12 11 8 10 7 9 6 8 5
Note:
DIP14 PACKAGE
Pin 8 of 14-pin socket or Pin 5 of the 8-pin socket is clock out.
DIP8 PACKAGE 1 1 2 3 4 2 5 3 6 4 U15 socket 7
Figure 2-6 3.3 V Clock Generator Assembly
2.5.2
External Clock Selection
To support non-standard clock rates and frequency fine tuning, the DSP56301ADM provides a 50 impedance, DC-coupled, BNC connector for a 3.3 V clock input. To select the external clock generator, JP13 should not be jumpered, and JP14 should be jumpered from pin 3 to pin 4. Note: For proper operation, the external clock must have rise/fall times < 3 ns.
2.5.3
Crystal Oscillator Selection
By using a low-frequency crystal oscillator, the user can reduce external high frequency emissions, while still allowing the the DSP56301 to run at higher operating frequencies generated by the on-chip PLL. The crystal must have bypass capacitors at both ends. When the crystal oscillator is used, the user should install appropriately rated components C32,C33,R16,R17 and Y1 (See the DSP56301 Technical Data sheet for more information). To enable the on-board crystal oscillator, place a jumper on JP13 and another jumper across pins 16 on JP14. Note: Power should be turned off prior to inserting/removing the crystal oscillator.
2-10
MOTOROLA
DSP56301ADM Technical Summary Host Port Selection
2.5.4
DSP56301 PLL Enable/Disable On Reset
The DSP56301 samples the PINIT/NMI line on exit from the reset state to determine whether the PLL should be enabled or disabled. To enable the PLL, JP12 should be jumpered. To disable the PLL, JP12 pins 1-2 should be jumpered.
RESET QS3244SO (2 to 1 MUX) NMI Requests 1 To DSP56301
PLL INIT jumper 0
Figure 2-7 PLL Mode Selection After the RESET line is deasserted the PINIT/NMI signal is connected to the NMI signal. Note: The ADM is factory configured for PLL enabled (JP12 removed).
2.6
HOST PORT SELECTION
The DSP56301s HI32 port directly supports a PCI bus interface. Connection to an ISA bus interface requires the addition of external buffers. The DSP56301ADM supports application development for either bus by providing both a PCI edge connector and an ISA edge connector (with the appropriate buffers). When the DSP56301ADM is used with ISA host, place a jumper across JP4, JP5, JP6, and JP7 with the components U16, U17, U18, U19, U20, RN1, and RN2 mounted in their sockets. When the ADM is used in PCI host or as a stand-alone device, there should be no jumpers on JP4, JP5, JP6, and JP7 and the components in U16, U17, U18, U19, U20, RN1, and RN2 should be removed. Note: The ADM is factory configured for ISA Host Mode.
MOTOROLA
2-11
DSP56301ADM Technical Summary ISA DMA and Interrupt Channels
2.7
ISA DMA AND INTERRUPT CHANNELS
The ADM enables the user to configure one of four channels for DMA and one of four interrupt channels for an ISA bus interface. Table 2-3 and Table 2-4 describe these configurations options. Table 2-3 ISA Bus DMA Channel Configuration
DMA Channel 0 5 6 7 JP8 None None 36, 45 18, 27 JP10 18, 27 36, 45 None None
Table 2-4 ISA Bus Interrupt Selection

Interrupt 5 6 7 10 JP11 36 27 18 45
2-12
MOTOROLA
DSP56301ADM Technical Summary Connectors
2.8
CONNECTORS
The DSP56301ADM includes the following connectors: Expansion and Logic-Analyzer connectorfour 2 25-pin SMD pin-rows Power2-pin terminal block, two-part HI32 portISA and PCI edge connectors SSI I/FTwo connectors: 2 7 and 2 15 SMD pin-rows JTAGE/OnCE port connector2 7 SMD pin-rows
2.8.1
Expansion And Logic Analyzer Connectors
The DSP56301ADM has a set of four dual-in-line 50-pin SMD pin rows connectors to support both hardware expansion and logic-analyzer connection. These connectors are connected to all the pins of the DSP56301 chip except for the PCAP, XTAL, EXTAL, MODA, MODB, MODC, and PINIT. All the other DSP56301 pins are routed to these connectors along with +3.3 V and GND pins. The power and ground pins facilitate hardware expansions powered by the DSP56301ADM. Figure 2-8 on page 2-14, Figure 2-9 on page 2-15, Figure 2-10 on page 2-16, and Figure 2-11 on page 2-17 show the pinouts for these connectors.
MOTOROLA
2-13
BCLK V3.3 CLKOUT CAS NMI V3.3 GND BB BR GND AA3 RD V3.3 GND A0 GND A1 A2 GND A3 A4 GND A5 A6 A7
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
AA1 GND AA0 TA RESET V3.3 GND BG V3.3 AA2 WR GND V3.3 SPARE2 A8 V3.3 A9 A10 V3.3 A11 A12 V3.3 A13 A14 A15
Figure 2-8 Expansion Connector (P10)
2-14
MOTOROLA
IRQB D22 D21 GND D18 D16 D15 GND D12 D10 D9 GND GND D6 D4 D3 GND D0 A22 V3.3 A20 A18 V3.3 A16 GND
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
IRQA D23 V3.3 D20 D19 D17 V3.3 D14 D13 D11 V3.3 V3.3 D8 D7 D5 V3.3 D2 D1 A23 V3.3 A21 A19 V3.3 A17 GND
MOTOROLA
2-15
GND BL STD0 TDI TMS
1 3 5 7 9
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
GND BS SC10 TCK TDO DEZ TRST V3.3 SRD1 SCK1 STD1 SC01 GND SPARE1 V3.3 RXD TIO1 HAD0 HAD2 V3.3 HAD4 HAD6 HC0 HAD9 HAD11
SC20 11 SC00 13 GND 15 SCK0 17 SRD0 19 SC21 21 SC11 23 TXD 25 V3.3 27 GND 29 SCLK 31 TIO0 33 TIO2 35 HAD1 37 HAD3 39 GND 41 HAD5 43 HAD7 45 HAD8 47 HAD10 49
2-16
MOTOROLA
V3.3 HAD12 HAD14 HRST HCLK
1 3 5 7 9
2 4 6 8
GND HAD13 HAD15 HC1
10 HAEN 12 HPAR 14 GND 16 HWR 18 HDRQ 20 HDEVSEL 22 V3.3 24 HFRAME 26 V3.3 28 HRD 30 HAD16 32 HAD17 34 GND 36 HAD20 38 HAD22 40 HC3 42 HAD25 44 HAD27 46 HAD29 48 HAD31 50 IRQC
HREQ 11 V3.3 13 HIRQ 15 HLOCK 17 PVCL 19 GND 21 HTRDY 23 GND 25 HIRDY 27 HC2 29 HAD18 31 HAD19 33 V3.3 35 HAD21 37 HAD23 39 HAD24 41 HAD26 43 HAD28 45 HAD30 47 IRQD 49
MOTOROLA
2-17
2.8.2
5 V Power Connector
The 5 V power connector to the DSP56301ADM is a 2-lead terminal block next to the power switch SW1. The power connector and power switch are only used for stand-alone operation; the power switch SW1 is used to turn the ADM on or off.
2.8.3
HI32 Connector
There are two HI32 connectors on the DSP56301ADM: 1. PCI edge connector, configured as 32-bit universal (5 V & 3.3 V) connector 2. ISA edge connector These connectors are located on opposite sides of the DSP56301ADM, enabling it to operate using an ISA, EISA, or PCI bus interface. The PCI edge connector is keyed with both 5 V and 3.3 V keys to permit operation with either 5 V or 3.3 V PCI-backplanes.
2-18
MOTOROLA
2.8.4
SSI Port Connectors
The SSI port pins appear on three different connectors: The Expansion & Logic-Analyzer connectors Two dedicated SSI port connectors DSP56004 Audio Interface Bus (AIB) compatible connector The SSI pins are multiplexed to these connectors to permit connection of the SSI pins to various applications. The dedicated general purpose connectors are for general purpose use to be connected via a ribbon cable to another board. To avoid crosstalk and supply concurrent impedance path for the ongoing signals, GND lines are inserted between the signal lines. To avoid incorrect insertion of the receptacle connector, keying is provided as pin 13 is cut while its corresponding hole in the receptacle connector is filled. The pinout of the independent SSI connector is shown in Figure 2-12
SRD1 STD1 SC01 SC11 SC21
1 3 5 7 9
2 4 6 8
GND GND GND GND
10 GND 12 GND 14 GND
SCK1 11 KEY 13
Figure 2-12 Dedicated SSI Connector (P3) The AIB interface connector is meant to support the DSP56004 Audio Interface Board (AIB), a high-quality audio board with two stereo 18-bit ADCs and three stereo 18-bit DACs, originally designed to for the DSP56004. The pinout of the SSI-AIB connector is shown in Figure 2-13 on page 2-20. In the figure, the leftmost column contains the AIB connector signal names, while the next column contains the DSP56301 signal names. The DSP56301ADM supports one stereo output channel and one stereo input channel when connected to the AIB.
MOTOROLA
2-19
AIB Function GPIO0 GPIO1 GPIO2 GPIO3 SDI0 SDI1 RBICK RLRCK SDO0 SDO1 SDO2 TBICK TLRCK RESET GND This connector is not on ADM
SRD1 STD1 SC01 SC11 SRD0 N.C. SC00 SC10 STD0 N.C N.C SCK0 SC20 RESET GND
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Figure 2-13 SSI - AIB Connector (P2)
2.8.5
SCI Port Connector
The SCI port pins are routed to two connectors: The Expansion & Logic-Analyzer connectors Dedicated SCI port connector Routing to the expansion Logic-Analyzer connectors is done to support expansion boards and application debugging. The dedicated connector attaches to an application board via a ribbon cable. To avoid incorrect insertion of the plug into the receptacle, keying is provided via pin 6, which is cut, while its corresponding hole in the receptacle connector is filled.
2-20
MOTOROLA
The pinout of the SCI dedicated connector is shown in Figure 2-14.
TXD SCLK RXD
1 3 5
2 4 6
GND GND KEY
Figure 2-14 SCI Dedicated Connector (P6)
2.8.6
JTAG/OnCE Connector
The JTAG/OnCE connector is used both for JTAG testing during production, and for OnCE functions for code debugging and software development.The pinout of the JTAG/OnCE dedicated connector is shown in Figure 2-15.
TDI TDO TCK DR ORESET
1 3 5 7 9
2 GND 4 GND 6 GND 8 KEY 10 TMS 12 TMS1 14 TRST
VDD 11 DEZ 13
Figure 2-15 JTAG/OnCE Connector (P4)
MOTOROLA
2-21
2-22
MOTOROLA
APPENDIX A DSP56301ADM SCHEMATICS
MOTOROLA
DSP56301ADMUM/AD
A-1
DSP56301ADM Schematics
A-2
DSP56301ADMUM/AD
MOTOROLA
8 A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> A<17> A<18> A<19> A<20> A<21> A<22> A<23>
U12 29 30 33 34 35 36 39 40 41 42 45 46 47 48 51 52 55 56 59 60 61 62 65 66
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> A<17> A<18> A<19> A<20> A<21> A<22> A<23>
AA0_RAS0* AA1_RAS1* AA2_RAS2* AA3_RAS3* 101 102 105 106 IRQA* IRQB* IRQC* IRQD*
1 2 20 21 AA0 AA1 AA2 AA3
HINTA SPARE2
D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> D<8> D<9> D<10> D<11> D<12> D<13> D<14> D<15> D<16> D<17> D<18> D<19> D<20> D<21> D<22> D<23>
67 68 69 72 73 74 75 76 77 82 83 84 85 86 87 90 91 92 93 94 95 98 99 100
D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> D<8> D<9> D<10> D<11> D<12> D<13> D<14> D<15> D<16> D<17> D<18> D<19> D<20> D<21> D<22> D<23>
DSP56301ADMUM/AD
JTAG
HC<0> HC<1> HC<2> HC<3> PORT D
163 150 128 117
HAD<0> HAD<1> HAD<2> HAD<3> HAD<4> HAD<5> HAD<6> HAD<7> HAD<8> HAD<9> HAD<10> HAD<11> HAD<12> HAD<13> HAD<14> HAD<15> HAD<16> HAD<17> HAD<18> HAD<19> HAD<20> HAD<21> HAD<22> HAD<23> HAD<24> HAD<25> HAD<26> HAD<27> HAD<28> HAD<29> HAD<30> HAD<31> HC<0>_HBE0* HC<1>_HBE1* HC<2>_HBE2* HC<3>_HBE3* IRQA*_MODA IRQB*_MODB IRQC*_MODC IRQD*_MODD 1 1 R12 1K 2 GND R11 1K 2 GND WR* RD* CAS* TA* BR* BG* BB* BL* BS* DE* TRST* TCK TDI TDO TMS DE* TRST* TCK TDI TDO TMS 199 204 201 202 203 200 22 23 7 8 17 16 15 206 205 WR* RD* CAS* TA* BR* BG* BB* BL* BS* RN3 4.7K
SC10 SC11 SC12 STD1 SRD1 SCK1 PORT E TXD RXD SCLK TIO0 TIO1 TIO2
187 186 185 188 190 189 184 177 178 176 175 174
SC10 SC11 SC12 STD1 SRD1 SCK1 TXD RXD SCLK TIO0 TIO1 TIO2
RD* WR* AA2 AA3 BB* DE* TDI TMS TCK AA1 AA0 IRQD* N/C PORT C SC00 SC01 SC02 STD0 SRD0 SCK0 SC00 SC01 SC02 STD0 SRD0 SCK0
1 2 3 4 5 6 7 8 9 10 11 12 13
1 V3.3 1 PINIT_NMI* RESET* PCAP 10 9 12 PINIT RESET* 2 DRAWING LAST_MODIFIED=Fri Jun 16 15:08:23 1995 TITLE: DSP56301ADS DATE: CPU CONNECTIONS PAGE: 1 OF 12 C25 390PF 2 GND A R20 1K
PVCL HTRDY* HIRDY* HDEVSEL* HLOCK HPAR HDRQ HAEN HREQ* HIRQ HWR* HRD* HFRAME* HCLK HRST PVCL HTRDY*_HDBEN* HIRDY*_HDBDR* HDEVSEL*_HSAK* HLOCK*_HBS* HPARHDAK* HPERR*_HDRQ HGNT*_HAEN HREQ*_HTA* HSERR*_HIRQ HSTOP*_HWR* HIDSEL_HRD* HFRAME* HCLK HRST*_HRST
137 134 133 138 140 145 141 149 146 142 139 129 130 148 147
BCLK CLKOUT EXTAL XTAL
6 5 26 24
BCLK CLKOUT EXTAL XTAL
HINTA SPARE2
181 28
RES14COM
MOTOROLA
DSP56301
196 197 198 195 191 192
HAD<0> HAD<1> HAD<2> HAD<3> HAD<4> HAD<5> HAD<6> HAD<7> HAD<8> HAD<9> HAD<10> HAD<11> HAD<12> HAD<13> HAD<14> HAD<15> HAD<16> HAD<17> HAD<18> HAD<19> HAD<20> HAD<21> HAD<22> HAD<23> HAD <24> HAD <25> HAD <26> HAD <27> HAD <28> HAD <29> HAD <30> HAD <31>
173 172 171 170 167 166 165 164 162 161 160 159 154 153 152 151 127 126 125 124 121 120 119 118 116 115 114 113 110 109 108 107
14 V3.3
A-3
8 RN4 1K 1 SW2 U14 V3.3
RES10COM
A-4
GND RESET
1 1G* 2A1 2A2 2A3 2A4 2G* 2Y1 2Y2 2Y3 2Y4 9 7 5 3 MODA MODB MODC 11 13 15 17 19
D
INTRA* INTRB* INTRC* NMI* 2 4 6 8 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 18 16 14 12
RESET RESETP MODC MODB MODA INTRA* INTRB* INTRC* NMI* 2 3 4 5 6 7 8 9 10 1 2 3 4 8 7 6 5 26P MODA MODB MODC V3.3 U13 LS05 9 8 V3.3 1 R21 1K 2 RESET* 1 R14 1K Q2 S-8053HNB 2 IN OUT VSS C31 4.7UF 3 V3.3 GND 1 R16 XTLCLK 1 1MEG R17 2 XTALIN 1 1 C32 33PF 2 GND GENCLK C33 2 GND 100 1 2 33PF GND Y1 27MHZ JP12 12 JPINIT 2 EXTALIN R13 1K 2 1 R15 1K 2 U13 LS05 13 12 RESETP U13 LS05 11 10
IRQA* IRQB* IRQC*
PINIT
V3.3
V3.3
QS3244SO
D11
1N4148
C RESET SW. SPST 1
SW3
GND
GND
JP13
XTAL
DSP56301ADMUM/AD
JP14 6 1 2 5 3 4 EXTAL R19 EXTCLK GND 1 51 2 CLKTERM 1 0.1UF TITLE: C52 2 GND DRAWING 7 6 5 4 3
21
ACCEPTS 8 PIN DIP AND 14 PIN DIP PACKAGES
U15 33MHZ
OUT
P13
BNC
MOTOROLA
LAST_MODIFIED=Fri Jun 16 15:11:04 1995 DSP56301ADS CLOCK AND INIT MODE SELECT DATE: REV 1.1 PAGE: 2 OF 12 2 1
D U4 U3
U2
MOTOROLA
O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 BD<0> BD<1> BD<2> BD<3> BD<4> BD<5> BD<6> BD<7> 11 12 13 15 16 17 18 19 BD<8> BD<9> BD<10> BD<11> BD<12> BD<13> BD<14> BD<15> BD<16> BD<17> BD<18> BD<19> BD<20> BD<21> BD<22> BD<23> 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 MCM6706AJ MCM6706AJ MCM6706AJ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 OE* CS* WE* RD* SRAM_CS WR* 22 20 27 OE* CS* WE* RD* SRAM_CS WR* 22 20 27 OE* CS* WE* D10 D9 2 GND 1 2 0.1UF 1N4001 VCC VU22 1 2 VU21 1 0.1UF 2 C14 C13 GND VCC 1 2 1N4001 20 20 18 17 16 15 14 13 12 11 BD<0> BD<1> BD<2> BD<3> BD<4> BD<5> BD<6> BD<7> GND 19 D<8> D<9> D<10> D<11> D<12> D<13> D<14> D<15> 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 G* QS3245SO U6 DRAWING TITLE: B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 BD<8> BD<9> BD<10> BD<11> BD<12> BD<13> BD<14> BD<15> D<16> D<17> D<18> D<19> D<20> D<21> D<22> D<23> GND 2 3 4 5 6 7 8 9 19 A1 A2 A3 A4 A5 A6 A7 A8 G* QS3245SO U5 B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 BD<16> BD<17> BD<18> BD<19> BD<20> BD<21> BD<22> BD<23> 0.1UF D8 VU23 1 C12 2 GND 20 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 G* QS3245SO U7 19 7 6 5 4 3 2
AA0
JP1
1 2
V3.3
R8 10K
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14>
SRAM_CS
RD*
22 20 WR* 27
VCC
DSP56301ADMUM/AD
1N4001
D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7>
GND
LAST_MODIFIED=Fri Jun 16 15:07:43 1995 DATE: DSP56301ADS REV 1.1 SRAM CONNECTIONS + 5V <-> 3V BUF PAGE: 3 OF 12 1
A-5
A-6
D U11 U10 U9 A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> 10 11 12 13 16 17 18 19 20 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 MCM54800AJ MCM54800AJ MCM54800AJ D0 D1 D2 D3 D4 D5 D6 D7 A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 D5 D6 D7 A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 D5 D6 D7 BD<8> BD<9> BD<10> BD<11> BD<12> BD<13> BD<14> BD<15> 2 3 4 5 24 25 26 27 BD<0> BD<1> BD<2> BD<3> BD<4> BD<5> BD<6> BD<7> 10 11 12 13 16 17 18 19 20 9 2 3 4 5 24 25 26 27 10 11 12 13 16 17 18 19 20 9 2 3 4 5 24 25 26 27 BD<16> BD<17> BD<18> BD<19> BD<20> BD<21> BD<22> BD<23> C CAS* CAS* RD* WR* CAS* RAS* OE* WE* RD* WR* CAS* RAS* OE* WE* 23 8 22 7 23 8 22 7 CAS* RD* WR* 23 8 22 7 CAS* RAS* OE* WE* B DRAMCS A DRAWING LAST_MODIFIED=Fri Jun 16 15:07:22 1995 TITLE: DSP56301ADS DRAM MEMORY DATE: REV 1.1 PAGE: 4 OF 12 7 6 5 4 3 2 1
DSP56301ADMUM/AD
JP2
AA3
MOTOROLA
MOTOROLA
U8 O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21 D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 AT29LV512J 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 JP3 1 2 FL_CS WR* RD* WE* OE* CS* 31 24 22 V3.3 R10 10K DRAWING TITLE: DSP56301ADS FLASH MEMORY 7 6 5 4 3 2
AA1
DSP56301ADMUM/AD
LAST_MODIFIED=Fri Jun 16 15:06:54 1995 DATE: REV 1.1 PAGE: 5 OF 12 1
A-7
8 U19
SA<1> SA<2> SA<3> SA<4> 2 4 6 8 1 2A1 2A2 2A3 2A4 2G* 2Y1 2Y2 2Y3 2Y4 9 7 5 3 HAD<1> HAD<2> HAD<3> HAD<4> 1G* 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 18 16 14 12 HC<0> HC<1> HC<2> HAD<0> ISA_EN1 SA<5> SA<6> SA<7> SA<8> ISA_EN1 11 13 15 17 19
HCLK HIRQ HLOCK* HDEVSEL* HFRAME* U18 JP7 HDBDR 1

ISA_EN4 SD<0> SD<1> SD<2> SD<3> SD<4> SD<5> SD<6> SD<7> 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 1 19 DIR G*
2 3 4 5 6 7 8 9 1 VCC RES9COM
B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11
NRST ISA_EN3 ISA_EN4 ISA_EN1 ISA_EN2 IRQ NIRQ IIRQ
2 3 4 5 6 7 8 9
HAD<8> HAD<9> HAD<10> HAD<11> HAD<12> HAD<13> HAD<14> HAD<15>
RN2 1K 1 GND
HIRDY*
ISA_EN3
A
SD<8> SD<9> SD<10> SD<11> SD<12> SD<13> SD<14> SD<15> 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8
RES9COM
74HCT245 U17
B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 HAD<16> HAD<17> HAD<18> HAD<19> HAD<20> HAD<21> HAD<22> HAD<23>
RES9COM
A-8
GND 74HCT244 U16
SA<9> GND SA<0> SBHE* HAD<5> HAD<6> HAD<7> HWR* HRD* 2 4 6 8 1A1 1A2 1A3 1A4 1G* 1Y1 1Y2 1Y3 1Y4 1 18 16 14 12 ISA_EN1 IOWC IORC DACK*
D JP4 1 2
RSTDRV
HRST ISA_EN1 2G*
U13 LS05 5 6 NRST

11 13 15 17 19 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 9 7 5 3
HDAK* HPAR
C MAX_DELAY=10000 74HCT244 U20

HAEN GRQ IIRQ
VCC U13 LS05 1 2 1 R18 10K

ISA_EN1 1G* CHRDY IO16* 1 AEN HDRQ GND HIRQ 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2 4 6 8 18 16 14 12
U13 NIRQ LS05 3 4 MAX_DELAY=10000 RN5 10K 1 VCC B IRQ
2 HREQ* JP5 1 2
ISA_EN2 2G* GND GND 2A1 2A2 2A3 2A4 GND 2Y1 2Y2 2Y3 2Y4 9 7 5 3
HTA
11 13 15 17 19
MAX_DELAY=10000
HDEVSEL* 74HCT244
HSACK
DSP56301ADMUM/AD
HAD<24> HAD<26> HAD<28> HAD<30> HAD<25> HAD<27> HAD<29> HAD<31> HDBEN* JP6 1 2 ISA_EN4
ISA_EN3 1 19
RN1 10K
2 3 4 5 6 7 8 9
DRAWING
DIR G*
MOTOROLA
7 6
LAST_MODIFIED=Fri Jun 16 15:12:11 1995 DATE: 74HCT245 REV 1.1 PAGE: 6 OF 12 5 4 3 2 1 TITLE: DSP56301ADS ISA/EISA BUS BUFFERS
HTRDY*
P11 ISA-CON1 SD<7> SD<6> SD<5> SD<4> SD<3> SD<2> SD<1> SD<0> CHDRY AEN IOWC IORC C GND RSTDRV VCC D
MOTOROLA
JP11 IRQ7 IRQ6 IRQ5 1 2 3 4 5 8 7 6 IRQ SA<9> SA<8> SA<7> SA<6> SA<5> SA<4> SA<3> SA<2> SA<1> SA<0> IOCHK* SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOREADY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 ISAGND1 ISARESET +5VA IRQ9 -5V DRQ2 -12V NOW* +12V ISAGND2 MEMER* MEMRD* IOWR* IORD* DACK3* DRQ3 DACK1* DRQ1 REFRESH* SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK* T/C BALE +5VB OSC ISAGND3 JP10 1 2 3 4 8 7 6 5 DACK* DRQ B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 P8 ISA-CON2 SBHE* IO16* IRQ10 JP8 4 3 2 1 DACK0* DRQ0 DACK5* DRQ5 DACK6* DRQ6 DACK7* DRQ7 VCC GND 5 6 7 8 SD<8> SD<9> SD<10> SD<11> SD<12> SD<13> SD<14> SD<15> C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 SBHE* LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMRD* MEMWR* D<8> D<9> D<10> D<11> D<12> D<13> D<14> D<15> M16* IO16* IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0* DRQ0 DACK5* DRQ5 DACK6* DRQ6 DACK7* DRQ7 +5V MASTER* ISAGND D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 7 6 5 4 3 2
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
DSP56301ADMUM/AD
DRAWING LAST_MODIFIED=Fri Jun 16 15:05:53 1995 TITLE: DSP56301ADS DATE: REV 1.1 ISA BUS CONNECTORS
A-9
PAGE: 7 OF 12 1
8 P9 PCI-CON JP9 VCC VCC V3.3 IOVCC HRST* HRST HAEN HGNT HAD<30> HAD<28> HAD<26> HAD<24> HAD<22> HAD<20> HAD<18> HAD<16> HFRAME* HTRDY* HSTOP HWR* HIOSEL HRD* 1 2 3
A-10
GND VCC 1B 2B 3B 4B 5B 6B 7B 8B 9B -12V TCK GROUNDP TDO +5VE +5VF INTB* INTD* PRSNT1* TRST* +12V TMS TDI +5VA INTA* INTL* +5VB +VI/OA PVCL PRSNT2* 11B 1A 2A 3A 4A 5A 6A 7A 8A 10A HPAR HAD<15> HAD<13> HAD<11> HAD<9> RST* +VI/OB GNT* GROUNDA AD30 +3.3VA AD28 AD26 GROUNDB AD24 IDSEL +3.3VB AD22 AD20 GROUNDC AD18 AD16 +3.3VC FRAME* GROUNDD TRDY* GROUND STOP* +3.3VD SDONE SBO* GROUNDE PAR AD15 +3.3VE AD13 AD11 GROUNDF AD9 15A 16A 17A 18A 20A 21A 22A 23A 24A 25A 26A 27A 28A 29A 30A 31A 32A 33A 34A 35A 36A 37A 38A 39A 40A 41A 42A 43A 44A 45A 46A 47A 48A 49A HC<0> HAD<6> HAD<4> GND HAD<2> HAD<0> DRAWING LAST_MODIFIED=Fri Jun 16 15:05:14 1995 TITLE: PCI CONNECTOR DSP56301 ADS DATE: REV 1.1 15B 16B 17B 18B 19B 20B 21B 22B 23B 24B 25B 26B 27B 28B 29B 30B 31B 32B 33B 34B 35B 36B 37B 38B 39B 40B 41B 42B 43B 44B 45B 46B 47B 48B 49B 52B 53B 54B 55B 56B 57B 58B 59B 60B 61B 62B GROUNDQ CLK GROUNDR REQ* +VI/OG AD31 AD29 GROUNDS AD27 AD25 +3.3VG C/BE3* AD23 GROUNDT AD21 AD19 +3.3VH AD17 C/BE2* GROUNDU IRDY* +3.3VI DEVSEL* GROUNDV LOCK* PERR* +3.3VJ SERR* +3.3VK C/BE1* AD14 GROUNDW AD12 AD10 GROUNDX AD8 AD7 +3.3VL AD5 AD3 GROUNDY AD1 +VI/OH ACK64* +5VG +5VH C/BE0* +3.3VF AD6 AD4 GROUNDG AD2 AD0 +VI/OC REQ64* +5VC +5VD 52A 53A 54A 55A 56A 57A 58A 59A 60A 61A 62A 7 6 5 4 3 2 PAGE: 8 OF 12 1
HCLK
HREQ* IOVCC
HAD<31> HAD<29>
HAD<27> HAD<25>
HC <3>
HAD<23>
HAD<21> HAD<19>
HAD<17>
HC<2>
DSP56301ADMUM/AD
HIRDY*
HDEVSEL*
HLOCK* HDRQ
HIRQ
HC<1>
HAD<14>
HAD<12> HAD<10>
HAD<8> HAD<7>
HAD<5> HAD<3>
MOTOROLA
HAD<1>
P4
D KEY0 TMS TMS1 TRST*
JTAG D
TDI TDO TCK DR* RESET* V3.3 DE*
1 3 5 7 9 11 13
2 4 6 8 10 12 14
MOTOROLA
P6 TXD 1 SCLK RXD 5 KEY2 6 3 4 SCI 2 P3 SRD1 1 2 4 6 8 10 12 14 SSI 3 5 7 9 11 KEY3 13 STD1 SC01 SC11 SC12 SCK1 P2 SRD0 N/C SD11 SC00 SC10 STD0 N/C SD01 N/C SD02 SCK0 SC02 RESET* SSI-AIB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 GND DRAWING TITLE: DSP56301ADS SSI-AIB AND SCI CONNECTIONS 7 6 5 4 3 2
DSP56301ADMUM/AD
LAST_MODIFIED=Fri Jun 16 15:04:50 1995 DATE: REV 1.1 PAGE: 1 9 OF 12
A-11
A-12
D PINS 55 TO 102 P7 P5 PINS 105 TO 156 PINS 159 TO 206 C 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 AA1 GND AA0 TA* RESET* V3.3 GND BG* V3.3 AA2 WR* GND V3.3 SPARE2 A<8> V3.3 A<9> A<10> V3.3 A<11> A<12> V3.3 A<13> A<14> A<15> INTRA* D<23> V3.3 D<20> D<19> D<17> V3.3 D<14> D<13> D<11> V3.3 V3.3 D<8> D<7> D<5> V3.3 D<2> D<1> A<23> V3.3 A<21> A<19> V3.3 A<17> GND V3.3 HAD<12> HAD<14> HRST HCLK HREQ* V3.3 HIRQ HLOCK* PVCL GND HTRDY* GND HIRDY* HC<2> HAD<18> HAD<19> V3.3 HAD<21> HAD<23> HAD<24> HAD<26> HAD<28> HAD<30> IRQD* GND HAD<13> HAD<15> HC<1> HAEN HPAR GND HWR* HDRQ HDEVSEL* V3.3 HFRAME* V3.3 HRD* HAD<16> HAD<17> GND HAD<20> HAD<22> HC<3> HAD<25> HAD<27> HAD<29> HAD<31> INTRC* GND BL* STD0 TDI TMS SC02 SC00 GND SCK0 SRD0 SC12 SC11 TXD V3.3 GND SCLK TIO0 TIO2 HAD<1> HAD<3> GND HAD<5> HAD<7> HAD<8> HAD<10> INTRB* D<22> D<21> GND D<18> D<16> D<15> GND D<12> D<10> D<9> GND GND D<6> D<4> D<3> GND D<0> A<22> V3.3 A<20> A<18> V3.3 A<16> GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 P12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GND BS* SC01 TCK TDO DEZ* TRST* V3.3 SRD1 SCK1 STD1 SC10 GND SPARE1 V3.3 RXD TIO1 HAD<0> HAD<2> V3.3 HAD<4> HAD<6> HC<0> HAD<9> HAD<11> B A DRAWING LAST_MODIFIED=Fri Jun 16 15:04:26 1995 TITLE:DSP56301ADS DATE: EXPANSION CONNECTIONS REV 1.1 PAGE: 10 OF 12 7 6 5 4 3 2 1
PINS 1 TO 52
P10
DSP56301ADMUM/AD
BCLK V3.3 CLKOUT CAS* NMI* V3.3 GND BB* BR* GND AA3 RD* V3.3 GND A<0> GND A<1> A<2> GND A<3> A<4> GND A<5> A<6> A<7>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
MOTOROLA
D VCC F1 2 2A MBRD620CT 1 C2 2 0.1UF 1 2 GND GND C3 470UF 1 2 GND GND GND 3 + 1 4 D7
SW1
MOTOROLA
R1 0.1 LT1085CT 3 IN V3.3 1 R6 150 GND 2 1 GREEN R2 0.1 OUT2 REF 1 2 LD2 1 C6 470UF + C7 470UF 2 1 + 1 C1 0.1UF 2 GND 2 GND GND GND DRAWING TITLE: DSP56301ADS POWER SUPPLY REGULATOR 7 6 5 4 3 2
PWR3 VSW 2 1 2 3 GND
1 VIN 1
P1
D6 ZENER 1SMC5.0AT3
1 R5 330 2 1 GREEN
2 LD1 GND
DSP56301ADMUM/AD
LAST_MODIFIED=Mon Jun 19 17:36:38 1995 DATE: REV 1.1 PAGE: 1 11 OF 12
A-13
8 DRAM 1 C10 2 0.1UF 2 2 0.1UF 2 0.1UF C11 C27 1 1 1 1 1 1 1 1 1 VCC SRAM 32K X 8 CLOCK GENERATOR V3.3
FLASH
A-14
GND DSP56301 POWER PINS V3.3 HI32 CLAMP PIN PVCL 1 1 1 1 1 1 1 1 1 GND VCC MODE SELECT IOVCC 1 1 C50 2 0.1UF 2 PCI CONNECTOR C28 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF C30 C37 C47 1 1 1 1 I/O SUPPLY PINS GND VCC ISA BUFFERS 1 1 C34 2 0.1UF 2 0.1UF C51 C40 2 0.1UF 1 C29 2 0.1UF 2 0.1UF C35 1 1 C42 2 0.1UF 2 1 ISA CONNECTOR AND BUFFERS 1 GND DRAWING TITLE: LAST_MODIFIED=Fri Jun 16 15:04:02 1995 DATE: DSP56301ADS REV 1.1 DECOUPLING CAPACITORS PAGE: 12 OF 12 7 6 5 4 3 2 1
V3.3
C15 C18 C17 C16 C21 C20 C19 C9 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF
C48 C41 C38 C39 C43 C46 C44 C45 C49 C23 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2 0.1UF 2
5V PINS
C22
C24
DSP56301ADMUM/AD
0.1UF
2 0.1UF
ISA CONNECTOR
MOTOROLA
C26 0.1UF
C36
2 0.1UF
APPENDIX B DSP56301ADM BILL OF MATERIALS
MOTOROLA
B-1
DSP56301ADM Bill of Materials
B-2
MOTOROLA
B.1
DSP56301ADMELECTRICAL PARTS LIST REV. 2.13/15/95

Description Ref. Designators Integrated Circuits Vendor Part #
Qty
3 3 1 3 1 1 1 1 3 2 1
MCM6706AJ-12 QS3245SO AT29LV512-20J MCM54800AJ-70 DSP56301 MC74LS05N QS3244SO A53AA-33MHz MC74HCT244AN MC74HCT245AN 27 MHz
U2, U3, U4 U5, U6, U7 U8 U9, U10, U11 U12 U13 U14 U15 U16, U19, U20 U17, U18 Crystal Y1
Motorola,IDT Quality Semiconductor Atmel Motorola, Toshiba Motorola Quality Semiconductor Connor-Winfield Motorola Motorola International Crystal #436161-27.00., FOX #HC94U-27.00MHz 30/50/20/10 Fundamental Frequency at Cut Crystal. 1/4 W through hole Bourns CR12061302JVCA Bourns CR12062002JVCA Bourns CR12063300JVCA Bourns CR12061500JVCA Bourns CR12061002JVCA Bourns CR12061001JVCA Bourns CR12061004JVCA Bourns CR12061000JVCA Bourns CR120651R0JVCA
Resistors 2 1 1 1 1 5 7 1 1 1 0.1 13 K 20 K 330 150 10 K 1 K 1 M 100 51 R1, R2 R3 R4 R5 R6 R8, R9, R10, R18 R11, R12, R13, R14, R15, R20, R21 R16 R17 R19
MOTOROLA
B-3
Qty
Description
Ref. Designators Resistor Networks
Vendor Part #
3 1 1 1 1 1
10 K 4.7 K 1 K LT1085CT-3.3/3A S-8053HNB 2A
RN1, RN2, RN5 RN3 RN4 Transistors Q1 Q2 Fuse / Fuse Holder F1 LEDs
Bourns 4609X-101-103 Bourns 4814P-002-472 Bourns 4610X-101-102 Linear Seiko Wickman 19197 2A Fast Blow Holder 19646 Hewlett Packard HSMG-C650 Motorola MBRD620CT Motorola 1N4001 Micro-Semi 1N914 Motorola 1SMC5.0AT3 Murata Erie GRM42-6X7R104M25BB Sprague 501D477M016MM Murata Erie GRM42-6X7R391M50BB Murata Erie GRM42-6COG330M50BB
2 2 7 1 1 43 3 1 2
Green LED Rectifier Rectifier Rectifier Rectifier 0.1 F 470 F 390 pF 33 pF
LD1,LD2 Diodes D7 D8,9,10 D11 D6 Capacitors C1, C2, C9C24, C26C31, C35C52 C3, C6, C7 C25 C32, C33
B-4
MOTOROLA
B.2
DSP56301 ADMHARDWARE PARTS LIST REV. 2.13/15/95

Description 1 2 Bergstik 8-pin Connector 1 3 Bergstik 6-pin Connector 32-pin PLCC 14-pin DIP 20-pin DIP 3-position Power 1 9 Mach Strip 1 10 Mach Strip 2-position Terminal Block 30-pin Connector 14-pin Connector 20-pin Connector 6-pin Connector BNC Toggle DIP Momentary Pushbutton Cup Miscellaneous 4 1 1 RUBBER FEET 4-40 SCREW 4-40 NUT Located on Q1 Located on Q1 Amatom #5186 Ref. Designator Jumpers 9 3 1 1 1 1 5 1 3 1 1 5 2 4 1 1 1 1 1 1 JP1JP7, JP12, JP13 JP8, JP10, JP11 JP9 JP14 Sockets U8 U15 U16U20 P1 RN1, RN2, RN5 RN4 Connectors P1 P2, P5, P7, P10, P12 P3, P4 P5, P7, P10, P12 P6 P13 Switches SW1 SW2 SW3 C&K E101MD1ABE Grayhill 90HBW04S C&K E121SD1AGE C&K 708902000 Augat/RD1-MC6-P102-02 Samtec TSM11501SDV Samtec TSM10701SDV Samtec TSM11001SDV Samtec TSM10301SDV Molex 73138-5003 Augat PCS-032SMU-1XT Augat 214-AG19SM Augat 220-AG19SM Wieland 25.332.3353 R.N. SBE-09-S-TG30 R.N. SBE-10-S-TG30 R.N. NSH-02SB-S2-TG30 Samtec TSM10401SDV R.N. NSH-03SB-S2-TG30 Samtec TSM10301SDV Vendor Part #
Qty
MOTOROLA
B-5
B-6
MOTOROLA

DSP56301ADM: User's Manual

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DSP56301ADM

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DSP56301ADM SCHEMATICS . . . . . . . . . . . . . . . . . A-1

SECTION 1 QUICK START GUIDE

Quick Start Guide

1.1 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.2 1.4

Quick Start Guide Overview

What You Get with the DSP56301ADM

Quick Start Guide Installation Procedure

What You Need to Supply

Quick Start Guide Installation Procedure

Preparing the DSP56301ADM

Quick Start Guide Installation Procedure

Note: 5 V is on side closest to switch.

Figure 1-1 DSP56301ADM Key Component Layout

Quick Start Guide Installation Procedure

Table 1-1 DSP56301ADM Default Jumper Options

Quick Start Guide Using the DSP56301ADM

Connecting the DSP56301ADM to the PC and Power

Figure 1-2 Application Development

USING THE DSP56301ADM

SECTION 2 DSP56301ADM TECHNICAL SUMMARY

DSP56301ADM Technical Summary

DSP56301ADM Technical Summary DSP56301ADM Description and Features

DSP56301ADM DESCRIPTION AND FEATURES

DSP56301ADM Technical Summary DSP56301ADM Description and Features

Expansion & Logic Analyzer Connectors

Reset Clock Gen. & Mode sel.

64 K X 8 Flash PROM (3 V) AT29LV512 (ATMEL)

DSP56301 PORT A HI32 PORT SCI PORT SSI PORTS

3 V <-> 5 V Signals buffers

32 K 24 Static RAM MCM6706AJ12

512 K 24 DRAM MCM54800AJ70

ISA Edge Connector JTAG/OnCE PCI Edge Connector JTAG/OnCE Connector

SCI Port SSI0 and SSI1 Port & AIB I/F

Figure 2-1 DSP56301ADM Functional Block Diagram

DSP56301ADM Technical Summary DSP56301 Description

DSP56301ADM Technical Summary Memory

DSP56301ADM Technical Summary Memory

MCM6706AJ12 A0A14 A0A14 A0A14 A0A14

Flash PROM Selection

DSP56301ADM Technical Summary DSP56301 Operating Mode Selection

29F010-12 A0A16 WR RD AA1 A0A16 WE OE CE DQ0DQ7 D0D7

DSP56301 OPERATING MODE SELECTION

Figure 2-5 DSP Mode Selection

DSP56301ADM Technical Summary Clock Source Selection

Table 2-2 DSP56301 Operating Mode Selection

CLOCK SOURCE SELECTION

DSP56301ADM Technical Summary Clock Source Selection

On-Board Clock Generator Selection

Pin 8 of 14-pin socket or Pin 5 of the 8-pin socket is clock out.

DIP8 PACKAGE 1 1 2 3 4 2 5 3 6 4 U15 socket 7

Figure 2-6 3.3 V Clock Generator Assembly

External Clock Selection

Crystal Oscillator Selection

DSP56301ADM Technical Summary Host Port Selection

DSP56301 PLL Enable/Disable On Reset

PLL INIT jumper 0

HOST PORT SELECTION

DSP56301ADM Technical Summary ISA DMA and Interrupt Channels