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Prabhat Kumar Saraswat

Contact Department of Informatics and Mathematical Modelling Voice: +45.45257505

Information Richard Petersens Plads, Building 322, Room 213 Skype ID: prabhat saraswat
Technical University of Denmark E-mail: pksa@imm.dtu.dk
DK-2800, Kgs Lyngby, Denmark WWW: http://www.prabhat.2ya.com

Research System Level Design, Soft Real Time Systems, Embedded Systems, Formal Mathematics, System
Interests on Chip , Simulation Methodologies

Education Technical University of Denmark, Lyngby, Denmark

Department of Informatics and Mathematics Modeling
PhD, Embedded Systems Engineering Section, August. 2008 (expected graduation date: August
• PhD Topic: “System Level Analysis and Optimizations of Distributed Soft Real Time Em-
bedded Systems”
• Advisors: Prof. Paul Pop, Prof. Jan Madsen, DTU Informatics

ALaRI - Advanced Learning and Research Institute, Lugano, Switzerland

M. Sc., Embedded System Design, Sept. 2006 - July. 2008, GPA: 8.5/10.0
• Masters Thesis Topic: “Development of a Hybrid-Simulation Framework for MPSoC”
• Advisors: Prof. Rainer Leupers, MSc. Lei Gao, Dipl.-Ing. Stefan Kraemer, Institute for
Integrated Signal Processing Systems, RTWH Aachen, Germany

Dhirubhai Ambani Institute of Information and Communication Technology, India

B. Tech., Information and Communication Technology, May. 2002 - May. 2006, GPA: 3.23/4.0

Colonel’s Central Academy, Gurgaon, India

AISSCE (All India Secondary School Examination), Aug 2000 - May 2002, GPA: 80.2%

Honors and Best Undergraduate Paper award at IEEE Twelfth International Conference on Advanced Comput-
Awards ing and Communication (ADCOM 2004), Ahmedabad, India
Best Paper award at IEEE India Council M V Chauhan Students’ Paper Contest (INDICON 2004)
IIT Kharagpur, India
Chairman IEEE Student Branch,DA-IICT, India, 2005
IBM PowerPC Research Grant 2005: Instruction Level Power Modeling of PowerPC
Full Scholarship for Graduate Studies at ALaRI, Switzerland

Research Philips Research Labs, Aachen, Germany

Experience Research Internship Sept 2007 - March 2008
I am working as a Research Intern with Connectivity Systems Group at Philips Technologie GmbH,
Aachen. I am working on the development and extension of zigbee simulator to model a light
management sensor network. I am also involved in designing and implementation of network &
MAC layer protocols of the same.

DA-IICT, Ahmedabad, India

Research Engineer May - Aug, 2006
I worked as a Research Engineer at Embedded Systems and Sensor Networks Research Lab under
the guidance of Prof. Prabhat Ranjan, Ph.D. UC Berkeley. I designed and developed MAC layer
protocols for the wildCENSE project. I also wrote research proposals for various projects to be
funded by external government agencies.

Research Assistant Aug - Dec, 2005

I worked as a Research Assistant with Prof. Prabhat Ranjan in a project sponsored under the
IBM Linux on POWER Innovation Grant 2005. I worked on Instruction Level Power Modeling of
PowerPC Architecture. The findings are discussed in a paper published in National Conference on
Embedded Systems06.

Reliance Infocomm, Dhirubhai Ambani Knowledge City, Navi Mumbai, India

Summer Intern May - Jul, 2004
As a summer intern i worked on a project whose aim was to gain an insight into the problem of
motion estimation and tracking of multiple objects in an MPEG-4 stream. The project analyzed
the vehicular traffic using a live video feed, and sent the information on a mobile.

Bhasha Research & Publication Centre, Vadodara, India

Summer Intern May - Jul, 2003
This internship done in May-June 2003 in the tribal areas of Vadodara (India) was aimed at exploring
ICT applications to improve the conditions of the rural sector. A period of 6 weeks was spent in
villages, and several projects were taken up.

Publications Prabhat K. Saraswat, Prasoon Gupta, “Design and Implementation of a Process Scheduler Simulator
and an Improved Process Scheduling Algorithm for Multimedia Operating Systems” , In: Proceedings
of Fourteenth International Conference on Advanced Computing and Communication, Surathkal,
India, December 2006.

Prabhat K. Saraswat, N.Vinod Reddy and Prabhat Ranjan, “A Novel Approach for Instruction
Level Power Modeling of Embedded Systems” , In: Proceedings of National Conference on Embedded
Systems 2006, Mumbai, India, Feburary 2006, pp. I-1 - I-5.

Prabhat K. Saraswat, Mourya Ravuri and Prabhat Ranjan, “SeNTuMPS : A Sensor Network based
Turtle Migratory Path Monitoring System” , In: Proceedings of National Conference on Embedded
Systems 2006, Mumbai, India, Feburary 2006, pp. II-11 - II-17.

Prabhat K. Saraswat, Harshit, “Intelligent Resource Allocation and Inductive Learning Algorithms
for the Prevention of Distributed Denial of Service Attacks on a Grid Based Video on Demand System
- Extended” , In: Proceedings of IEEE Twelfth International Conference on Advanced Computing
and Communication (ADCOM 2004), Ahmedabad, India, December 2004.

Prabhat K. Saraswat, “An Alternative Multiplexing Scheme for Acoustic Leak Detection in Oil
Pipelines” , In: Proceedings of International Conference on CAD CAM Robotics and Autonomous
Factories (INCARF 2003), IIT Delhi, India, August 2003.

Prabhat K. Saraswat, “User Space Device Drivers Introduction and Implementation using VGALib
Library” , In: Proceedings of IEEE Student Paper Contest and Technical Symposium (SPCTS 2005)
, IIT Delhi, India, March 2005.

Prabhat K. Saraswat, Harshit, “Intelligent Resource Allocation and Inductive Learning Algorithms
for the Prevention of Distributed Denial of Service Attacks on a Grid Based Video on Demand
System” , In: Proceedings of IEEE India Council M V Chauhan Students’ Paper Contest (INDICON
2004), IIT Kharagpur, India, December 2004.
Prabhat K. Saraswat, “Time based Slicing and Alternative Modulation Scheme in ALDOP” , In:
IEEE Student Paper Contest and Technical Symposium (SPCTS 2003) , Ahmedabad, India, August

Papers in Prabhat K. Saraswat, Prabhat Ranjan, Ashish Kumar and Polana Swetha, “wildCENSE: Sensor
preparation Network for Wildlife Monitoring”.

Seminar Prabhat K. Saraswat, “IEEE Seminar : How to write a technical paper?” August 2006, IEEE
Presentations Student Branch, DA-IICT, India.

Research A Fast and Efficient Simulated Annealing based Design Space Exploration for a Custom VLIW
Projects Architecture for GSM Decoder and Optimizations using VEX compiler Dec, 2006 - Jan, 2007
This paper describes an attempt to find out the best custom VLIW architecture for a GSM Decoder
Application. The suitability and the efficiency of the Annealing based Design Space Exploration
Algorithm is evaluated and compared against the exhaustive exploration of the complete design
space. Source and IR level profiling is also done to understand various resource consumption patterns
of the GSM code. Various code level optimization steps are taken to enable the application to utilize
the architecture in an efficient way.

A Low Power Design of Gray and T0 Codecs for the Address Bus Encoding for System Level Power
Optimization Jan, 2007 - March, 2007
This Project describes our attempt to design the Gray and T0 codecs to be used to encode the
bits to be sent on the processor-memory address bus. The trade offs between power utilization
of the codec hardware and the power reduction due to lessening of switching transitions has also
been understood. The codecs are designed and synthesized using VHDL/Synopsis Tools. The total
power including the power consumed by the bus is calculated. Various comparisons are made with
the uncoded binary scheme. An optimum bus capacitance is also calculated which makes the usage
of codecs beneficial.

An Empirical Performance Evaluation and Modelling of BitTorrent peer-to-peer File Sharing System
using Queuing Network Models Nov, 2006 - Jan, 2007
In this project we have tried to understand the BitTorrent protocol and have performed an exper-
iment to understand the performance and incentive mechanism imbibed in the protocol. Through
the medium of empirical observation we have tried to characterize various parameters of the BitTor-
rent system so that it could be modelled using a queuing network model. We have also found the
asymptotic bounds on the performance.

Optimization of PISA Architecture for ADPCM Decoder using Simulated Annealing based Design
Space Exploration Dec, 2006 - Jan, 2007
This project describes an attempt to intelligently explore the design space of PISA architecture
using the Simplescalar and Wattch tools to optimize its power over performance metric for ADPCM
Decoder. The ADPCM code is studied and extensive profiling is done to understand the critical
resources required by the benchmark. The dependance of various parameters like cache associativity,
cache replacement policy, number of integer/float ALUs/multipliers on the performance of ADPCM
codec are studied.

Audio Feature Extraction: Tempo & Beat Analysis Apr, 2007 - May, 2007
In this project we have proposed and implemented a DSP algorithm to automatically extract beat
and tempo information from a musical piece. The algorithm is implemented as a matlab function
and the functionality was verified using various musical test pieces.

Reliance - Web Transaction Analyzer Mar, 2007 - Mar, 2007

A novel idea of measuring customer satisfaction in websites is proposed, and the ideas are assimilated
in form of a product ’Web Transaction Analyzer’. A startup company Reliance is also proposed.
This project also won Best Project at Dependable Systems Workshop, ALaRI, Lugano

Construction of a C like Compiler and Sim. for a Conceptual Architecture Dec, 2006 - Jan, 2007
The Project Development consisted of three parts. The initial part is conceptualization of the
language features, the instruction set, underlying architecture support for the instruction set, and
the binary executable file format. Then the compiler was developed from the scratch independent of
any assumptions about the underlying architecture. A simulator was also developed, which emulates
the conceptualized architecture and is capable of executing the binary executables generated by the
above compiler, on a host OS.

Design of an efficient JPEG encoder using SystemC Dec, 2006 - Jan, 2007
In this project an efficient JPEG encoder was designed and implemented using SystemC. The RTL
model for the DCT operation of the jpeg encoder was efficiently implemented using a fast DCT
approach. The throughput of the designed JPEG encoder was verified with the given SystemC
simulator for the real time behavior.

Design and Implementation of Game of Life on FPGA Feb, 2007 - Mar, 2007
In this project we have implemented John Conway’s Game of Life cellular automaton on FPGA.
Our approach draws its inspiration from the limitations of both fully parallel and fully sequential
implementations. We have proposed and implemented a new approach involving a modular design
using Control Unit and Data-path methodology. Efficient algorithms to utilize the limited memory
in FPGA were implemented.

ANT Brain modeling using VHDL Jan, 2007 - Feb, 2007

The classical problem of antbrain has been studied and a VHDL code has been developed for the
same. Synopsis’s design compiler is used to study various tradeoffs and optimizations in the resultant
circuit. After the thorough analysis of the code and the reports generated from the design compiler,
various optimization are proposed and the results are evaluated.

wildCENSE : Tracking of Wild life using Sensor Networks Jan, 2006 - May, 2006
This live project is an attempt to monitor the habitat of Indian Nilgai using mobile sensor networks.
The proposed solution collects the microclimatic as well as positional information. The system would
be integrated in the form of a collar that can be easily fitted on to the neck of animal. I worked on
its network protocols and communication aspects.

A Sensor Network based Turtle Migratory Path Monitoring Systems Aug, 2005 - Dec, 2005
An attempt to track the migratory path of turtles to help wildlife researchers to understand the
rather unusual migratory behavior of sea turtles and to propose measures to protect the nesting
grounds and habitats of these creatures and of-course, to unravel the mysteries hidden behind these
carapaces. A two tier sensor nodes based solution was proposed to track the turtles. A new dataset
storage format to store the sensed values was also proposed for the optimized memory usage.

Quality of Service for MANET using Linux Sept, 2005 - Dec, 2005
The scope of the work was to validate a given set of experiments. Hierarchical Token Bucket code
was improved upon to suit MANET since it is not specifically designed for it. The new queuing
mechanism was compared with HTB to see if improvements are possible. A comparative study
(survey) was done on various attempts to add QoS control at lower layers.

Multimedia Operating System Scheduler Simulator Feb, 2005 - May, 2005

This project involved designing of a Simulator to enable simulation of various process scheduling
algorithms and to compare their effectiveness in a multimedia environment. A new Multimedia
Scheduling algorithm was proposed which would improve the efficiency of MMOS.
Digital Logic Circuit Simulator Jan, 2005 - Apr, 2005
This project involved designing of a simulator for logic gates that allows digital circuits to be designed
and verified. It would be used by the students in the Digital Logic Course Labs at Dhirubhai Ambani
Institute of ICT, India.

Motion Estimation & Tracking Of Multiple Objects in MPEG-4 May, 2004 - Jul, 2004
The Java Media Framework Application software takes the feed from a Video Transmitter connected
to a camera and counts the no. of persons moving in the either directions at the location.

Auto-Tuning C-S application for Elphel313 Network Camera Jan, 2003 - Apr, 2003
An auto-tuning client server application for Elphel313 camera for synchronized quicktime video
retrieval. Kernel of Elphel313 camera was modified to enable direct image retrieval via a low level
networking layer. RTSP was also introduced for video streaming.

Black Hope : Blacks and the origins of music Jan, 2003 - Apr, 2003
A 20 minute documentary on the contributions of african american musicians in various genres of
music. The movie was screened in Synapse 2006, a techno-cultural festival of DA-IICT, India.

Computer Skills • Languages: C/C++, Java, Perl, PHP, Tcl/Tk Scripting, Bash scripting, VHDL, Prolog, 8085
and PowerPC Assembly language, Haskell, SystemC

• Applications: Matlab 6.5, Texas Instruments CCS, Oracle9i, Aldec ActiveHDL, PSpice, Au-
toCAD, Scilab 3.0, MySQL, PostgreSQL, GLADE, Atmels AVRStudio, NS-2 Simulator, Keil
Embedded Development Tools, ModelSIM, Leonardo Spectrum, Altera Quartus, Synopsis De-
sign Compiler, LisaTEK Processor Designer, LLVM, LATEX

• Algorithms: Experience programming Markov Chain Monte Carlo simulations, Graph color-
ing/traversal algorithms, power optimization of software and hardware, Compiler Graphs.

• Operating Systems: Linux, Sun Solaris, FreeRTOS, Windows, eCOS.

• Hardware Platforms: PowerPC, TINI microcontroller, ATMEL Microcontrollers, Mica Motes,


Personal • Chairman IEEE DA-IICT Student Branch for the year 2005.
Achievements • Overall Student Coordinator of IEEE Two day Intensive Workshop on Embedded Systems, 2005.
• Overall Student Coordinator of IEEE National Symposium on Packet Data Services in CDMA
• Founder member of Core Organization team of Synapse04 Techfest.
• Science and Technology Section Editor of ICTIAN DA-IICT College Magazine.
• Won the best project award at Dependable Systems Workshop at USI, Lugano for the project
Web Transaction Analyzer.
• (Bass Guitars/Keyboards/Manager) for my Rock Band IGNEOUS.
• Represented DA-IICT at National Rock Idols Competition at Ahmedabad. The band stood 7th.
• Won National Level Rock Music Competition as Best Band at Genesis 2004, annual festival of
National Institute of Technology, Hamirpur.
• Student Representative for DLUG DA-IICT Linux Users Group.

Personal Nationality: Indian

Information Date of Birth: 09 January, 1986
Languages Known: English (Very fluent), Hindi (Native), Danish (Intermediate), Ital-
ian (Basic), German (Basic)
References Available on Request