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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Agenda
Overview Modeling and Simulation Verification and Testing Algorithm design Advanced Systems Summary
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
SYSTEM DESIGN
Test Plans
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Open Modeling
Existing Models/Templates Custom Models : C++,SystemC,.m, HDL Model Import: MATLAB, ADS, SignalStudio, VSA, STK Recorded Data
SystemVue
Advanced Dataflow engine Co-Simulation Model Libraries Integration of SW, HW HDL Simulation FPGA Implementation
HW Implementation
Existing Modeling Templates DSP Algorithm Creation Fixed Point Simulation HDL Code Generation FPGA Synthesis
HW Test
Link to VSG/VSA/Scope/LA Integration/Controlling/Automation Custom Waveform Generation Advanced RF & BB Measurements Parameter Estimation Troubleshooting
Model more accurately across domains, verify earlier, and continue naturally into test
4 Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Agenda
Overview Modeling and Simulation Verification and Testing Algorithm design Advanced Systems Summary
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Earth
Earth Receiving Station
Satellite Transponder
Interferences
Transponder Filter
Modulation
Channel
Info Sink Signal Format Channel Decode DSP Demodulation Receiver Filter TWTA AGC
Receiver
BER Measurements
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Transponder
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Broadcast
Satellite Antenna
Multiple Receivers
Transmitter
Multiple Receivers
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Measurement-based RF modeling
Behavioral compressing amp/mixer/osc model from datasheet parameters (P2D, S2P, phase noise, etc) Measured compressing amp/mixer model (from P2D curve from a PNA-X network analyzer) X-parameter measurements from a Nonlinear VNA Digital Pre-Distortion (DPD) creates a DPD correction network, AND a memory polynomial PA model that can be used in system simulations.
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
SystemVue Dataflow
SystemVue Spectrasys
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Filter
DPD
TWTA HPA
Filter
Equalization
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Pin
Pin-pd
Input Power
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2. Capture PA Response
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
ACLR
PA input Raw PA output DPD+PA output
-2BW Lower
64.05 46.62 49.87
-1BW Lower
63.63 32.52 46.61
+1BW Upper
63.82 27.01 46.69
+2BW Upper
64.26 44.26 50.99
SourceMXG Vector AnalyzerPXA PA output Spectrum(Blue), PA+DPD Spectrum(Red) after one iteration to extract DPD coefficients
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
ADS & GoldenGate Circuits as simulated RF DUTs - Complex loading, memory FX, dynamic behaviors NVNA X-parameter measurement model, - Great for smaller solid-state devices
CO-SIM, MODELS
X-parameters
MODEL
N5241,2 PNA-X
RF DUT
MEASUREMENT-BASED DPD
89600 VSA
External Trigger
I,Q
N5182 MXG or E8257D PSG as external modulator
RF
Attenuator
RF DUT
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Agenda
Overview Modeling and Simulation Verification and Testing Algorithm design Advanced Systems Summary
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Info Source
Signal Format
Channel Encode
Modulation
Transmit Filter
High-Power Amplifier
+
Channel Interferences
Transponder Filter
Info Sink
Signal Format
Channel Decode
DSP
Demodulation
RF Receiver
TWTA
AGC
HW Receiver
MXG
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Most SV examples provide a VSA setup file (.setx), to pre-configure the software parameters
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
1. SV generates wideband I/Q data, then downloads to M8190A, 81180A, M9330/N6030 AWG 2. Wideband analog test signal formed in M8190A and sent to analog I,Q inputs of PSG signal generator 3. Wideband microwave signals actually test the Analog/RF components 4. The DUT output is captured by a VSA (PXA or Infiniium scope) and brought back to the PC for analysis using 89600 VSA, or further signal processing using SystemVue.
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Agenda
Overview Modeling and Simulation Verification and Testing Algorithm design Advanced Systems Summary
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Satellite Transponder
+
Channel Interferences
Transponder Filter
Info Sink
Signal Format
Channel Decode
DSP
Demodulation
Receiver Filter
TWTA
AGC
Receiver
BER Measurement
C++ Model
Custom .m Algorithm
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Source Models
To observe how phase noise affects system performances in simulation a typical communication system model is structured in Figure 1.
Baseband Signal
RF Modulator
Channel
RF + DSP Receiver
At the receiver input the equivalent baseband received signal can be described as
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Phase Noise
Assume that the phase noise is caused by the Oscillator in the RF modulator. As a typical example, the phase noise in (1) is modeled as a color Gaussian noise with a mean value and a power density spectrum
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Receiver Filtering
DSP Receiver
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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4.8E-1 1.1E-12
Table 1. BER for the S Band Satellite system with 10 dB of Eb/No for Additive Noise (plus -40 dBm for phase noise)
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Agenda
Overview Modeling and Simulation Verification and Testing Algorithm design Advanced Systems Summary
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
SystemVue ADS
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
DSSS QPSK Receiver: Timing and Frequency synchronization, Channel estimator and Rake
combiner.
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
It will be extended to other DSSS system (such as OQPSK, 8-PSK, 16-QAM and etc).
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Block
Block
OFDM symbol
OFDM symbol
Block
Block
OFDM symbol
OFDM symbol
There are two kinds of pilots (Pilot1 and Pilot2) supported in Data 1 and Data 2. Both Pilot1 and Pilot2 can be turned ON/OFF.
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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The above figure is from Ludong Wang and Jezek Bs paper, OFDM modulation schemes for military satellite communications, IEEE MILCOM 2008.
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Agenda
Overview Modeling and Simulation Verification and Testing Algorithm design Advanced Systems Summary
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
Summary
SystemVue provides a platform solution for designing and verification of satellite communication systems
o Modeling integration: SV integrates all SW models in C++, MATLAB code, math language, HDL code, together as a system. Without the integration, each different modeling format makes system-level PHY verification very difficult. o Test integration: SV integrates test instruments together as a system test tool. Without integration, each HW instrument only provides individual functionality. SystemVue integrates powerful system-level verification suites in software and hardware. o Unique Value: From functionality point of view Agilent Design-Verification-Test provides unique value in the following areas Embedded reference transmitters and receivers, to validate your systems earlier Custom waveform generation and integration of user IP, to customize test systems More sophisticated system-level measurements, including closed-loop tests, and tests of partial systems
Contact Agilent about SystemVues Early Access Program to evaluate new SatComm and SatNav capabilities http://www.agilent.com/find/eesof-systemvue-earlyaccess
Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
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At the websites above, Select Contact an Expert to get further information, or Contact your local Agilent EEsof EDA sales representative.
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification
References
1. S. Benedetto, E. Biglieri, and V. Castellani, " Digital trunsmission theory, Prentice Hall International, Englewood Cliffs. New Jersey, 1987. D. Lu and K. Yao, "Estimation Variance Bounds of Importance Sampling Simulations in Digital Communication Systems," IEEE Trans. On Communications vol. 39, Oct., 1991, pp 1413-1417. Dingqing Lu, Quasi-Analytical Method For Estimating low False Alarm Rate, EuRAD2010, 2010. Dingqing Lu and Zhengrong Zhou, "Integrated Solutions for testing Wireless Communication Systems," IEEE Com Mag, June, 2011
Authors contact information: dingqing_lu@agilent.com
2.
3. 4.
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Copyright 2012 Agilent Technologies June 7, 2012 Webcast: System-Level Satellite Design & Verification