ANALOG ICs

Use analog for better performance-to-power ratios

Paul McCormack Senior Product Applications Engineer National Semiconductor Corp.

Traditionally, analog IC designers boosted supply voltages and operating current to maximize device speed of operation and dynamic range. But that is no longer possible in todays energy-conscious world. Maximum frequency of operation, useable bandwidth, noise performance and dynamic range must continually improve while power consumption remains flat or decreases. In short, the industry is demanding components with better performance-to-power ratios. National Semiconductors PowerWise products are developed using novel architectures on state of the art manufacturing processes resulting in industry leading performance at exceptionally low power consumption. Using the reference design platform shown in Figure 1, this article demonstrates how a complete analog system can be developed using energy-efficient ADCs, fully differential amplifiers and clock conditioning circuits. Tailored to fit A given process technology designed for ADC development will not necessarily be suitable for developing high frequency low noise amplifiers. In fact, normally companies use several different process technologies, CMOS, BiCMOS, SiGe etc. depending on the desired component parameters. Exceptional circuit design alone is inadequate without exceptional process technologies. Nationals Advanced Process Technology Development group develops highly characterized and modeled, manufacturable and reliable, innovative and differentiated process technologies. Special transistors are

engineered in-house on several process technologies to achieve optimal analog performance at low power consumption. National uses pure CMOS technology for the design of many of it latest ADCs. CMOS is ubiquitous today because CMOS logic gates dissipate no static power yet have high drive current and speed. Considering ADCs contain a high percentage of digital circuits, realizing the circuit design on pure CMOS technology results in lower power consumption compared to a chip designed, for example, on a BiCMOS process. Digital CMOS gates consume no current in DC mode. Digital bipolar gates on the other hand consume current even in DC mode as bias currents are required to maintain performance parameters. The result is higher current consumption for the digital portion of the chip leading to higher total power consumption. National has also specially developed processes such as VIP10 for amplifier IC design. VIP10 is a high-speed, dielectrically isolated, complementary bipolar IC process that utilizes deep trench technology on a bonded wafer for complete dielectric isolation and optimal high-speed amplifier performance. Trench technology with bonded wafers helps minimize parasitic capacitance for optimal power-to-bandwidth performance, lower distortion and decreased die size. Complementary bipolar transistor designs, by using high-performance NPN and PNP transistors, can offer the best combinations of features required in todays high speed amplifiers: high bandwidth, low power consumption, low supply voltages, large output swing, high output current and low distortion. The most common AC figure of merit for a bipolar transistor is the transition frequency (FT) which is the

Figure 1: This reference design platform shows a complete analog system developed using ADCs, fully differential amplifiers and clock conditioning circuits.

frequency at which the commonemitter current gain decreases to unity. The FT of the VIP10 NPN and PNP at Vce=5V are 9GHz and 8GHz respectively, about 50 percent higher than on competitive processes. The transistor FT being high means that its emitter-base diffusion capacitance will be low for a given operating point. With VIP10 transistors, National can design amplifiers either with bandwidths exceeding 1GHz or with bandwidths in the 100MHz range with very low power consumption. This is because the internal stages will have low phase shifts even at very low operating currents, since both diffusion and parasitic capacitances have been greatly reduced. FT can dramatically decrease at lower voltages on some bipolar process. But FTs on VIP10 remain high at Vce=1V: 7GHz for the NPN and 5GHz for the PNP. Equation 1 shows how

the transition frequency of a bipolar transistor can be calculated.

where;

k is Boltzmanns constant, T is absolute temperature, Cte is the emitter capacitance, q is the unit charge of an electron, IC is the collector current, WB is the base width, B is the electron mobility, rcs is the collector resistance, Ccb is the col-

EE Times-Asia | May 1-15, 2008 | eetasia.com

lector capacitance, Xs is the width of collector space charge region, and vx is the saturation speed of the collector space charge region. Innovative technology We have seen above that best circuit design practices, patented architectures and the latest process technology enable IC designers to engineer industry-leading technology. Such technology empowers system developers to differentiate their products in highly competitive markets. To gain a further edge over their competition system architects demand access to further industry developments. Innovations such as Nationals PowerWise technology allow DSP or FPGA power consumption in digital processors to be reduced by up to 70 percent. PowerWise uses techniques such as adaptive voltage scaling (AVS) and threshold scaling to automatically minimize active and leakage power in digital logic ICs with minimal system overhead. PowerWise technology is unique in the industry in that it is the only advanced system-level energy management solution available to all IC developers as comprehensive and well documented intellectual property packages. The use of simple standard hardware interfaces and Nationals collaboration with industry leaders such as ARM, TSMC, UMC and Synopsys ensures that this technology can be used on any CMOS process, with standard design tools and flows, and can be integrated with any OS or application yet resulting in exceptional energy efficiency. Build analog systems Reference designs are important in providing engineers a template for good design practices especially when looking to increase performance without increasing power consumption. Much of the difficult design issues such as proper component selection and placement, layout and routing are provided in these reference designs. Building on the knowledge gained from helping customers

Figure 2: The ADC14DS105KARB is a low IF receiver subsystem reference design board that enables immediate evaluation of a quadrature direct conversion.

create high-performance analog systems, National provides a library of reference designs that illustrate best system performance. An example is the latest addition to this librarythe ADC14DS105KARB Reference Design which uses the new LMH6552 1.5GHz differential driver from the PowerWise family as part of the signal chain. This component in combination with the High-Speed ADC14DS105 data converter and timing solutions provide a great starting place for engineers involved in designing instrumentation. Reference design board The ADC14DS105KARB is a nearzero IF receiver reference design board that utilizes the following components: Two LMH6552 1.5GHz bandwidth differential current feedback amplifiers; ADC14DS105 14bit, 1GHz, Dual 105MSps ADC with serial LVDS outputs; LMK02000 low-jitter precision clock conditioner with an integrated PLL that provides 128fs

jitter over an integration bandwidth of 100Hz to 20MHz; Several energy-efficient power management ICs.

The ADC14DS105KARB is a low IF receiver subsystem reference design board (Figure 2) that utilizes a pair of LMH6552 differential drivers and a dual ADC to enable immediate evaluation of a quadrature direct conversion or near-zero IF receiver for signal frequencies from DC to 40MHz. This receiver architecture is commonly used in WiMAX and WCDMA receiver systems. The 1Hz input bandwidth of the ADC and the 1.5GHz differential amplifier gain stage enable a large SNR of 73.3dB full scale (dBFS) and spurious free dynamic range (SFDR) greater than 85dBFS for input signals up to 40MHz. In addition to the LMH6552, the board includes the new ADC14DS105 dual 14bit, 105MSps low-distortion, low-noise ADC with serialized LVDS outputs; LMK02000 low-jitter clock conditioner; as well as several energyefficient power management ICs.

The LMH6552 is a high-performance fully differential amplifier designed to provide the exceptional signal fidelity and wide large-signal bandwidth necessary for driving 14bit high-speed data acquisition systems. Using a proprietary differential current mode input stage architecture; the LMH6552 allows operation at gains greater than unity without sacrificing response flatness, bandwidth, harmonic distortion, or output noise performance. With external gain set resistors and integrated common mode feedback, the LMH6552 can be configured as either a differential input to differential output or single ended input to differential output gain block. The LMH6552 can be AC- or DC-coupled at the input that makes it suitable for a wide range of applications including communication systems and high-speed oscilloscope front ends. The current feedback topology of the LMH6552 offers gain and bandwidth independence with exceptional gain flatness and

eetasia.com | May 1-15, 2008 | EE Times-Asia

noise performance, even at high values of gain, simply with the appropriate choice of the feedback resistors (RF1, RF2). In most of the applications RF1 is set equal to RF2, so the gain is set by the ratio RF /RG. The LMH6512 datasheet suggests the optimum value of feedback resistors for various gains. An excessively large or small RF will compromise stability. Within reason, the feedback resistor can be used to adjust the frequency response One hidden advantage of current feedback amplifiers is that they usually require fewer internal gain stages than their voltage feedback counterparts. Often a current feedback amplifier consists of merely an input buffer, one gain stage and an output buffer. Having fewer stages means less delay through the open-loop circuit. This translates into higher bandwidth for the same power! The basic current feedback topology in Figure 3 is a singlestage amplifier. The only high impedance node in the circuit is at the input to the output buffer. Voltage feedback amplifiers usually require two or more stages

for sufficient loop-gain. These additional stages add delay and yield lower stable bandwidths. Figure 4 illustrates the reference board configuration for the amplifiers. The inputs are 50, DC-coupled. The LMH6552 is configured for the single-ended-todifferential mode conversion. The VCOM output of the ADC14DS105 is used as the common mode input to the amplifier. Each amplifier is configured for 6dB of gain, so the maximum input signal level is 1Vp-p, producing 2Vp-p at the output of the amplifier. It is recommended that the amplifiers be powered by dual supply rails (<P/M>5VDC), but the board can also be configured to operate in single supply mode by installing jumpers at VCCAA- and VCCAB-. Refer to the LMH6552 datasheet for a description of operating the LMH6552 with a single supply. To obtain the best SFDR, a low noise signal generator is recommended to drive the signal inputs of the evaluation board. The output of the signal generator should be bandpass filtered to suppress any harmonic distortion produced by the signal generator and to allow accurate measurement of the

Figure 3: The basic current feedback topology shown is a single-stage amplifier.

noise and distortion performance. The 43MHz 5th order low pass filter following the LMH6552 will further improve the noise performance of the ADC by filtering the broadband noise of the signal generator. The filter output is sampled by the ADC. The ADC14DS105 is the worlds first 14bit high-speed, 1GHz full power bandwidth, DUAL ADC

with serialised LVDS outputs. The serialised LVDS outputs greatly simplify board layout by significantly reducing the number of traces that have to be routed across or between PCBs. The ADC clock used to sample the analog inputs is generated using a voltage-controlled crystal oscillator (VCXO) controlled by the LMK02000 precision clock condi-

Figure 4: The reference board configuration for the amplifiers is shown. The LMH6552 is configured for the single-ended-to-differential mode conversion.

EE Times-Asia | May 1-15, 2008 | eetasia.com

tioner. The LMK02000 gives the user an ultralow noise PLL paired with a clock distribution section that provides five low-voltage positive emitter coupled logic (LVPECL) outputs and three LVDS outputs (all differential). Each clock output channel on the LMK02000 contains a divider block and delay adjustment clock. The LMK02000 is typically paired with a low jitter VCXO, in this case the Crystek model CVHD-950X100.0, which provides a singleended CMOS clock driving the ADC clock input. The LMK02000 PLL locks this VCXO to a 25MHz reference oscillator (ConnorWinfield model CWX823). The PLL counters, phase detector and charge pump of the LMK02000 are programmed using the PIC microcontroller board as discussed in users guide. The LMK02000 achieves 128fs RMS jitter (integrated from 100Hz to 20MHz). Figure 5 illustrates the phase noise performance of the clock, measured at CLKout4 of the LMK02000. The single-ended clock signal from the VCXO is applied to the CLK input on the ADC14DS105. The LMK02000X precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a high-performance Integer-N PLL, a partially integrated loop filter, three LVDS, and five LVPECL clock output distribution blocks. The combined channel response of the differential amplifier, bandpass filter and ADC is shown in Figure 6. Note the excellent dynamic performance and matching between channels.

Figure 5: The phase noise performance of the clock as measured at CLKout4 of the LMK02000 is shown.

Figure 6: Typical SFDR and SNR performance against input frequency is shown.

eetasia.com | May 1-15, 2008 | EE Times-Asia