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CPS104 Lec17.1
GK Spring 2004
Admin.
Homework-3 Due Feb. 23rd 11:59 pm. C++ version is posted. Start NOW!
CPS104 Lec17.2
GK Spring 2004
s
a
Y Y = (A * S) + (B * ~S)
S
CPS104 Lec17.3
GK Spring 2004
0 1
a b c d
3 2
y
C
1 0
1 0
S S0 S1
CPS104 Lec17.4
GK Spring 2004
I1 I0 Q0 Q1 Q2 Q3
Q2
0 0 0 1
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
Q1
1 0 1 1
Q0
CPS104 Lec17.5
I1
I0
GK Spring 2004
Cout
a 0 0 0 0 1 1 1 1
b 0 0 1 1 0 0 1 1
Cin 0 1 0 1 0 1 0 1
Sum 0 1 1 0 1 0 0 1
Cout 0 0 0 1 0 1 1 1
GK Spring 2004
CPS104 Lec17.6
S3 Cout
Full Adder
S2
Full Adder
S1
Full Adder
S0
Full Adder
b3 a3
b2 a2
b1
a1
b0
a0
CPS104 Lec17.7
GK Spring 2004
Example: Adder/Subtractor
S3 Cout
Full Adder
S2
Full Adder
S1
Full Adder
S0
Full Adder
Add/Sub b3 a3 b2 a2 b1 a1 b0 a0
CPS104 Lec17.8
GK Spring 2004
Overflow Example1: 0100000 01101012 (= 5310) +01010102 (= 4210) 10111112 (=-3310) Example3: 1100000 01101012 (= 5310) +11010102 (=-2210) 00111112 (= 3110)
CPS104 Lec17.9
Example2: 1000000 10101012 (=-4310) +10010102 (=-5410) 00111112 (= 3110) Example4: 0000000 00101012 (= 2110) +01010102 (= 4210) 01111112 (= 6310)
GK Spring 2004
Sn- 1
Full Adder
Sn- 2
Full Adder
S1
S0
Full Adder
Full Adder
CPS104 Lec17.10
GK Spring 2004
ALU Slice
Cin 3
a b
2 1
A 0 1 -
F 0 0 1 2 3
Add/sub
0 2
Cout Add/sub
CPS104 Lec17.11
F
GK Spring 2004
The ALU
Overflow
= Zero
Qn-1
Qn-2
Q1
Q0
ALU control
ALU Slice
ALU Slice
ALU Slice
ALU Slice
bn-1 an-1
bn-2 an-2
b1
a1
b0
a0
CPS104 Lec17.12
GK Spring 2004
Shifter
a7 a6 a5 a4 a3 a2 a1 a0
Shift-1
Shift-2
Shift-4
1
Q7
CPS104 Lec17.13
Q6
Q5
Q4
Q3
Q2
Q1
Q0
GK Spring 2004
Memory Elements
All the circuit we looked at so far are combinational circuits: the output is a Boolean function of the inputs. We need circuits that can remember values. (registers) The output of the circuit is a function of the input AND a function of a stored values (state) . Circuits with memory are called sequential circuits.
CPS104 Lec17.14
GK Spring 2004
Rest-Set Latch
S Q
Q R
R 0 0 1 1
S 0 1 0 1
Q Q 1 0 -
CPS104 Lec17.15
GK Spring 2004
0 1 0
S0 Q
1
1 0
Q R
0 1 0
CPS104 Lec17.16
GK Spring 2004
S1
1
S Q
0 1 0
0 1
Q R
1 0 1
CPS104 Lec17.17
GK Spring 2004
Q Enable Q
D 0 1 -
E 1 1 0
Q 0 1 Q
D E
Q
CPS104 Lec17.18
Time
GK Spring 2004
Data
Enable Q
D 0 1 -
E 1 1 0
Q 0 1 Q
E Q Time
CPS104 Lec17.19
GK Spring 2004
Master-Slave Data-Flip-Flop
Data
Master
Slave
Q
Clock
t
On C
On C the Master stage is transferred into the slave stage (output), and the master stage is stable.
GK Spring 2004
CPS104 Lec17.20
DFF Timing
Data Q M Q
Clock
Clock
1 0 0 1 0 1 1 0
M
1 0 0 1 0 1 1 0
Time
CPS104 Lec17.21
GK Spring 2004