CPS 104 Computer Organization and Programming Lecture- 20: Building a Datapath

Feb 25, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

CPS104 Lec20.1

GK Spring 2004

Admin.

Homework-4 is posted. Due March. 1st. In class. Midterm Exam March 5th. u In Class u 1 hour u Closed books u Covers all material including Data-path. u Bring SPIM manual and/or Common MIPS Instructions. Wednesday March 3, Review Session u Bring questions about ANY topic we covered in the course.

CPS104 Lec20.2

GK Spring 2004

The Big Picture: Where are We Now?

The Five Classic Components of a Computer

Processor Input Control Memory Datapath

Output

Todays Topic: Datapath Design

CPS104 Lec20.3

GK Spring 2004

Review: RTL: The ADD Instruction

add rd, rs, rt

u

mem[PC] R[rd] <- R[rs] + R[rt] PC <- PC + 4

Fetch the instruction from memory The ADD operation

Calculate the next instructions address

CPS104 Lec20.4

GK Spring 2004

Review: RTL: The Load Instruction

lw
u

rt, rs, imm16 mem[PC] Fetch the instruction from memory

Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr] PC <- PC + 4 Load the data into the register

Calculate the next instructions address

CPS104 Lec20.5

GK Spring 2004

Review: Combinational Logic Elements (Basic Building Blocks)

CarryIn A

32

Adder

Adder
B 32 Select A B 32 32 OP A 32

32

Sum Carry

MUX

MUX ALU

32

ALU
B

32

Result Zero
GK Spring 2004

CPS104 Lec20.6

32

Review: Storage Element: Register (Basic Building Block)

Register u Similar to the D Flip Flop except

u

Write Enable

N-bit input and output Shared Write Enable input

Data In N

Data Out N

Write Enable:

negated (0): Data Out will not change asserted (1): Data Out will become the same as Data In.

Clk

CPS104 Lec20.7

GK Spring 2004

Review: Clocking Methodology

Clk Setup Hold Dont Care Setup Hold

. . .

. . .

. . .

. . .

All storage elements are clocked by the same clock edge Cycle Time >= CLK-to-Q + Longest Delay Path + Setup + Clock Skew

CPS104 Lec20.8

GK Spring 2004

Storage Element: Register File

Register File consists of 32 registers: busA u Two 32-bit output busses: busW 32 32 32-bit busA and busB 32 Registers busB u One 32-bit input bus: busW Clk 32 Register is selected by: u RA selects the register to put on busA u RB selects the register to put on busB u RW selects the register to be written via busW when Write Enable is 1 Clock input (CLK) u The CLK input is a factor ONLY during write operation u During read operation, behaves as a combinational logic block:

RW RA RB Write Enable5 5 5

RA or RB valid => busA or busB valid after access time.

GK Spring 2004

CPS104 Lec20.9

Storage Element: Idealized Memory

Write Enable

Address

Memory (idealized) Data In DataOut u One input bus: Data In 32 32 u One output bus: Data Out Clk Memory word is selected by: u Write Enable = 0: Address selects the word to put on the Data Out bus u Write Enable = 1: Address selects the memory word to be written via the Data In bus Clock input (CLK) u The CLK input is a factor ONLY during write operation u During read operation, behaves as a combinational logic block:

Address valid => Data Out valid after access time.

CPS104 Lec20.10

GK Spring 2004

Overview of the Instruction Fetch Unit

The common RTL operations u Fetch the Instruction: mem[PC] u Update the program counter:

Sequential Code: PC <- PC + 4 Branch and Jump: PC <- something else

Clk

PC Next Address Logic Address Instruction Memory

Instruction Word 32

CPS104 Lec20.11

GK Spring 2004

RTL: The ADD Instruction

31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

add rd, rs, rt

u

mem[PC] R[rd] <- R[rs] + R[rt] PC <- PC + 4

Fetch the instruction from memory The actual operation

Calculate the next instructions address

CPS104 Lec20.12

GK Spring 2004

RTL: The Subtract Instruction

31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

sub rd, rs, rt

u

mem[PC] R[rd] <- R[rs] - R[rt] PC <- PC + 4

Fetch the instruction from memory The actual operation

Calculate the next instructions address

CPS104 Lec20.13

GK Spring 2004

Datapath for Register-Register Operations

R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt u Ra, Rb, and Rw comes from instructions rs, rt, and rd fields u ALUctr and RegWr: control logic after decoding the instruction fields: op and func
31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits ALUctr busA 32 busB 32 Result 32 ALU 6 funct 6 bits 0

Rd Rs Rt RegWr 5 5 5 busW 32 Clk Rw Ra Rb 32 32-bit Registers

CPS104 Lec20.14

GK Spring 2004

Register-Register Timing
Inst fetch
Clk PC Old Value Rs, Rt, Rd, Op, Func Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value

Decode Opr. fetch Execute

Write Back

ALUctr RegWr busA, B busW

Rd Rs Rt RegWr 5 5 5 busW 32 Clk

CPS104 Lec20.15

ALUctr busA 32 busB 32 ALU Result 32

Rw Ra Rb 32 32-bit Registers

Register Write Occurs Here

GK Spring 2004

RTL: The OR Immediate Instruction

31 26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

ori rt, rs, imm16

u

mem[PC]

Fetch the instruction from memory The OR operation

R[rt] <- R[rs] OR ZeroExt(imm16) PC <- PC + 4

Calculate the next instructions address

31 0000000000000000 16 bits
CPS104 Lec20.16

16 15 immediate 16 bits

GK Spring 2004

Datapath for Logical Operations with Immediate

R[rt] <- R[rs] op ZeroExt[imm16]]

31 26 op 6 bits Rd RegDst
1 Mux 0

Example: ori
immediate 16 bits

rt, rs, imm16

0

21 rs 5 bits Rt Rs 5 5

16 rt 5 bits

RegWr 5 busW 32 Clk

Dont Care (Rt) busA 32 busB 32 ZeroExt

0

ALUctr

Rw Ra Rb 32 32-bit Registers

Result 32

ALU

Mux
1

imm16

16

32 ALUSrc
GK Spring 2004

CPS104 Lec20.17

RTL: The Load Instruction

31

26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

lw
u

rt, rs, imm16 mem[PC]

Fetch the instruction from memory

Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register PC <- PC + 4
31

Calculate the next instructions address

0 immediate 16 bits 0 immediate 16 bits

16 15 0 0000000000000000 16 bits 16 15 1111111111111111 1 16 bits

31

CPS104 Lec20.18

GK Spring 2004

Datapath for Load Operations

R[rt] <- Mem[R[rs] + SignExt[imm16]] imm16 31 26 21 16

op 6 bits Rd RegDst Rt Rs 5 5 Dont Care (Rt) busA 32 busB 32 Extender 32 ALUSrc
0

Example: lw
0

rt, rs,

rs 5 bits

rt 5 bits

immediate 16 bits

1 Mux 0

RegWr 5 busW 32 Clk

ALUctr MemtoReg
0

Rw Ra Rb 32 32-bit Registers

ALU

Mux

32 MemWr WrEn Adr

32

Mux Data In 32 Clk

imm16

16

Data Memory

CPS104 Lec20.19

GK Spring 2004

ExtOp

RTL: The Store Instruction

31 26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

sw rt, rs, imm16

u

mem[PC]

Fetch the instruction from memory

Addr <- R[rs] + SignExt(imm16) Calculate the memory address Mem[Addr] <- R[rt] PC <- PC + 4 Store the register into memory Calculate the next instructions address

CPS104 Lec20.20

GK Spring 2004

Datapath for Store Operations

Mem[R[rs] + SignExt[imm16] ] <- R[rt] sw rt, rs, imm16

31 26 op 6 bits Rd Rt Rs Rt 5 5 busA 32 busB 32 Extender 32
0

21 rs 5 bits

16 rt 5 bits immediate 16 bits

RegDst

1 Mux 0

RegWr 5 busW 32 Clk

ALUctr MemWr ALU MemtoReg

Rw Ra Rb 32 32-bit Registers

Mux

32 32 WrEn Adr

Mux Data In 32 ALUSrc Clk

imm16

16

Data Memory

CPS104 Lec20.21

ExtOp

GK Spring 2004

RTL: The Branch Instruction

31 26 op 6 bits

21 rs 5 bits

16 rt 5 bits immediate 16 bits

beq rs, rt, imm16

u

mem[PC] Cond <- R[rs] - R[rt] if (COND eq 0)

Fetch the instruction from memory Calculate the branch condition

Calculate the next instructions address

PC <- PC + 4 + ( SignExt(imm16) x 4 ) PC <- PC + 4

else

CPS104 Lec20.22

GK Spring 2004

Datapath for Branch Operations

beq

rs, rt, imm16

31 26 op 6 bits Rd Rt Rs Rt 5 5 busA 21 rs 5 bits

We need to compare Rs and Rt!

16 rt 5 bits immediate 16 bits Branch Clk 0

RegDst

PC

1 Mux 0

RegWr 5 busW 32 Clk

ALUctr

imm16 16

Next Address Logic

Rw Ra Rb 32 32-bit Registers

32 busB 32 Extender 32 ALUSrc

0

ALU

Zero

To Instruction Memory

Mux

imm16

16

CPS104 Lec20.23

GK Spring 2004

ExtOp

Binary Arithmetic for the Next Address

In theory, the PC is a 32-bit byte address into the instruction memory: u Sequential operation: PC<31:0> = PC<31:0> + 4 u Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4 The magic number 4 always comes up because: u The 32-bit PC is a byte address u And all our instructions are 4 bytes (32 bits) long In other words: u The 2 LSBs of the 32-bit PC are always zeros u There is no reason to have hardware to keep the 2 LSBs In practice, we can simplify the hardware by using a 30-bit PC<31:2>: u Sequential operation: PC<31:2> = PC<31:2> + 1 u Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16] u In either case: Instruction-Memory-Address = PC<31:2> concat 00
GK Spring 2004

CPS104 Lec20.24

Next Address Logic: Expensive and Fast Solution

Using a 30-bit PC: u Sequential operation: PC<31:2> = PC<31:2> + 1 u Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16] u In either case: Instruction-Memory-Address = PC<31:2> concat 00
30 30 30 1 Clk imm16 Instruction<15:0> 16 SignExt 00 0 30 Adder Mux Adder Addr<31:2> Addr<1:0> Instruction Memory 32 PC

1 30

30

Instruction<31:0> Branch Zero

GK Spring 2004

CPS104 Lec20.25

Next Address Logic

30 30 0 Clk imm16 Instruction<15:0> 16 0 Mux Addr<31:2> Addr<1:0> Instruction Memory 32 PC

1 Carry In Adder

00

1 30 30

30

SignExt

Instruction<31:0> Branch Zero

CPS104 Lec20.26

GK Spring 2004

RTL: The Jump Instruction

31 26 op 6 bits target address 26 bits 0

j
u

target mem[PC] Fetch the instruction from memory

PC<31:2> <- PC<31:28> concat target<26:0> concat <00> Calculate the next instructions address

CPS104 Lec20.27

GK Spring 2004

Instruction Fetch Unit

j
u

target PC<31:2> <- PC<31:28> concat target<25:0>

30 PC<31:28> Target Instruction<25:0> PC Clk 30 1 4 30 26 0 30 Adder Mux 30 00 1 Mux 0 Addr<31:2> Addr<1:0> Instruction Memory 32

Adder SignExt 30

1 30

Jump

Instruction<31:0>

imm16 Instruction<15:0> 16

Branch
CPS104 Lec20.28

Zero
GK Spring 2004

Putting it All Together: A Single Cycle Datapath

We have everything except control signals.

Branch Rd RegDst Rt Rs 5 5 busA 32 0 Mux ALU Rt Jump Clk Instruction Fetch Unit

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

1 Mux 0 RegWr 5 ALUctr

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

1 32

imm16

Data In 32 Clk

16

Data Memory

ALUSrc
CPS104 Lec20.29

ExtOp

GK Spring 2004